1/* 2 * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#ifndef EL3_COMMON_MACROS_S 8#define EL3_COMMON_MACROS_S 9 10#include <arch.h> 11#include <asm_macros.S> 12 13 /* 14 * Helper macro to initialise EL3 registers we care about. 15 */ 16 .macro el3_arch_init_common 17 /* --------------------------------------------------------------------- 18 * SCTLR_EL3 has already been initialised - read current value before 19 * modifying. 20 * 21 * SCTLR_EL3.I: Enable the instruction cache. 22 * 23 * SCTLR_EL3.SA: Enable Stack Alignment check. A SP alignment fault 24 * exception is generated if a load or store instruction executed at 25 * EL3 uses the SP as the base address and the SP is not aligned to a 26 * 16-byte boundary. 27 * 28 * SCTLR_EL3.A: Enable Alignment fault checking. All instructions that 29 * load or store one or more registers have an alignment check that the 30 * address being accessed is aligned to the size of the data element(s) 31 * being accessed. 32 * --------------------------------------------------------------------- 33 */ 34 mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT) 35 mrs x0, sctlr_el3 36 orr x0, x0, x1 37 msr sctlr_el3, x0 38 isb 39 40#ifdef IMAGE_BL31 41 /* --------------------------------------------------------------------- 42 * Initialise the per-cpu cache pointer to the CPU. 43 * This is done early to enable crash reporting to have access to crash 44 * stack. Since crash reporting depends on cpu_data to report the 45 * unhandled exception, not doing so can lead to recursive exceptions 46 * due to a NULL TPIDR_EL3. 47 * --------------------------------------------------------------------- 48 */ 49 bl init_cpu_data_ptr 50#endif /* IMAGE_BL31 */ 51 52 /* --------------------------------------------------------------------- 53 * Initialise SCR_EL3, setting all fields rather than relying on hw. 54 * All fields are architecturally UNKNOWN on reset. The following fields 55 * do not change during the TF lifetime. The remaining fields are set to 56 * zero here but are updated ahead of transitioning to a lower EL in the 57 * function cm_init_context_common(). 58 * 59 * SCR_EL3.TWE: Set to zero so that execution of WFE instructions at 60 * EL2, EL1 and EL0 are not trapped to EL3. 61 * 62 * SCR_EL3.TWI: Set to zero so that execution of WFI instructions at 63 * EL2, EL1 and EL0 are not trapped to EL3. 64 * 65 * SCR_EL3.SIF: Set to one to disable instruction fetches from 66 * Non-secure memory. 67 * 68 * SCR_EL3.SMD: Set to zero to enable SMC calls at EL1 and above, from 69 * both Security states and both Execution states. 70 * 71 * SCR_EL3.EA: Set to one to route External Aborts and SError Interrupts 72 * to EL3 when executing at any EL. 73 * 74 * SCR_EL3.{API,APK}: For Armv8.3 pointer authentication feature, 75 * disable traps to EL3 when accessing key registers or using pointer 76 * authentication instructions from lower ELs. 77 * --------------------------------------------------------------------- 78 */ 79 mov_imm x0, ((SCR_RESET_VAL | SCR_EA_BIT | SCR_SIF_BIT) \ 80 & ~(SCR_TWE_BIT | SCR_TWI_BIT | SCR_SMD_BIT)) 81#if CTX_INCLUDE_PAUTH_REGS 82 /* 83 * If the pointer authentication registers are saved during world 84 * switches, enable pointer authentication everywhere, as it is safe to 85 * do so. 86 */ 87 orr x0, x0, #(SCR_API_BIT | SCR_APK_BIT) 88#endif 89 msr scr_el3, x0 90 91 /* --------------------------------------------------------------------- 92 * Initialise MDCR_EL3, setting all fields rather than relying on hw. 93 * Some fields are architecturally UNKNOWN on reset. 94 * 95 * MDCR_EL3.SDD: Set to one to disable AArch64 Secure self-hosted debug. 96 * Debug exceptions, other than Breakpoint Instruction exceptions, are 97 * disabled from all ELs in Secure state. 98 * 99 * MDCR_EL3.SPD32: Set to 0b10 to disable AArch32 Secure self-hosted 100 * privileged debug from S-EL1. 101 * 102 * MDCR_EL3.TDOSA: Set to zero so that EL2 and EL2 System register 103 * access to the powerdown debug registers do not trap to EL3. 104 * 105 * MDCR_EL3.TDA: Set to zero to allow EL0, EL1 and EL2 access to the 106 * debug registers, other than those registers that are controlled by 107 * MDCR_EL3.TDOSA. 108 * 109 * MDCR_EL3.TPM: Set to zero so that EL0, EL1, and EL2 System register 110 * accesses to all Performance Monitors registers do not trap to EL3. 111 * 112 * MDCR_EL3.SCCD: Set to one so that cycle counting by PMCCNTR_EL0 is 113 * prohibited in Secure state. This bit is RES0 in versions of the 114 * architecture earlier than ARMv8.5, setting it to 1 doesn't have any 115 * effect on them. 116 * --------------------------------------------------------------------- 117 */ 118 mov_imm x0, ((MDCR_EL3_RESET_VAL | MDCR_SDD_BIT | \ 119 MDCR_SPD32(MDCR_SPD32_DISABLE) | MDCR_SCCD_BIT) \ 120 & ~(MDCR_TDOSA_BIT | MDCR_TDA_BIT | MDCR_TPM_BIT)) 121 122 msr mdcr_el3, x0 123 124 /* --------------------------------------------------------------------- 125 * Enable External Aborts and SError Interrupts now that the exception 126 * vectors have been setup. 127 * --------------------------------------------------------------------- 128 */ 129 msr daifclr, #DAIF_ABT_BIT 130 131 /* --------------------------------------------------------------------- 132 * Initialise CPTR_EL3, setting all fields rather than relying on hw. 133 * All fields are architecturally UNKNOWN on reset. 134 * 135 * CPTR_EL3.TCPAC: Set to zero so that any accesses to CPACR_EL1, 136 * CPTR_EL2, CPACR, or HCPTR do not trap to EL3. 137 * 138 * CPTR_EL3.TTA: Set to zero so that System register accesses to the 139 * trace registers do not trap to EL3. 140 * 141 * CPTR_EL3.TFP: Set to zero so that accesses to the V- or Z- registers 142 * by Advanced SIMD, floating-point or SVE instructions (if implemented) 143 * do not trap to EL3. 144 */ 145 mov_imm x0, (CPTR_EL3_RESET_VAL & ~(TCPAC_BIT | TTA_BIT | TFP_BIT)) 146 msr cptr_el3, x0 147 148 /* 149 * If Data Independent Timing (DIT) functionality is implemented, 150 * always enable DIT in EL3 151 */ 152 mrs x0, id_aa64pfr0_el1 153 ubfx x0, x0, #ID_AA64PFR0_DIT_SHIFT, #ID_AA64PFR0_DIT_LENGTH 154 cmp x0, #ID_AA64PFR0_DIT_SUPPORTED 155 bne 1f 156 mov x0, #DIT_BIT 157 msr DIT, x0 1581: 159 .endm 160 161/* ----------------------------------------------------------------------------- 162 * This is the super set of actions that need to be performed during a cold boot 163 * or a warm boot in EL3. This code is shared by BL1 and BL31. 164 * 165 * This macro will always perform reset handling, architectural initialisations 166 * and stack setup. The rest of the actions are optional because they might not 167 * be needed, depending on the context in which this macro is called. This is 168 * why this macro is parameterised ; each parameter allows to enable/disable 169 * some actions. 170 * 171 * _init_sctlr: 172 * Whether the macro needs to initialise SCTLR_EL3, including configuring 173 * the endianness of data accesses. 174 * 175 * _warm_boot_mailbox: 176 * Whether the macro needs to detect the type of boot (cold/warm). The 177 * detection is based on the platform entrypoint address : if it is zero 178 * then it is a cold boot, otherwise it is a warm boot. In the latter case, 179 * this macro jumps on the platform entrypoint address. 180 * 181 * _secondary_cold_boot: 182 * Whether the macro needs to identify the CPU that is calling it: primary 183 * CPU or secondary CPU. The primary CPU will be allowed to carry on with 184 * the platform initialisations, while the secondaries will be put in a 185 * platform-specific state in the meantime. 186 * 187 * If the caller knows this macro will only be called by the primary CPU 188 * then this parameter can be defined to 0 to skip this step. 189 * 190 * _init_memory: 191 * Whether the macro needs to initialise the memory. 192 * 193 * _init_c_runtime: 194 * Whether the macro needs to initialise the C runtime environment. 195 * 196 * _exception_vectors: 197 * Address of the exception vectors to program in the VBAR_EL3 register. 198 * ----------------------------------------------------------------------------- 199 */ 200 .macro el3_entrypoint_common \ 201 _init_sctlr, _warm_boot_mailbox, _secondary_cold_boot, \ 202 _init_memory, _init_c_runtime, _exception_vectors 203 204 .if \_init_sctlr 205 /* ------------------------------------------------------------- 206 * This is the initialisation of SCTLR_EL3 and so must ensure 207 * that all fields are explicitly set rather than relying on hw. 208 * Some fields reset to an IMPLEMENTATION DEFINED value and 209 * others are architecturally UNKNOWN on reset. 210 * 211 * SCTLR.EE: Set the CPU endianness before doing anything that 212 * might involve memory reads or writes. Set to zero to select 213 * Little Endian. 214 * 215 * SCTLR_EL3.WXN: For the EL3 translation regime, this field can 216 * force all memory regions that are writeable to be treated as 217 * XN (Execute-never). Set to zero so that this control has no 218 * effect on memory access permissions. 219 * 220 * SCTLR_EL3.SA: Set to zero to disable Stack Alignment check. 221 * 222 * SCTLR_EL3.A: Set to zero to disable Alignment fault checking. 223 * 224 * SCTLR.DSSBS: Set to zero to disable speculation store bypass 225 * safe behaviour upon exception entry to EL3. 226 * ------------------------------------------------------------- 227 */ 228 mov_imm x0, (SCTLR_RESET_VAL & ~(SCTLR_EE_BIT | SCTLR_WXN_BIT \ 229 | SCTLR_SA_BIT | SCTLR_A_BIT | SCTLR_DSSBS_BIT)) 230 msr sctlr_el3, x0 231 isb 232 .endif /* _init_sctlr */ 233 234 .if \_warm_boot_mailbox 235 /* ------------------------------------------------------------- 236 * This code will be executed for both warm and cold resets. 237 * Now is the time to distinguish between the two. 238 * Query the platform entrypoint address and if it is not zero 239 * then it means it is a warm boot so jump to this address. 240 * ------------------------------------------------------------- 241 */ 242 bl plat_get_my_entrypoint 243 cbz x0, do_cold_boot 244 br x0 245 246 do_cold_boot: 247 .endif /* _warm_boot_mailbox */ 248 249 /* --------------------------------------------------------------------- 250 * Set the exception vectors. 251 * --------------------------------------------------------------------- 252 */ 253 adr x0, \_exception_vectors 254 msr vbar_el3, x0 255 isb 256 257 /* --------------------------------------------------------------------- 258 * It is a cold boot. 259 * Perform any processor specific actions upon reset e.g. cache, TLB 260 * invalidations etc. 261 * --------------------------------------------------------------------- 262 */ 263 bl reset_handler 264 265 el3_arch_init_common 266 267 .if \_secondary_cold_boot 268 /* ------------------------------------------------------------- 269 * Check if this is a primary or secondary CPU cold boot. 270 * The primary CPU will set up the platform while the 271 * secondaries are placed in a platform-specific state until the 272 * primary CPU performs the necessary actions to bring them out 273 * of that state and allows entry into the OS. 274 * ------------------------------------------------------------- 275 */ 276 bl plat_is_my_cpu_primary 277 cbnz w0, do_primary_cold_boot 278 279 /* This is a cold boot on a secondary CPU */ 280 bl plat_secondary_cold_boot_setup 281 /* plat_secondary_cold_boot_setup() is not supposed to return */ 282 bl el3_panic 283 284 do_primary_cold_boot: 285 .endif /* _secondary_cold_boot */ 286 287 /* --------------------------------------------------------------------- 288 * Initialize memory now. Secondary CPU initialization won't get to this 289 * point. 290 * --------------------------------------------------------------------- 291 */ 292 293 .if \_init_memory 294 bl platform_mem_init 295 .endif /* _init_memory */ 296 297 /* --------------------------------------------------------------------- 298 * Init C runtime environment: 299 * - Zero-initialise the NOBITS sections. There are 2 of them: 300 * - the .bss section; 301 * - the coherent memory section (if any). 302 * - Relocate the data section from ROM to RAM, if required. 303 * --------------------------------------------------------------------- 304 */ 305 .if \_init_c_runtime 306#if defined(IMAGE_BL31) || (defined(IMAGE_BL2) && BL2_AT_EL3) 307 /* ------------------------------------------------------------- 308 * Invalidate the RW memory used by the BL31 image. This 309 * includes the data and NOBITS sections. This is done to 310 * safeguard against possible corruption of this memory by 311 * dirty cache lines in a system cache as a result of use by 312 * an earlier boot loader stage. 313 * ------------------------------------------------------------- 314 */ 315 adrp x0, __RW_START__ 316 add x0, x0, :lo12:__RW_START__ 317 adrp x1, __RW_END__ 318 add x1, x1, :lo12:__RW_END__ 319 sub x1, x1, x0 320 bl inv_dcache_range 321#endif 322 adrp x0, __BSS_START__ 323 add x0, x0, :lo12:__BSS_START__ 324 325 adrp x1, __BSS_END__ 326 add x1, x1, :lo12:__BSS_END__ 327 sub x1, x1, x0 328 bl zeromem 329 330#if USE_COHERENT_MEM 331 adrp x0, __COHERENT_RAM_START__ 332 add x0, x0, :lo12:__COHERENT_RAM_START__ 333 adrp x1, __COHERENT_RAM_END_UNALIGNED__ 334 add x1, x1, :lo12: __COHERENT_RAM_END_UNALIGNED__ 335 sub x1, x1, x0 336 bl zeromem 337#endif 338 339#if defined(IMAGE_BL1) || (defined(IMAGE_BL2) && BL2_IN_XIP_MEM) 340 adrp x0, __DATA_RAM_START__ 341 add x0, x0, :lo12:__DATA_RAM_START__ 342 adrp x1, __DATA_ROM_START__ 343 add x1, x1, :lo12:__DATA_ROM_START__ 344 adrp x2, __DATA_RAM_END__ 345 add x2, x2, :lo12:__DATA_RAM_END__ 346 sub x2, x2, x0 347 bl memcpy16 348#endif 349 .endif /* _init_c_runtime */ 350 351 /* --------------------------------------------------------------------- 352 * Use SP_EL0 for the C runtime stack. 353 * --------------------------------------------------------------------- 354 */ 355 msr spsel, #0 356 357 /* --------------------------------------------------------------------- 358 * Allocate a stack whose memory will be marked as Normal-IS-WBWA when 359 * the MMU is enabled. There is no risk of reading stale stack memory 360 * after enabling the MMU as only the primary CPU is running at the 361 * moment. 362 * --------------------------------------------------------------------- 363 */ 364 bl plat_set_my_stack 365 366#if STACK_PROTECTOR_ENABLED 367 .if \_init_c_runtime 368 bl update_stack_protector_canary 369 .endif /* _init_c_runtime */ 370#endif 371 .endm 372 373#endif /* EL3_COMMON_MACROS_S */ 374