1/* 2 * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#ifndef EL3_COMMON_MACROS_S 8#define EL3_COMMON_MACROS_S 9 10#include <arch.h> 11#include <asm_macros.S> 12#include <assert_macros.S> 13#include <context.h> 14#include <lib/xlat_tables/xlat_tables_defs.h> 15 16 /* 17 * Helper macro to initialise EL3 registers we care about. 18 */ 19 .macro el3_arch_init_common 20 /* --------------------------------------------------------------------- 21 * SCTLR_EL3 has already been initialised - read current value before 22 * modifying. 23 * 24 * SCTLR_EL3.I: Enable the instruction cache. 25 * 26 * SCTLR_EL3.SA: Enable Stack Alignment check. A SP alignment fault 27 * exception is generated if a load or store instruction executed at 28 * EL3 uses the SP as the base address and the SP is not aligned to a 29 * 16-byte boundary. 30 * 31 * SCTLR_EL3.A: Enable Alignment fault checking. All instructions that 32 * load or store one or more registers have an alignment check that the 33 * address being accessed is aligned to the size of the data element(s) 34 * being accessed. 35 * --------------------------------------------------------------------- 36 */ 37 mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT) 38 mrs x0, sctlr_el3 39 orr x0, x0, x1 40 msr sctlr_el3, x0 41 isb 42 43#ifdef IMAGE_BL31 44 /* --------------------------------------------------------------------- 45 * Initialise the per-cpu cache pointer to the CPU. 46 * This is done early to enable crash reporting to have access to crash 47 * stack. Since crash reporting depends on cpu_data to report the 48 * unhandled exception, not doing so can lead to recursive exceptions 49 * due to a NULL TPIDR_EL3. 50 * --------------------------------------------------------------------- 51 */ 52 bl init_cpu_data_ptr 53#endif /* IMAGE_BL31 */ 54 55 /* --------------------------------------------------------------------- 56 * Initialise SCR_EL3, setting all fields rather than relying on hw. 57 * All fields are architecturally UNKNOWN on reset. The following fields 58 * do not change during the TF lifetime. The remaining fields are set to 59 * zero here but are updated ahead of transitioning to a lower EL in the 60 * function cm_init_context_common(). 61 * 62 * SCR_EL3.TWE: Set to zero so that execution of WFE instructions at 63 * EL2, EL1 and EL0 are not trapped to EL3. 64 * 65 * SCR_EL3.TWI: Set to zero so that execution of WFI instructions at 66 * EL2, EL1 and EL0 are not trapped to EL3. 67 * 68 * SCR_EL3.SIF: Set to one to disable instruction fetches from 69 * Non-secure memory. 70 * 71 * SCR_EL3.SMD: Set to zero to enable SMC calls at EL1 and above, from 72 * both Security states and both Execution states. 73 * 74 * SCR_EL3.EA: Set to one to route External Aborts and SError Interrupts 75 * to EL3 when executing at any EL. 76 * 77 * SCR_EL3.{API,APK}: For Armv8.3 pointer authentication feature, 78 * disable traps to EL3 when accessing key registers or using pointer 79 * authentication instructions from lower ELs. 80 * --------------------------------------------------------------------- 81 */ 82 mov_imm x0, ((SCR_RESET_VAL | SCR_EA_BIT | SCR_SIF_BIT) \ 83 & ~(SCR_TWE_BIT | SCR_TWI_BIT | SCR_SMD_BIT)) 84#if CTX_INCLUDE_PAUTH_REGS 85 /* 86 * If the pointer authentication registers are saved during world 87 * switches, enable pointer authentication everywhere, as it is safe to 88 * do so. 89 */ 90 orr x0, x0, #(SCR_API_BIT | SCR_APK_BIT) 91#endif 92#if ENABLE_RME 93 /* 94 * TODO: Settting the EEL2 bit to allow EL3 access to secure only registers 95 * in context management. This will need to be refactored. 96 */ 97 orr x0, x0, #SCR_EEL2_BIT 98#endif 99 msr scr_el3, x0 100 101 /* --------------------------------------------------------------------- 102 * Initialise MDCR_EL3, setting all fields rather than relying on hw. 103 * Some fields are architecturally UNKNOWN on reset. 104 * 105 * MDCR_EL3.SDD: Set to one to disable AArch64 Secure self-hosted debug. 106 * Debug exceptions, other than Breakpoint Instruction exceptions, are 107 * disabled from all ELs in Secure state. 108 * 109 * MDCR_EL3.SPD32: Set to 0b10 to disable AArch32 Secure self-hosted 110 * privileged debug from S-EL1. 111 * 112 * MDCR_EL3.TDOSA: Set to zero so that EL2 and EL2 System register 113 * access to the powerdown debug registers do not trap to EL3. 114 * 115 * MDCR_EL3.TDA: Set to zero to allow EL0, EL1 and EL2 access to the 116 * debug registers, other than those registers that are controlled by 117 * MDCR_EL3.TDOSA. 118 * 119 * MDCR_EL3.TPM: Set to zero so that EL0, EL1, and EL2 System register 120 * accesses to all Performance Monitors registers do not trap to EL3. 121 * 122 * MDCR_EL3.SCCD: Set to one so that cycle counting by PMCCNTR_EL0 is 123 * prohibited in Secure state. This bit is RES0 in versions of the 124 * architecture with FEAT_PMUv3p5 not implemented, setting it to 1 125 * doesn't have any effect on them. 126 * 127 * MDCR_EL3.MCCD: Set to one so that cycle counting by PMCCNTR_EL0 is 128 * prohibited in EL3. This bit is RES0 in versions of the 129 * architecture with FEAT_PMUv3p7 not implemented, setting it to 1 130 * doesn't have any effect on them. 131 * 132 * MDCR_EL3.SPME: Set to zero so that event counting by the programmable 133 * counters PMEVCNTR<n>_EL0 is prohibited in Secure state. If ARMv8.2 134 * Debug is not implemented this bit does not have any effect on the 135 * counters unless there is support for the implementation defined 136 * authentication interface ExternalSecureNoninvasiveDebugEnabled(). 137 * 138 * MDCR_EL3.NSTB, MDCR_EL3.NSTBE: Set to zero so that Trace Buffer 139 * owning security state is Secure state. If FEAT_TRBE is implemented, 140 * accesses to Trace Buffer control registers at EL2 and EL1 in any 141 * security state generates trap exceptions to EL3. 142 * If FEAT_TRBE is not implemented, these bits are RES0. 143 * 144 * MDCR_EL3.TTRF: Set to one so that access to trace filter control 145 * registers in non-monitor mode generate EL3 trap exception, 146 * unless the access generates a higher priority exception when trace 147 * filter control(FEAT_TRF) is implemented. 148 * When FEAT_TRF is not implemented, this bit is RES0. 149 * --------------------------------------------------------------------- 150 */ 151 mov_imm x0, ((MDCR_EL3_RESET_VAL | MDCR_SDD_BIT | \ 152 MDCR_SPD32(MDCR_SPD32_DISABLE) | MDCR_SCCD_BIT | \ 153 MDCR_MCCD_BIT) & ~(MDCR_SPME_BIT | MDCR_TDOSA_BIT | \ 154 MDCR_TDA_BIT | MDCR_TPM_BIT | MDCR_NSTB(MDCR_NSTB_EL1) | \ 155 MDCR_NSTBE | MDCR_TTRF_BIT)) 156 157 mrs x1, id_aa64dfr0_el1 158 ubfx x1, x1, #ID_AA64DFR0_TRACEFILT_SHIFT, #ID_AA64DFR0_TRACEFILT_LENGTH 159 cbz x1, 1f 160 orr x0, x0, #MDCR_TTRF_BIT 1611: 162 msr mdcr_el3, x0 163 164 /* --------------------------------------------------------------------- 165 * Initialise PMCR_EL0 setting all fields rather than relying 166 * on hw. Some fields are architecturally UNKNOWN on reset. 167 * 168 * PMCR_EL0.LP: Set to one so that event counter overflow, that 169 * is recorded in PMOVSCLR_EL0[0-30], occurs on the increment 170 * that changes PMEVCNTR<n>_EL0[63] from 1 to 0, when ARMv8.5-PMU 171 * is implemented. This bit is RES0 in versions of the architecture 172 * earlier than ARMv8.5, setting it to 1 doesn't have any effect 173 * on them. 174 * 175 * PMCR_EL0.LC: Set to one so that cycle counter overflow, that 176 * is recorded in PMOVSCLR_EL0[31], occurs on the increment 177 * that changes PMCCNTR_EL0[63] from 1 to 0. 178 * 179 * PMCR_EL0.DP: Set to one so that the cycle counter, 180 * PMCCNTR_EL0 does not count when event counting is prohibited. 181 * 182 * PMCR_EL0.X: Set to zero to disable export of events. 183 * 184 * PMCR_EL0.D: Set to zero so that, when enabled, PMCCNTR_EL0 185 * counts on every clock cycle. 186 * --------------------------------------------------------------------- 187 */ 188 mov_imm x0, ((PMCR_EL0_RESET_VAL | PMCR_EL0_LP_BIT | \ 189 PMCR_EL0_LC_BIT | PMCR_EL0_DP_BIT) & \ 190 ~(PMCR_EL0_X_BIT | PMCR_EL0_D_BIT)) 191 192 msr pmcr_el0, x0 193 194 /* --------------------------------------------------------------------- 195 * Enable External Aborts and SError Interrupts now that the exception 196 * vectors have been setup. 197 * --------------------------------------------------------------------- 198 */ 199 msr daifclr, #DAIF_ABT_BIT 200 201 /* --------------------------------------------------------------------- 202 * Initialise CPTR_EL3, setting all fields rather than relying on hw. 203 * All fields are architecturally UNKNOWN on reset. 204 * 205 * CPTR_EL3.TCPAC: Set to zero so that any accesses to CPACR_EL1, 206 * CPTR_EL2, CPACR, or HCPTR do not trap to EL3. 207 * 208 * CPTR_EL3.TTA: Set to one so that accesses to the trace system 209 * registers trap to EL3 from all exception levels and security 210 * states when system register trace is implemented. 211 * When system register trace is not implemented, this bit is RES0 and 212 * hence set to zero. 213 * 214 * CPTR_EL3.TTA: Set to zero so that System register accesses to the 215 * trace registers do not trap to EL3. 216 * 217 * CPTR_EL3.TFP: Set to zero so that accesses to the V- or Z- registers 218 * by Advanced SIMD, floating-point or SVE instructions (if implemented) 219 * do not trap to EL3. 220 * 221 * CPTR_EL3.TAM: Set to one so that Activity Monitor access is 222 * trapped to EL3 by default. 223 * 224 * CPTR_EL3.EZ: Set to zero so that all SVE functionality is trapped 225 * to EL3 by default. 226 * 227 * CPTR_EL3.ESM: Set to zero so that all SME functionality is trapped 228 * to EL3 by default. 229 */ 230 231 mov_imm x0, (CPTR_EL3_RESET_VAL & ~(TCPAC_BIT | TTA_BIT | TFP_BIT)) 232 mrs x1, id_aa64dfr0_el1 233 ubfx x1, x1, #ID_AA64DFR0_TRACEVER_SHIFT, #ID_AA64DFR0_TRACEVER_LENGTH 234 cbz x1, 1f 235 orr x0, x0, #TTA_BIT 2361: 237 msr cptr_el3, x0 238 239 /* 240 * If Data Independent Timing (DIT) functionality is implemented, 241 * always enable DIT in EL3. 242 * First assert that the FEAT_DIT build flag matches the feature id 243 * register value for DIT. 244 */ 245#if ENABLE_FEAT_DIT 246#if ENABLE_ASSERTIONS || ENABLE_FEAT_DIT > 1 247 mrs x0, id_aa64pfr0_el1 248 ubfx x0, x0, #ID_AA64PFR0_DIT_SHIFT, #ID_AA64PFR0_DIT_LENGTH 249#if ENABLE_FEAT_DIT > 1 250 cbz x0, 1f 251#else 252 cmp x0, #ID_AA64PFR0_DIT_SUPPORTED 253 ASM_ASSERT(eq) 254#endif 255 256#endif /* ENABLE_ASSERTIONS */ 257 mov x0, #DIT_BIT 258 msr DIT, x0 2591: 260#endif 261 .endm 262 263/* ----------------------------------------------------------------------------- 264 * This is the super set of actions that need to be performed during a cold boot 265 * or a warm boot in EL3. This code is shared by BL1 and BL31. 266 * 267 * This macro will always perform reset handling, architectural initialisations 268 * and stack setup. The rest of the actions are optional because they might not 269 * be needed, depending on the context in which this macro is called. This is 270 * why this macro is parameterised ; each parameter allows to enable/disable 271 * some actions. 272 * 273 * _init_sctlr: 274 * Whether the macro needs to initialise SCTLR_EL3, including configuring 275 * the endianness of data accesses. 276 * 277 * _warm_boot_mailbox: 278 * Whether the macro needs to detect the type of boot (cold/warm). The 279 * detection is based on the platform entrypoint address : if it is zero 280 * then it is a cold boot, otherwise it is a warm boot. In the latter case, 281 * this macro jumps on the platform entrypoint address. 282 * 283 * _secondary_cold_boot: 284 * Whether the macro needs to identify the CPU that is calling it: primary 285 * CPU or secondary CPU. The primary CPU will be allowed to carry on with 286 * the platform initialisations, while the secondaries will be put in a 287 * platform-specific state in the meantime. 288 * 289 * If the caller knows this macro will only be called by the primary CPU 290 * then this parameter can be defined to 0 to skip this step. 291 * 292 * _init_memory: 293 * Whether the macro needs to initialise the memory. 294 * 295 * _init_c_runtime: 296 * Whether the macro needs to initialise the C runtime environment. 297 * 298 * _exception_vectors: 299 * Address of the exception vectors to program in the VBAR_EL3 register. 300 * 301 * _pie_fixup_size: 302 * Size of memory region to fixup Global Descriptor Table (GDT). 303 * 304 * A non-zero value is expected when firmware needs GDT to be fixed-up. 305 * 306 * ----------------------------------------------------------------------------- 307 */ 308 .macro el3_entrypoint_common \ 309 _init_sctlr, _warm_boot_mailbox, _secondary_cold_boot, \ 310 _init_memory, _init_c_runtime, _exception_vectors, \ 311 _pie_fixup_size 312 313 .if \_init_sctlr 314 /* ------------------------------------------------------------- 315 * This is the initialisation of SCTLR_EL3 and so must ensure 316 * that all fields are explicitly set rather than relying on hw. 317 * Some fields reset to an IMPLEMENTATION DEFINED value and 318 * others are architecturally UNKNOWN on reset. 319 * 320 * SCTLR.EE: Set the CPU endianness before doing anything that 321 * might involve memory reads or writes. Set to zero to select 322 * Little Endian. 323 * 324 * SCTLR_EL3.WXN: For the EL3 translation regime, this field can 325 * force all memory regions that are writeable to be treated as 326 * XN (Execute-never). Set to zero so that this control has no 327 * effect on memory access permissions. 328 * 329 * SCTLR_EL3.SA: Set to zero to disable Stack Alignment check. 330 * 331 * SCTLR_EL3.A: Set to zero to disable Alignment fault checking. 332 * 333 * SCTLR.DSSBS: Set to zero to disable speculation store bypass 334 * safe behaviour upon exception entry to EL3. 335 * ------------------------------------------------------------- 336 */ 337 mov_imm x0, (SCTLR_RESET_VAL & ~(SCTLR_EE_BIT | SCTLR_WXN_BIT \ 338 | SCTLR_SA_BIT | SCTLR_A_BIT | SCTLR_DSSBS_BIT)) 339 msr sctlr_el3, x0 340 isb 341 .endif /* _init_sctlr */ 342 343#if DISABLE_MTPMU 344 bl mtpmu_disable 345#endif 346 347 .if \_warm_boot_mailbox 348 /* ------------------------------------------------------------- 349 * This code will be executed for both warm and cold resets. 350 * Now is the time to distinguish between the two. 351 * Query the platform entrypoint address and if it is not zero 352 * then it means it is a warm boot so jump to this address. 353 * ------------------------------------------------------------- 354 */ 355 bl plat_get_my_entrypoint 356 cbz x0, do_cold_boot 357 br x0 358 359 do_cold_boot: 360 .endif /* _warm_boot_mailbox */ 361 362 .if \_pie_fixup_size 363#if ENABLE_PIE 364 /* 365 * ------------------------------------------------------------ 366 * If PIE is enabled fixup the Global descriptor Table only 367 * once during primary core cold boot path. 368 * 369 * Compile time base address, required for fixup, is calculated 370 * using "pie_fixup" label present within first page. 371 * ------------------------------------------------------------ 372 */ 373 pie_fixup: 374 ldr x0, =pie_fixup 375 and x0, x0, #~(PAGE_SIZE_MASK) 376 mov_imm x1, \_pie_fixup_size 377 add x1, x1, x0 378 bl fixup_gdt_reloc 379#endif /* ENABLE_PIE */ 380 .endif /* _pie_fixup_size */ 381 382 /* --------------------------------------------------------------------- 383 * Set the exception vectors. 384 * --------------------------------------------------------------------- 385 */ 386 adr x0, \_exception_vectors 387 msr vbar_el3, x0 388 isb 389 390#if !(defined(IMAGE_BL2) && ENABLE_RME) 391 /* --------------------------------------------------------------------- 392 * It is a cold boot. 393 * Perform any processor specific actions upon reset e.g. cache, TLB 394 * invalidations etc. 395 * --------------------------------------------------------------------- 396 */ 397 bl reset_handler 398#endif 399 400 el3_arch_init_common 401 402 .if \_secondary_cold_boot 403 /* ------------------------------------------------------------- 404 * Check if this is a primary or secondary CPU cold boot. 405 * The primary CPU will set up the platform while the 406 * secondaries are placed in a platform-specific state until the 407 * primary CPU performs the necessary actions to bring them out 408 * of that state and allows entry into the OS. 409 * ------------------------------------------------------------- 410 */ 411 bl plat_is_my_cpu_primary 412 cbnz w0, do_primary_cold_boot 413 414 /* This is a cold boot on a secondary CPU */ 415 bl plat_secondary_cold_boot_setup 416 /* plat_secondary_cold_boot_setup() is not supposed to return */ 417 bl el3_panic 418 419 do_primary_cold_boot: 420 .endif /* _secondary_cold_boot */ 421 422 /* --------------------------------------------------------------------- 423 * Initialize memory now. Secondary CPU initialization won't get to this 424 * point. 425 * --------------------------------------------------------------------- 426 */ 427 428 .if \_init_memory 429 bl platform_mem_init 430 .endif /* _init_memory */ 431 432 /* --------------------------------------------------------------------- 433 * Init C runtime environment: 434 * - Zero-initialise the NOBITS sections. There are 2 of them: 435 * - the .bss section; 436 * - the coherent memory section (if any). 437 * - Relocate the data section from ROM to RAM, if required. 438 * --------------------------------------------------------------------- 439 */ 440 .if \_init_c_runtime 441#if defined(IMAGE_BL31) || (defined(IMAGE_BL2) && \ 442 ((RESET_TO_BL2 && BL2_INV_DCACHE) || ENABLE_RME)) 443 /* ------------------------------------------------------------- 444 * Invalidate the RW memory used by the BL31 image. This 445 * includes the data and NOBITS sections. This is done to 446 * safeguard against possible corruption of this memory by 447 * dirty cache lines in a system cache as a result of use by 448 * an earlier boot loader stage. If PIE is enabled however, 449 * RO sections including the GOT may be modified during 450 * pie fixup. Therefore, to be on the safe side, invalidate 451 * the entire image region if PIE is enabled. 452 * ------------------------------------------------------------- 453 */ 454#if ENABLE_PIE 455#if SEPARATE_CODE_AND_RODATA 456 adrp x0, __TEXT_START__ 457 add x0, x0, :lo12:__TEXT_START__ 458#else 459 adrp x0, __RO_START__ 460 add x0, x0, :lo12:__RO_START__ 461#endif /* SEPARATE_CODE_AND_RODATA */ 462#else 463 adrp x0, __RW_START__ 464 add x0, x0, :lo12:__RW_START__ 465#endif /* ENABLE_PIE */ 466 adrp x1, __RW_END__ 467 add x1, x1, :lo12:__RW_END__ 468 sub x1, x1, x0 469 bl inv_dcache_range 470#if defined(IMAGE_BL31) && SEPARATE_NOBITS_REGION 471 adrp x0, __NOBITS_START__ 472 add x0, x0, :lo12:__NOBITS_START__ 473 adrp x1, __NOBITS_END__ 474 add x1, x1, :lo12:__NOBITS_END__ 475 sub x1, x1, x0 476 bl inv_dcache_range 477#endif 478#if defined(IMAGE_BL2) && SEPARATE_BL2_NOLOAD_REGION 479 adrp x0, __BL2_NOLOAD_START__ 480 add x0, x0, :lo12:__BL2_NOLOAD_START__ 481 adrp x1, __BL2_NOLOAD_END__ 482 add x1, x1, :lo12:__BL2_NOLOAD_END__ 483 sub x1, x1, x0 484 bl inv_dcache_range 485#endif 486#endif 487 adrp x0, __BSS_START__ 488 add x0, x0, :lo12:__BSS_START__ 489 490 adrp x1, __BSS_END__ 491 add x1, x1, :lo12:__BSS_END__ 492 sub x1, x1, x0 493 bl zeromem 494 495#if USE_COHERENT_MEM 496 adrp x0, __COHERENT_RAM_START__ 497 add x0, x0, :lo12:__COHERENT_RAM_START__ 498 adrp x1, __COHERENT_RAM_END_UNALIGNED__ 499 add x1, x1, :lo12: __COHERENT_RAM_END_UNALIGNED__ 500 sub x1, x1, x0 501 bl zeromem 502#endif 503 504#if defined(IMAGE_BL1) || \ 505 (defined(IMAGE_BL2) && RESET_TO_BL2 && BL2_IN_XIP_MEM) 506 adrp x0, __DATA_RAM_START__ 507 add x0, x0, :lo12:__DATA_RAM_START__ 508 adrp x1, __DATA_ROM_START__ 509 add x1, x1, :lo12:__DATA_ROM_START__ 510 adrp x2, __DATA_RAM_END__ 511 add x2, x2, :lo12:__DATA_RAM_END__ 512 sub x2, x2, x0 513 bl memcpy16 514#endif 515 .endif /* _init_c_runtime */ 516 517 /* --------------------------------------------------------------------- 518 * Use SP_EL0 for the C runtime stack. 519 * --------------------------------------------------------------------- 520 */ 521 msr spsel, #0 522 523 /* --------------------------------------------------------------------- 524 * Allocate a stack whose memory will be marked as Normal-IS-WBWA when 525 * the MMU is enabled. There is no risk of reading stale stack memory 526 * after enabling the MMU as only the primary CPU is running at the 527 * moment. 528 * --------------------------------------------------------------------- 529 */ 530 bl plat_set_my_stack 531 532#if STACK_PROTECTOR_ENABLED 533 .if \_init_c_runtime 534 bl update_stack_protector_canary 535 .endif /* _init_c_runtime */ 536#endif 537 .endm 538 539 .macro apply_at_speculative_wa 540#if ERRATA_SPECULATIVE_AT 541 /* 542 * This function expects x30 has been saved. 543 * Also, save x29 which will be used in the called function. 544 */ 545 str x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29] 546 bl save_and_update_ptw_el1_sys_regs 547 ldr x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29] 548#endif 549 .endm 550 551 .macro restore_ptw_el1_sys_regs 552#if ERRATA_SPECULATIVE_AT 553 /* ----------------------------------------------------------- 554 * In case of ERRATA_SPECULATIVE_AT, must follow below order 555 * to ensure that page table walk is not enabled until 556 * restoration of all EL1 system registers. TCR_EL1 register 557 * should be updated at the end which restores previous page 558 * table walk setting of stage1 i.e.(TCR_EL1.EPDx) bits. ISB 559 * ensures that CPU does below steps in order. 560 * 561 * 1. Ensure all other system registers are written before 562 * updating SCTLR_EL1 using ISB. 563 * 2. Restore SCTLR_EL1 register. 564 * 3. Ensure SCTLR_EL1 written successfully using ISB. 565 * 4. Restore TCR_EL1 register. 566 * ----------------------------------------------------------- 567 */ 568 isb 569 ldp x28, x29, [sp, #CTX_EL1_SYSREGS_OFFSET + CTX_SCTLR_EL1] 570 msr sctlr_el1, x28 571 isb 572 msr tcr_el1, x29 573#endif 574 .endm 575 576#endif /* EL3_COMMON_MACROS_S */ 577