1/* 2 * Copyright (c) 2015-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#ifndef EL3_COMMON_MACROS_S 8#define EL3_COMMON_MACROS_S 9 10#include <arch.h> 11#include <asm_macros.S> 12#include <assert_macros.S> 13#include <context.h> 14#include <lib/xlat_tables/xlat_tables_defs.h> 15 16 /* 17 * Helper macro to initialise EL3 registers we care about. 18 */ 19 .macro el3_arch_init_common 20 /* --------------------------------------------------------------------- 21 * SCTLR_EL3 has already been initialised - read current value before 22 * modifying. 23 * 24 * SCTLR_EL3.I: Enable the instruction cache. 25 * 26 * SCTLR_EL3.SA: Enable Stack Alignment check. A SP alignment fault 27 * exception is generated if a load or store instruction executed at 28 * EL3 uses the SP as the base address and the SP is not aligned to a 29 * 16-byte boundary. 30 * 31 * SCTLR_EL3.A: Enable Alignment fault checking. All instructions that 32 * load or store one or more registers have an alignment check that the 33 * address being accessed is aligned to the size of the data element(s) 34 * being accessed. 35 * 36 * SCTLR_EL3.BT: PAuth instructions are compatible with bti jc 37 * --------------------------------------------------------------------- 38 */ 39 mov_imm x1, (SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT) 40 mrs x0, sctlr_el3 41#if ENABLE_BTI 42 bic x0, x0, #SCTLR_BT_BIT 43#endif 44 orr x0, x0, x1 45 msr sctlr_el3, x0 46 isb 47 48#if ENABLE_FEAT_SCTLR2 49#if ENABLE_FEAT_SCTLR2 > 1 50 is_feat_sctlr2_present_asm x1 51 beq feat_sctlr2_not_supported\@ 52#endif 53 mov x1, #SCTLR2_RESET_VAL 54 msr SCTLR2_EL3, x1 55feat_sctlr2_not_supported\@: 56#endif 57 58#ifdef IMAGE_BL31 59 /* --------------------------------------------------------------------- 60 * Initialise the per-cpu cache pointer to the CPU. 61 * This is done early to enable crash reporting to have access to crash 62 * stack. Since crash reporting depends on cpu_data to report the 63 * unhandled exception, not doing so can lead to recursive exceptions 64 * due to a NULL TPIDR_EL3. 65 * --------------------------------------------------------------------- 66 */ 67 bl plat_my_core_pos 68 /* index into the cpu_data */ 69 mov_imm x1, CPU_DATA_SIZE 70 mul x0, x0, x1 71 adr_l x1, percpu_data 72 add x0, x0, x1 73 msr tpidr_el3, x0 74#endif /* IMAGE_BL31 */ 75 76 /* --------------------------------------------------------------------- 77 * Initialise SCR_EL3, setting all fields rather than relying on hw. 78 * All fields are architecturally UNKNOWN on reset. The following fields 79 * do not change during the TF lifetime. The remaining fields are set to 80 * zero here but are updated ahead of transitioning to a lower EL in the 81 * function cm_init_context_common(). 82 * 83 * SCR_EL3.EEL2: Set to one if S-EL2 is present and enabled. 84 * 85 * NOTE: Modifying EEL2 bit along with EA bit ensures that we mitigate 86 * against ERRATA_V2_3099206. 87 * --------------------------------------------------------------------- 88 */ 89 mov_imm x0, SCR_RESET_VAL 90#if IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2 91 mrs x1, id_aa64pfr0_el1 92 and x1, x1, #(ID_AA64PFR0_SEL2_MASK << ID_AA64PFR0_SEL2_SHIFT) 93 cbz x1, 1f 94 orr x0, x0, #SCR_EEL2_BIT 95#endif 961: 97 msr scr_el3, x0 98 99 /* --------------------------------------------------------------------- 100 * Initialise MDCR_EL3, setting all fields rather than relying on hw. 101 * Some fields are architecturally UNKNOWN on reset. 102 */ 103 mov_imm x0, MDCR_EL3_RESET_VAL 104 msr mdcr_el3, x0 105 106 /* --------------------------------------------------------------------- 107 * Initialise CPTR_EL3, setting all fields rather than relying on hw. 108 * All fields are architecturally UNKNOWN on reset. 109 * --------------------------------------------------------------------- 110 */ 111 mov_imm x0, CPTR_EL3_RESET_VAL 112 msr cptr_el3, x0 113 114 .endm 115 116/* ----------------------------------------------------------------------------- 117 * This is the super set of actions that need to be performed during a cold boot 118 * or a warm boot in EL3. This code is shared by BL1 and BL31. 119 * 120 * This macro will always perform reset handling, architectural initialisations 121 * and stack setup. The rest of the actions are optional because they might not 122 * be needed, depending on the context in which this macro is called. This is 123 * why this macro is parameterised ; each parameter allows to enable/disable 124 * some actions. 125 * 126 * _init_sctlr: 127 * Whether the macro needs to initialise SCTLR_EL3, including configuring 128 * the endianness of data accesses. 129 * 130 * _warm_boot_mailbox: 131 * Whether the macro needs to detect the type of boot (cold/warm). The 132 * detection is based on the platform entrypoint address : if it is zero 133 * then it is a cold boot, otherwise it is a warm boot. In the latter case, 134 * this macro jumps on the platform entrypoint address. 135 * 136 * _secondary_cold_boot: 137 * Whether the macro needs to identify the CPU that is calling it: primary 138 * CPU or secondary CPU. The primary CPU will be allowed to carry on with 139 * the platform initialisations, while the secondaries will be put in a 140 * platform-specific state in the meantime. 141 * 142 * If the caller knows this macro will only be called by the primary CPU 143 * then this parameter can be defined to 0 to skip this step. 144 * 145 * _init_memory: 146 * Whether the macro needs to initialise the memory. 147 * 148 * _init_c_runtime: 149 * Whether the macro needs to initialise the C runtime environment. 150 * 151 * _exception_vectors: 152 * Address of the exception vectors to program in the VBAR_EL3 register. 153 * 154 * _pie_fixup_size: 155 * Size of memory region to fixup Global Descriptor Table (GDT). 156 * 157 * A non-zero value is expected when firmware needs GDT to be fixed-up. 158 * 159 * ----------------------------------------------------------------------------- 160 */ 161 .macro el3_entrypoint_common \ 162 _init_sctlr, _warm_boot_mailbox, _secondary_cold_boot, \ 163 _init_memory, _init_c_runtime, _exception_vectors, \ 164 _pie_fixup_size 165 166 .if \_init_sctlr 167 /* ------------------------------------------------------------- 168 * This is the initialisation of SCTLR_EL3 and so must ensure 169 * that all fields are explicitly set rather than relying on hw. 170 * Some fields reset to an IMPLEMENTATION DEFINED value and 171 * others are architecturally UNKNOWN on reset. 172 * 173 * SCTLR.EE: Set the CPU endianness before doing anything that 174 * might involve memory reads or writes. Set to zero to select 175 * Little Endian. 176 * 177 * SCTLR_EL3.WXN: For the EL3 translation regime, this field can 178 * force all memory regions that are writeable to be treated as 179 * XN (Execute-never). Set to zero so that this control has no 180 * effect on memory access permissions. 181 * 182 * SCTLR_EL3.SA: Set to zero to disable Stack Alignment check. 183 * 184 * SCTLR_EL3.A: Set to zero to disable Alignment fault checking. 185 * 186 * SCTLR.DSSBS: Set to zero to disable speculation store bypass 187 * safe behaviour upon exception entry to EL3. 188 * ------------------------------------------------------------- 189 */ 190 mov_imm x0, (SCTLR_RESET_VAL & ~(SCTLR_EE_BIT | SCTLR_WXN_BIT \ 191 | SCTLR_SA_BIT | SCTLR_A_BIT | SCTLR_DSSBS_BIT)) 192#if ENABLE_FEAT_RAS 193 /* If FEAT_RAS is present assume FEAT_IESB is also present */ 194 orr x0, x0, #SCTLR_IESB_BIT 195#endif 196 msr sctlr_el3, x0 197 isb 198 .endif /* _init_sctlr */ 199 200 .if \_warm_boot_mailbox 201 /* ------------------------------------------------------------- 202 * This code will be executed for both warm and cold resets. 203 * Now is the time to distinguish between the two. 204 * Query the platform entrypoint address and if it is not zero 205 * then it means it is a warm boot so jump to this address. 206 * ------------------------------------------------------------- 207 */ 208 bl plat_get_my_entrypoint 209 cbz x0, do_cold_boot 210 br x0 211 212 do_cold_boot: 213 .endif /* _warm_boot_mailbox */ 214 215 .if \_pie_fixup_size 216#if ENABLE_PIE 217 /* 218 * ------------------------------------------------------------ 219 * If PIE is enabled fixup the Global descriptor Table only 220 * once during primary core cold boot path. 221 * 222 * Compile time base address, required for fixup, is calculated 223 * using "pie_fixup" label present within first page. 224 * ------------------------------------------------------------ 225 */ 226 pie_fixup: 227 ldr x0, =pie_fixup 228 and x0, x0, #~(PAGE_SIZE_MASK) 229 mov_imm x1, \_pie_fixup_size 230 add x1, x1, x0 231 bl fixup_gdt_reloc 232#endif /* ENABLE_PIE */ 233 .endif /* _pie_fixup_size */ 234 235 /* --------------------------------------------------------------------- 236 * Set the exception vectors. 237 * --------------------------------------------------------------------- 238 */ 239 adr x0, \_exception_vectors 240 msr vbar_el3, x0 241 isb 242 243 call_reset_handler 244 245 el3_arch_init_common 246 247 /* --------------------------------------------------------------------- 248 * Set the el3 execution context(i.e. root_context). 249 * --------------------------------------------------------------------- 250 */ 251 setup_el3_execution_context 252 253 .if \_secondary_cold_boot 254 /* ------------------------------------------------------------- 255 * Check if this is a primary or secondary CPU cold boot. 256 * The primary CPU will set up the platform while the 257 * secondaries are placed in a platform-specific state until the 258 * primary CPU performs the necessary actions to bring them out 259 * of that state and allows entry into the OS. 260 * ------------------------------------------------------------- 261 */ 262 bl plat_is_my_cpu_primary 263 cbnz w0, do_primary_cold_boot 264 265 /* This is a cold boot on a secondary CPU */ 266 bl plat_secondary_cold_boot_setup 267 /* plat_secondary_cold_boot_setup() is not supposed to return */ 268 bl el3_panic 269 270 do_primary_cold_boot: 271 .endif /* _secondary_cold_boot */ 272 273 /* --------------------------------------------------------------------- 274 * Initialize memory now. Secondary CPU initialization won't get to this 275 * point. 276 * --------------------------------------------------------------------- 277 */ 278 279 .if \_init_memory 280 bl platform_mem_init 281 .endif /* _init_memory */ 282 283 /* --------------------------------------------------------------------- 284 * Init C runtime environment: 285 * - Zero-initialise the NOBITS sections. There are 2 of them: 286 * - the .bss section; 287 * - the coherent memory section (if any). 288 * - Relocate the data section from ROM to RAM, if required. 289 * --------------------------------------------------------------------- 290 */ 291 .if \_init_c_runtime 292#if defined(IMAGE_BL31) || (defined(IMAGE_BL2) && \ 293 ((RESET_TO_BL2 && BL2_INV_DCACHE) || ENABLE_RME)) 294 /* ------------------------------------------------------------- 295 * Invalidate the RW memory used by the BL31 image. This 296 * includes the data and NOBITS sections. This is done to 297 * safeguard against possible corruption of this memory by 298 * dirty cache lines in a system cache as a result of use by 299 * an earlier boot loader stage. If PIE is enabled however, 300 * RO sections including the GOT may be modified during 301 * pie fixup. Therefore, to be on the safe side, invalidate 302 * the entire image region if PIE is enabled. 303 * ------------------------------------------------------------- 304 */ 305#if ENABLE_PIE 306#if SEPARATE_CODE_AND_RODATA 307 adrp x0, __TEXT_START__ 308 add x0, x0, :lo12:__TEXT_START__ 309#else 310 adrp x0, __RO_START__ 311 add x0, x0, :lo12:__RO_START__ 312#endif /* SEPARATE_CODE_AND_RODATA */ 313#else 314 adrp x0, __RW_START__ 315 add x0, x0, :lo12:__RW_START__ 316#endif /* ENABLE_PIE */ 317 adrp x1, __RW_END__ 318 add x1, x1, :lo12:__RW_END__ 319 sub x1, x1, x0 320 bl inv_dcache_range 321#if defined(IMAGE_BL31) && SEPARATE_NOBITS_REGION 322 adrp x0, __NOBITS_START__ 323 add x0, x0, :lo12:__NOBITS_START__ 324 adrp x1, __NOBITS_END__ 325 add x1, x1, :lo12:__NOBITS_END__ 326 sub x1, x1, x0 327 bl inv_dcache_range 328#endif 329#if defined(IMAGE_BL2) && SEPARATE_BL2_NOLOAD_REGION 330 adrp x0, __BL2_NOLOAD_START__ 331 add x0, x0, :lo12:__BL2_NOLOAD_START__ 332 adrp x1, __BL2_NOLOAD_END__ 333 add x1, x1, :lo12:__BL2_NOLOAD_END__ 334 sub x1, x1, x0 335 bl inv_dcache_range 336#endif 337#endif 338 adrp x0, __BSS_START__ 339 add x0, x0, :lo12:__BSS_START__ 340 341 adrp x1, __BSS_END__ 342 add x1, x1, :lo12:__BSS_END__ 343 sub x1, x1, x0 344 bl zeromem 345 346#if USE_COHERENT_MEM 347 adrp x0, __COHERENT_RAM_START__ 348 add x0, x0, :lo12:__COHERENT_RAM_START__ 349 adrp x1, __COHERENT_RAM_END_UNALIGNED__ 350 add x1, x1, :lo12: __COHERENT_RAM_END_UNALIGNED__ 351 sub x1, x1, x0 352 bl zeromem 353#endif 354 355#if defined(IMAGE_BL1) || \ 356 (defined(IMAGE_BL2) && RESET_TO_BL2 && BL2_IN_XIP_MEM) || \ 357 (defined(IMAGE_BL31) && SEPARATE_RWDATA_REGION) 358 359 adrp x0, __DATA_RAM_START__ 360 add x0, x0, :lo12:__DATA_RAM_START__ 361 adrp x1, __DATA_ROM_START__ 362 add x1, x1, :lo12:__DATA_ROM_START__ 363 adrp x2, __DATA_RAM_END__ 364 add x2, x2, :lo12:__DATA_RAM_END__ 365 sub x2, x2, x0 366 bl memcpy16 367#endif 368 .endif /* _init_c_runtime */ 369 370 /* --------------------------------------------------------------------- 371 * Use SP_EL0 for the C runtime stack. 372 * --------------------------------------------------------------------- 373 */ 374 msr spsel, #0 375 376 /* --------------------------------------------------------------------- 377 * Allocate a stack whose memory will be marked as Normal-IS-WBWA when 378 * the MMU is enabled. There is no risk of reading stale stack memory 379 * after enabling the MMU as only the primary CPU is running at the 380 * moment. 381 * --------------------------------------------------------------------- 382 */ 383 bl plat_set_my_stack 384 385#if STACK_PROTECTOR_ENABLED 386 .if \_init_c_runtime 387 bl update_stack_protector_canary 388 .endif /* _init_c_runtime */ 389#endif 390 .endm 391 392 .macro apply_at_speculative_wa 393#if ERRATA_SPECULATIVE_AT 394 /* 395 * This function expects x30 has been saved. 396 * Also, save x29 which will be used in the called function. 397 */ 398 str x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29] 399 bl save_and_update_ptw_el1_sys_regs 400 ldr x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29] 401#endif 402 .endm 403 404 .macro restore_ptw_el1_sys_regs 405#if ERRATA_SPECULATIVE_AT 406 /* ----------------------------------------------------------- 407 * In case of ERRATA_SPECULATIVE_AT, must follow below order 408 * to ensure that page table walk is not enabled until 409 * restoration of all EL1 system registers. TCR_EL1 register 410 * should be updated at the end which restores previous page 411 * table walk setting of stage1 i.e.(TCR_EL1.EPDx) bits. ISB 412 * ensures that CPU does below steps in order. 413 * 414 * 1. Ensure all other system registers are written before 415 * updating SCTLR_EL1 using ISB. 416 * 2. Restore SCTLR_EL1 register. 417 * 3. Ensure SCTLR_EL1 written successfully using ISB. 418 * 4. Restore TCR_EL1 register. 419 * ----------------------------------------------------------- 420 */ 421 isb 422 ldp x28, x29, [sp, #CTX_ERRATA_SPEC_AT_OFFSET + CTX_ERRATA_SPEC_AT_SCTLR_EL1] 423 msr sctlr_el1, x28 424 isb 425 msr tcr_el1, x29 426#endif 427 .endm 428 429/* ----------------------------------------------------------------- 430 * The below macro reads SCR_EL3 from the context structure to 431 * determine the security state of the context upon ERET. 432 * ------------------------------------------------------------------ 433 */ 434 .macro get_security_state _ret:req, _scr_reg:req 435 ubfx \_ret, \_scr_reg, #SCR_NSE_SHIFT, #1 436 cmp \_ret, #1 437 beq realm_state 438 bfi \_ret, \_scr_reg, #0, #1 439 b end 440 realm_state: 441 mov \_ret, #2 442 end: 443 .endm 444 445/*----------------------------------------------------------------------------- 446 * Helper macro to configure EL3 registers we care about, while executing 447 * at EL3/Root world. Root world has its own execution environment and 448 * needs to have its settings configured to be independent of other worlds. 449 * ----------------------------------------------------------------------------- 450 */ 451 .macro setup_el3_execution_context 452 453 /* --------------------------------------------------------------------- 454 * The following registers need to be part of separate root context 455 * as their values are of importance during EL3 execution. 456 * Hence these registers are overwritten to their intital values, 457 * irrespective of whichever world they return from to ensure EL3 has a 458 * consistent execution context throughout the lifetime of TF-A. 459 * 460 * DAIF.A: Enable External Aborts and SError Interrupts at EL3. 461 * 462 * MDCR_EL3.SDD: Set to one to disable AArch64 Secure self-hosted debug. 463 * Debug exceptions, other than Breakpoint Instruction exceptions, are 464 * disabled from all ELs in Secure state. 465 * 466 * SCR_EL3.EA: Set to one to enable SError interrupts at EL3. 467 * 468 * SCR_EL3.SIF: Set to one to disable instruction fetches from 469 * Non-secure memory. 470 * 471 * PMCR_EL0.DP: Set to one so that the cycle counter, 472 * PMCCNTR_EL0 does not count when event counting is prohibited. 473 * Necessary on PMUv3 <= p7 where MDCR_EL3.{SCCD,MCCD} are not 474 * available. 475 * 476 * CPTR_EL3.EZ: Set to one so that accesses to ZCR_EL3 do not trap 477 * CPTR_EL3.TFP: Set to zero so that advanced SIMD operations don't trap 478 * CPTR_EL3.ESM: Set to one so that SME related registers don't trap 479 * 480 * PSTATE.DIT: Set to one to enable the Data Independent Timing (DIT) 481 * functionality, if implemented in EL3. 482 * --------------------------------------------------------------------- 483 */ 484 msr daifclr, #DAIF_ABT_BIT 485 486 mrs x15, mdcr_el3 487 orr x15, x15, #MDCR_SDD_BIT 488 msr mdcr_el3, x15 489 490 mrs x15, scr_el3 491 orr x15, x15, #SCR_EA_BIT 492 orr x15, x15, #SCR_SIF_BIT 493 msr scr_el3, x15 494 495 mrs x15, pmcr_el0 496 orr x15, x15, #PMCR_EL0_DP_BIT 497 msr pmcr_el0, x15 498 499 mrs x15, cptr_el3 500 orr x15, x15, #CPTR_EZ_BIT 501 orr x15, x15, #ESM_BIT 502 bic x15, x15, #TFP_BIT 503 msr cptr_el3, x15 504 505#if ENABLE_FEAT_DIT 506#if ENABLE_FEAT_DIT > 1 507 mrs x15, id_aa64pfr0_el1 508 ubfx x15, x15, #ID_AA64PFR0_DIT_SHIFT, #ID_AA64PFR0_DIT_LENGTH 509 cbz x15, 1f 510#endif 511 mov x15, #DIT_BIT 512 msr DIT, x15 513 1: 514#endif 515 516 isb 517 .endm 518 519#endif /* EL3_COMMON_MACROS_S */ 520