1/* 2 * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#ifndef EL3_COMMON_MACROS_S 8#define EL3_COMMON_MACROS_S 9 10#include <arch.h> 11#include <asm_macros.S> 12#include <context.h> 13#include <lib/xlat_tables/xlat_tables_defs.h> 14 15 /* 16 * Helper macro to initialise EL3 registers we care about. 17 */ 18 .macro el3_arch_init_common 19 /* --------------------------------------------------------------------- 20 * SCTLR_EL3 has already been initialised - read current value before 21 * modifying. 22 * 23 * SCTLR_EL3.I: Enable the instruction cache. 24 * 25 * SCTLR_EL3.SA: Enable Stack Alignment check. A SP alignment fault 26 * exception is generated if a load or store instruction executed at 27 * EL3 uses the SP as the base address and the SP is not aligned to a 28 * 16-byte boundary. 29 * 30 * SCTLR_EL3.A: Enable Alignment fault checking. All instructions that 31 * load or store one or more registers have an alignment check that the 32 * address being accessed is aligned to the size of the data element(s) 33 * being accessed. 34 * --------------------------------------------------------------------- 35 */ 36 mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT) 37 mrs x0, sctlr_el3 38 orr x0, x0, x1 39 msr sctlr_el3, x0 40 isb 41 42#ifdef IMAGE_BL31 43 /* --------------------------------------------------------------------- 44 * Initialise the per-cpu cache pointer to the CPU. 45 * This is done early to enable crash reporting to have access to crash 46 * stack. Since crash reporting depends on cpu_data to report the 47 * unhandled exception, not doing so can lead to recursive exceptions 48 * due to a NULL TPIDR_EL3. 49 * --------------------------------------------------------------------- 50 */ 51 bl init_cpu_data_ptr 52#endif /* IMAGE_BL31 */ 53 54 /* --------------------------------------------------------------------- 55 * Initialise SCR_EL3, setting all fields rather than relying on hw. 56 * All fields are architecturally UNKNOWN on reset. The following fields 57 * do not change during the TF lifetime. The remaining fields are set to 58 * zero here but are updated ahead of transitioning to a lower EL in the 59 * function cm_init_context_common(). 60 * 61 * SCR_EL3.TWE: Set to zero so that execution of WFE instructions at 62 * EL2, EL1 and EL0 are not trapped to EL3. 63 * 64 * SCR_EL3.TWI: Set to zero so that execution of WFI instructions at 65 * EL2, EL1 and EL0 are not trapped to EL3. 66 * 67 * SCR_EL3.SIF: Set to one to disable instruction fetches from 68 * Non-secure memory. 69 * 70 * SCR_EL3.SMD: Set to zero to enable SMC calls at EL1 and above, from 71 * both Security states and both Execution states. 72 * 73 * SCR_EL3.EA: Set to one to route External Aborts and SError Interrupts 74 * to EL3 when executing at any EL. 75 * 76 * SCR_EL3.{API,APK}: For Armv8.3 pointer authentication feature, 77 * disable traps to EL3 when accessing key registers or using pointer 78 * authentication instructions from lower ELs. 79 * --------------------------------------------------------------------- 80 */ 81 mov_imm x0, ((SCR_RESET_VAL | SCR_EA_BIT | SCR_SIF_BIT) \ 82 & ~(SCR_TWE_BIT | SCR_TWI_BIT | SCR_SMD_BIT)) 83#if CTX_INCLUDE_PAUTH_REGS 84 /* 85 * If the pointer authentication registers are saved during world 86 * switches, enable pointer authentication everywhere, as it is safe to 87 * do so. 88 */ 89 orr x0, x0, #(SCR_API_BIT | SCR_APK_BIT) 90#endif 91 msr scr_el3, x0 92 93 /* --------------------------------------------------------------------- 94 * Initialise MDCR_EL3, setting all fields rather than relying on hw. 95 * Some fields are architecturally UNKNOWN on reset. 96 * 97 * MDCR_EL3.SDD: Set to one to disable AArch64 Secure self-hosted debug. 98 * Debug exceptions, other than Breakpoint Instruction exceptions, are 99 * disabled from all ELs in Secure state. 100 * 101 * MDCR_EL3.SPD32: Set to 0b10 to disable AArch32 Secure self-hosted 102 * privileged debug from S-EL1. 103 * 104 * MDCR_EL3.TDOSA: Set to zero so that EL2 and EL2 System register 105 * access to the powerdown debug registers do not trap to EL3. 106 * 107 * MDCR_EL3.TDA: Set to zero to allow EL0, EL1 and EL2 access to the 108 * debug registers, other than those registers that are controlled by 109 * MDCR_EL3.TDOSA. 110 * 111 * MDCR_EL3.TPM: Set to zero so that EL0, EL1, and EL2 System register 112 * accesses to all Performance Monitors registers do not trap to EL3. 113 * 114 * MDCR_EL3.SCCD: Set to one so that cycle counting by PMCCNTR_EL0 is 115 * prohibited in Secure state. This bit is RES0 in versions of the 116 * architecture earlier than ARMv8.5, setting it to 1 doesn't have any 117 * effect on them. 118 * 119 * MDCR_EL3.SPME: Set to zero so that event counting by the programmable 120 * counters PMEVCNTR<n>_EL0 is prohibited in Secure state. If ARMv8.2 121 * Debug is not implemented this bit does not have any effect on the 122 * counters unless there is support for the implementation defined 123 * authentication interface ExternalSecureNoninvasiveDebugEnabled(). 124 * --------------------------------------------------------------------- 125 */ 126 mov_imm x0, ((MDCR_EL3_RESET_VAL | MDCR_SDD_BIT | \ 127 MDCR_SPD32(MDCR_SPD32_DISABLE) | MDCR_SCCD_BIT) & \ 128 ~(MDCR_SPME_BIT | MDCR_TDOSA_BIT | MDCR_TDA_BIT | \ 129 MDCR_TPM_BIT)) 130 131 msr mdcr_el3, x0 132 133 /* --------------------------------------------------------------------- 134 * Initialise PMCR_EL0 setting all fields rather than relying 135 * on hw. Some fields are architecturally UNKNOWN on reset. 136 * 137 * PMCR_EL0.LP: Set to one so that event counter overflow, that 138 * is recorded in PMOVSCLR_EL0[0-30], occurs on the increment 139 * that changes PMEVCNTR<n>_EL0[63] from 1 to 0, when ARMv8.5-PMU 140 * is implemented. This bit is RES0 in versions of the architecture 141 * earlier than ARMv8.5, setting it to 1 doesn't have any effect 142 * on them. 143 * 144 * PMCR_EL0.LC: Set to one so that cycle counter overflow, that 145 * is recorded in PMOVSCLR_EL0[31], occurs on the increment 146 * that changes PMCCNTR_EL0[63] from 1 to 0. 147 * 148 * PMCR_EL0.DP: Set to one so that the cycle counter, 149 * PMCCNTR_EL0 does not count when event counting is prohibited. 150 * 151 * PMCR_EL0.X: Set to zero to disable export of events. 152 * 153 * PMCR_EL0.D: Set to zero so that, when enabled, PMCCNTR_EL0 154 * counts on every clock cycle. 155 * --------------------------------------------------------------------- 156 */ 157 mov_imm x0, ((PMCR_EL0_RESET_VAL | PMCR_EL0_LP_BIT | \ 158 PMCR_EL0_LC_BIT | PMCR_EL0_DP_BIT) & \ 159 ~(PMCR_EL0_X_BIT | PMCR_EL0_D_BIT)) 160 161 msr pmcr_el0, x0 162 163 /* --------------------------------------------------------------------- 164 * Enable External Aborts and SError Interrupts now that the exception 165 * vectors have been setup. 166 * --------------------------------------------------------------------- 167 */ 168 msr daifclr, #DAIF_ABT_BIT 169 170 /* --------------------------------------------------------------------- 171 * Initialise CPTR_EL3, setting all fields rather than relying on hw. 172 * All fields are architecturally UNKNOWN on reset. 173 * 174 * CPTR_EL3.TCPAC: Set to zero so that any accesses to CPACR_EL1, 175 * CPTR_EL2, CPACR, or HCPTR do not trap to EL3. 176 * 177 * CPTR_EL3.TTA: Set to zero so that System register accesses to the 178 * trace registers do not trap to EL3. 179 * 180 * CPTR_EL3.TFP: Set to zero so that accesses to the V- or Z- registers 181 * by Advanced SIMD, floating-point or SVE instructions (if implemented) 182 * do not trap to EL3. 183 */ 184 mov_imm x0, (CPTR_EL3_RESET_VAL & ~(TCPAC_BIT | TTA_BIT | TFP_BIT)) 185 msr cptr_el3, x0 186 187 /* 188 * If Data Independent Timing (DIT) functionality is implemented, 189 * always enable DIT in EL3 190 */ 191 mrs x0, id_aa64pfr0_el1 192 ubfx x0, x0, #ID_AA64PFR0_DIT_SHIFT, #ID_AA64PFR0_DIT_LENGTH 193 cmp x0, #ID_AA64PFR0_DIT_SUPPORTED 194 bne 1f 195 mov x0, #DIT_BIT 196 msr DIT, x0 1971: 198 .endm 199 200/* ----------------------------------------------------------------------------- 201 * This is the super set of actions that need to be performed during a cold boot 202 * or a warm boot in EL3. This code is shared by BL1 and BL31. 203 * 204 * This macro will always perform reset handling, architectural initialisations 205 * and stack setup. The rest of the actions are optional because they might not 206 * be needed, depending on the context in which this macro is called. This is 207 * why this macro is parameterised ; each parameter allows to enable/disable 208 * some actions. 209 * 210 * _init_sctlr: 211 * Whether the macro needs to initialise SCTLR_EL3, including configuring 212 * the endianness of data accesses. 213 * 214 * _warm_boot_mailbox: 215 * Whether the macro needs to detect the type of boot (cold/warm). The 216 * detection is based on the platform entrypoint address : if it is zero 217 * then it is a cold boot, otherwise it is a warm boot. In the latter case, 218 * this macro jumps on the platform entrypoint address. 219 * 220 * _secondary_cold_boot: 221 * Whether the macro needs to identify the CPU that is calling it: primary 222 * CPU or secondary CPU. The primary CPU will be allowed to carry on with 223 * the platform initialisations, while the secondaries will be put in a 224 * platform-specific state in the meantime. 225 * 226 * If the caller knows this macro will only be called by the primary CPU 227 * then this parameter can be defined to 0 to skip this step. 228 * 229 * _init_memory: 230 * Whether the macro needs to initialise the memory. 231 * 232 * _init_c_runtime: 233 * Whether the macro needs to initialise the C runtime environment. 234 * 235 * _exception_vectors: 236 * Address of the exception vectors to program in the VBAR_EL3 register. 237 * 238 * _pie_fixup_size: 239 * Size of memory region to fixup Global Descriptor Table (GDT). 240 * 241 * A non-zero value is expected when firmware needs GDT to be fixed-up. 242 * 243 * ----------------------------------------------------------------------------- 244 */ 245 .macro el3_entrypoint_common \ 246 _init_sctlr, _warm_boot_mailbox, _secondary_cold_boot, \ 247 _init_memory, _init_c_runtime, _exception_vectors, \ 248 _pie_fixup_size 249 250 .if \_init_sctlr 251 /* ------------------------------------------------------------- 252 * This is the initialisation of SCTLR_EL3 and so must ensure 253 * that all fields are explicitly set rather than relying on hw. 254 * Some fields reset to an IMPLEMENTATION DEFINED value and 255 * others are architecturally UNKNOWN on reset. 256 * 257 * SCTLR.EE: Set the CPU endianness before doing anything that 258 * might involve memory reads or writes. Set to zero to select 259 * Little Endian. 260 * 261 * SCTLR_EL3.WXN: For the EL3 translation regime, this field can 262 * force all memory regions that are writeable to be treated as 263 * XN (Execute-never). Set to zero so that this control has no 264 * effect on memory access permissions. 265 * 266 * SCTLR_EL3.SA: Set to zero to disable Stack Alignment check. 267 * 268 * SCTLR_EL3.A: Set to zero to disable Alignment fault checking. 269 * 270 * SCTLR.DSSBS: Set to zero to disable speculation store bypass 271 * safe behaviour upon exception entry to EL3. 272 * ------------------------------------------------------------- 273 */ 274 mov_imm x0, (SCTLR_RESET_VAL & ~(SCTLR_EE_BIT | SCTLR_WXN_BIT \ 275 | SCTLR_SA_BIT | SCTLR_A_BIT | SCTLR_DSSBS_BIT)) 276 msr sctlr_el3, x0 277 isb 278 .endif /* _init_sctlr */ 279 280 .if \_warm_boot_mailbox 281 /* ------------------------------------------------------------- 282 * This code will be executed for both warm and cold resets. 283 * Now is the time to distinguish between the two. 284 * Query the platform entrypoint address and if it is not zero 285 * then it means it is a warm boot so jump to this address. 286 * ------------------------------------------------------------- 287 */ 288 bl plat_get_my_entrypoint 289 cbz x0, do_cold_boot 290 br x0 291 292 do_cold_boot: 293 .endif /* _warm_boot_mailbox */ 294 295 .if \_pie_fixup_size 296#if ENABLE_PIE 297 /* 298 * ------------------------------------------------------------ 299 * If PIE is enabled fixup the Global descriptor Table only 300 * once during primary core cold boot path. 301 * 302 * Compile time base address, required for fixup, is calculated 303 * using "pie_fixup" label present within first page. 304 * ------------------------------------------------------------ 305 */ 306 pie_fixup: 307 ldr x0, =pie_fixup 308 and x0, x0, #~(PAGE_SIZE - 1) 309 mov_imm x1, \_pie_fixup_size 310 add x1, x1, x0 311 bl fixup_gdt_reloc 312#endif /* ENABLE_PIE */ 313 .endif /* _pie_fixup_size */ 314 315 /* --------------------------------------------------------------------- 316 * Set the exception vectors. 317 * --------------------------------------------------------------------- 318 */ 319 adr x0, \_exception_vectors 320 msr vbar_el3, x0 321 isb 322 323 /* --------------------------------------------------------------------- 324 * It is a cold boot. 325 * Perform any processor specific actions upon reset e.g. cache, TLB 326 * invalidations etc. 327 * --------------------------------------------------------------------- 328 */ 329 bl reset_handler 330 331 el3_arch_init_common 332 333 .if \_secondary_cold_boot 334 /* ------------------------------------------------------------- 335 * Check if this is a primary or secondary CPU cold boot. 336 * The primary CPU will set up the platform while the 337 * secondaries are placed in a platform-specific state until the 338 * primary CPU performs the necessary actions to bring them out 339 * of that state and allows entry into the OS. 340 * ------------------------------------------------------------- 341 */ 342 bl plat_is_my_cpu_primary 343 cbnz w0, do_primary_cold_boot 344 345 /* This is a cold boot on a secondary CPU */ 346 bl plat_secondary_cold_boot_setup 347 /* plat_secondary_cold_boot_setup() is not supposed to return */ 348 bl el3_panic 349 350 do_primary_cold_boot: 351 .endif /* _secondary_cold_boot */ 352 353 /* --------------------------------------------------------------------- 354 * Initialize memory now. Secondary CPU initialization won't get to this 355 * point. 356 * --------------------------------------------------------------------- 357 */ 358 359 .if \_init_memory 360 bl platform_mem_init 361 .endif /* _init_memory */ 362 363 /* --------------------------------------------------------------------- 364 * Init C runtime environment: 365 * - Zero-initialise the NOBITS sections. There are 2 of them: 366 * - the .bss section; 367 * - the coherent memory section (if any). 368 * - Relocate the data section from ROM to RAM, if required. 369 * --------------------------------------------------------------------- 370 */ 371 .if \_init_c_runtime 372#if defined(IMAGE_BL31) || (defined(IMAGE_BL2) && BL2_AT_EL3 && BL2_INV_DCACHE) 373 /* ------------------------------------------------------------- 374 * Invalidate the RW memory used by the BL31 image. This 375 * includes the data and NOBITS sections. This is done to 376 * safeguard against possible corruption of this memory by 377 * dirty cache lines in a system cache as a result of use by 378 * an earlier boot loader stage. 379 * ------------------------------------------------------------- 380 */ 381 adrp x0, __RW_START__ 382 add x0, x0, :lo12:__RW_START__ 383 adrp x1, __RW_END__ 384 add x1, x1, :lo12:__RW_END__ 385 sub x1, x1, x0 386 bl inv_dcache_range 387#if defined(IMAGE_BL31) && SEPARATE_NOBITS_REGION 388 adrp x0, __NOBITS_START__ 389 add x0, x0, :lo12:__NOBITS_START__ 390 adrp x1, __NOBITS_END__ 391 add x1, x1, :lo12:__NOBITS_END__ 392 sub x1, x1, x0 393 bl inv_dcache_range 394#endif 395#endif 396 adrp x0, __BSS_START__ 397 add x0, x0, :lo12:__BSS_START__ 398 399 adrp x1, __BSS_END__ 400 add x1, x1, :lo12:__BSS_END__ 401 sub x1, x1, x0 402 bl zeromem 403 404#if USE_COHERENT_MEM 405 adrp x0, __COHERENT_RAM_START__ 406 add x0, x0, :lo12:__COHERENT_RAM_START__ 407 adrp x1, __COHERENT_RAM_END_UNALIGNED__ 408 add x1, x1, :lo12: __COHERENT_RAM_END_UNALIGNED__ 409 sub x1, x1, x0 410 bl zeromem 411#endif 412 413#if defined(IMAGE_BL1) || (defined(IMAGE_BL2) && BL2_AT_EL3 && BL2_IN_XIP_MEM) 414 adrp x0, __DATA_RAM_START__ 415 add x0, x0, :lo12:__DATA_RAM_START__ 416 adrp x1, __DATA_ROM_START__ 417 add x1, x1, :lo12:__DATA_ROM_START__ 418 adrp x2, __DATA_RAM_END__ 419 add x2, x2, :lo12:__DATA_RAM_END__ 420 sub x2, x2, x0 421 bl memcpy16 422#endif 423 .endif /* _init_c_runtime */ 424 425 /* --------------------------------------------------------------------- 426 * Use SP_EL0 for the C runtime stack. 427 * --------------------------------------------------------------------- 428 */ 429 msr spsel, #0 430 431 /* --------------------------------------------------------------------- 432 * Allocate a stack whose memory will be marked as Normal-IS-WBWA when 433 * the MMU is enabled. There is no risk of reading stale stack memory 434 * after enabling the MMU as only the primary CPU is running at the 435 * moment. 436 * --------------------------------------------------------------------- 437 */ 438 bl plat_set_my_stack 439 440#if STACK_PROTECTOR_ENABLED 441 .if \_init_c_runtime 442 bl update_stack_protector_canary 443 .endif /* _init_c_runtime */ 444#endif 445 .endm 446 447 .macro apply_at_speculative_wa 448#if ERRATA_SPECULATIVE_AT 449 /* 450 * Explicitly save x30 so as to free up a register and to enable 451 * branching and also, save x29 which will be used in the called 452 * function 453 */ 454 stp x29, x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29] 455 bl save_and_update_ptw_el1_sys_regs 456 ldp x29, x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29] 457#endif 458 .endm 459 460 .macro restore_ptw_el1_sys_regs 461#if ERRATA_SPECULATIVE_AT 462 /* ----------------------------------------------------------- 463 * In case of ERRATA_SPECULATIVE_AT, must follow below order 464 * to ensure that page table walk is not enabled until 465 * restoration of all EL1 system registers. TCR_EL1 register 466 * should be updated at the end which restores previous page 467 * table walk setting of stage1 i.e.(TCR_EL1.EPDx) bits. ISB 468 * ensures that CPU does below steps in order. 469 * 470 * 1. Ensure all other system registers are written before 471 * updating SCTLR_EL1 using ISB. 472 * 2. Restore SCTLR_EL1 register. 473 * 3. Ensure SCTLR_EL1 written successfully using ISB. 474 * 4. Restore TCR_EL1 register. 475 * ----------------------------------------------------------- 476 */ 477 isb 478 ldp x28, x29, [sp, #CTX_EL1_SYSREGS_OFFSET + CTX_SCTLR_EL1] 479 msr sctlr_el1, x28 480 isb 481 msr tcr_el1, x29 482#endif 483 .endm 484 485#endif /* EL3_COMMON_MACROS_S */ 486