1/* 2 * Copyright (c) 2015-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#ifndef EL3_COMMON_MACROS_S 8#define EL3_COMMON_MACROS_S 9 10#include <arch.h> 11#include <asm_macros.S> 12#include <assert_macros.S> 13#include <context.h> 14#include <lib/xlat_tables/xlat_tables_defs.h> 15 16 /* 17 * Helper macro to initialise EL3 registers we care about. 18 */ 19 .macro el3_arch_init_common 20 /* --------------------------------------------------------------------- 21 * SCTLR_EL3 has already been initialised - read current value before 22 * modifying. 23 * 24 * SCTLR_EL3.I: Enable the instruction cache. 25 * 26 * SCTLR_EL3.SA: Enable Stack Alignment check. A SP alignment fault 27 * exception is generated if a load or store instruction executed at 28 * EL3 uses the SP as the base address and the SP is not aligned to a 29 * 16-byte boundary. 30 * 31 * SCTLR_EL3.A: Enable Alignment fault checking. All instructions that 32 * load or store one or more registers have an alignment check that the 33 * address being accessed is aligned to the size of the data element(s) 34 * being accessed. 35 * 36 * SCTLR_EL3.BT: PAuth instructions are compatible with bti jc 37 * --------------------------------------------------------------------- 38 */ 39 mov_imm x1, (SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT) 40 mrs x0, sctlr_el3 41#if ENABLE_BTI 42 bic x0, x0, #SCTLR_BT_BIT 43#endif 44 orr x0, x0, x1 45 msr sctlr_el3, x0 46 isb 47 48#if ENABLE_FEAT_SCTLR2 49#if ENABLE_FEAT_SCTLR2 > 1 50 is_feat_sctlr2_present_asm x1 51 beq feat_sctlr2_not_supported\@ 52#endif 53 mov x1, #SCTLR2_RESET_VAL 54 msr SCTLR2_EL3, x1 55feat_sctlr2_not_supported\@: 56#endif 57 58#ifdef IMAGE_BL31 59 /* --------------------------------------------------------------------- 60 * Initialise the per-cpu cache pointer to the CPU. 61 * This is done early to enable crash reporting to have access to crash 62 * stack. Since crash reporting depends on cpu_data to report the 63 * unhandled exception, not doing so can lead to recursive exceptions 64 * due to a NULL TPIDR_EL3. 65 * --------------------------------------------------------------------- 66 */ 67 bl plat_my_core_pos 68 bl _cpu_data_by_index 69 msr tpidr_el3, x0 70#endif /* IMAGE_BL31 */ 71 72 /* --------------------------------------------------------------------- 73 * Initialise SCR_EL3, setting all fields rather than relying on hw. 74 * All fields are architecturally UNKNOWN on reset. The following fields 75 * do not change during the TF lifetime. The remaining fields are set to 76 * zero here but are updated ahead of transitioning to a lower EL in the 77 * function cm_init_context_common(). 78 * 79 * SCR_EL3.EEL2: Set to one if S-EL2 is present and enabled. 80 * 81 * NOTE: Modifying EEL2 bit along with EA bit ensures that we mitigate 82 * against ERRATA_V2_3099206. 83 * --------------------------------------------------------------------- 84 */ 85 mov_imm x0, SCR_RESET_VAL 86#if IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2 87 mrs x1, id_aa64pfr0_el1 88 and x1, x1, #(ID_AA64PFR0_SEL2_MASK << ID_AA64PFR0_SEL2_SHIFT) 89 cbz x1, 1f 90 orr x0, x0, #SCR_EEL2_BIT 91#endif 921: 93 msr scr_el3, x0 94 95 /* --------------------------------------------------------------------- 96 * Initialise MDCR_EL3, setting all fields rather than relying on hw. 97 * Some fields are architecturally UNKNOWN on reset. 98 */ 99 mov_imm x0, MDCR_EL3_RESET_VAL 100 msr mdcr_el3, x0 101 102 /* --------------------------------------------------------------------- 103 * Initialise CPTR_EL3, setting all fields rather than relying on hw. 104 * All fields are architecturally UNKNOWN on reset. 105 * --------------------------------------------------------------------- 106 */ 107 mov_imm x0, CPTR_EL3_RESET_VAL 108 msr cptr_el3, x0 109 110 .endm 111 112/* ----------------------------------------------------------------------------- 113 * This is the super set of actions that need to be performed during a cold boot 114 * or a warm boot in EL3. This code is shared by BL1 and BL31. 115 * 116 * This macro will always perform reset handling, architectural initialisations 117 * and stack setup. The rest of the actions are optional because they might not 118 * be needed, depending on the context in which this macro is called. This is 119 * why this macro is parameterised ; each parameter allows to enable/disable 120 * some actions. 121 * 122 * _init_sctlr: 123 * Whether the macro needs to initialise SCTLR_EL3, including configuring 124 * the endianness of data accesses. 125 * 126 * _warm_boot_mailbox: 127 * Whether the macro needs to detect the type of boot (cold/warm). The 128 * detection is based on the platform entrypoint address : if it is zero 129 * then it is a cold boot, otherwise it is a warm boot. In the latter case, 130 * this macro jumps on the platform entrypoint address. 131 * 132 * _secondary_cold_boot: 133 * Whether the macro needs to identify the CPU that is calling it: primary 134 * CPU or secondary CPU. The primary CPU will be allowed to carry on with 135 * the platform initialisations, while the secondaries will be put in a 136 * platform-specific state in the meantime. 137 * 138 * If the caller knows this macro will only be called by the primary CPU 139 * then this parameter can be defined to 0 to skip this step. 140 * 141 * _init_memory: 142 * Whether the macro needs to initialise the memory. 143 * 144 * _init_c_runtime: 145 * Whether the macro needs to initialise the C runtime environment. 146 * 147 * _exception_vectors: 148 * Address of the exception vectors to program in the VBAR_EL3 register. 149 * 150 * _pie_fixup_size: 151 * Size of memory region to fixup Global Descriptor Table (GDT). 152 * 153 * A non-zero value is expected when firmware needs GDT to be fixed-up. 154 * 155 * ----------------------------------------------------------------------------- 156 */ 157 .macro el3_entrypoint_common \ 158 _init_sctlr, _warm_boot_mailbox, _secondary_cold_boot, \ 159 _init_memory, _init_c_runtime, _exception_vectors, \ 160 _pie_fixup_size 161 162 .if \_init_sctlr 163 /* ------------------------------------------------------------- 164 * This is the initialisation of SCTLR_EL3 and so must ensure 165 * that all fields are explicitly set rather than relying on hw. 166 * Some fields reset to an IMPLEMENTATION DEFINED value and 167 * others are architecturally UNKNOWN on reset. 168 * 169 * SCTLR.EE: Set the CPU endianness before doing anything that 170 * might involve memory reads or writes. Set to zero to select 171 * Little Endian. 172 * 173 * SCTLR_EL3.WXN: For the EL3 translation regime, this field can 174 * force all memory regions that are writeable to be treated as 175 * XN (Execute-never). Set to zero so that this control has no 176 * effect on memory access permissions. 177 * 178 * SCTLR_EL3.SA: Set to zero to disable Stack Alignment check. 179 * 180 * SCTLR_EL3.A: Set to zero to disable Alignment fault checking. 181 * 182 * SCTLR.DSSBS: Set to zero to disable speculation store bypass 183 * safe behaviour upon exception entry to EL3. 184 * ------------------------------------------------------------- 185 */ 186 mov_imm x0, (SCTLR_RESET_VAL & ~(SCTLR_EE_BIT | SCTLR_WXN_BIT \ 187 | SCTLR_SA_BIT | SCTLR_A_BIT | SCTLR_DSSBS_BIT)) 188#if ENABLE_FEAT_RAS 189 /* If FEAT_RAS is present assume FEAT_IESB is also present */ 190 orr x0, x0, #SCTLR_IESB_BIT 191#endif 192 msr sctlr_el3, x0 193 isb 194 .endif /* _init_sctlr */ 195 196 .if \_warm_boot_mailbox 197 /* ------------------------------------------------------------- 198 * This code will be executed for both warm and cold resets. 199 * Now is the time to distinguish between the two. 200 * Query the platform entrypoint address and if it is not zero 201 * then it means it is a warm boot so jump to this address. 202 * ------------------------------------------------------------- 203 */ 204 bl plat_get_my_entrypoint 205 cbz x0, do_cold_boot 206 br x0 207 208 do_cold_boot: 209 .endif /* _warm_boot_mailbox */ 210 211 .if \_pie_fixup_size 212#if ENABLE_PIE 213 /* 214 * ------------------------------------------------------------ 215 * If PIE is enabled fixup the Global descriptor Table only 216 * once during primary core cold boot path. 217 * 218 * Compile time base address, required for fixup, is calculated 219 * using "pie_fixup" label present within first page. 220 * ------------------------------------------------------------ 221 */ 222 pie_fixup: 223 ldr x0, =pie_fixup 224 and x0, x0, #~(PAGE_SIZE_MASK) 225 mov_imm x1, \_pie_fixup_size 226 add x1, x1, x0 227 bl fixup_gdt_reloc 228#endif /* ENABLE_PIE */ 229 .endif /* _pie_fixup_size */ 230 231 /* --------------------------------------------------------------------- 232 * Set the exception vectors. 233 * --------------------------------------------------------------------- 234 */ 235 adr x0, \_exception_vectors 236 msr vbar_el3, x0 237 isb 238 239 call_reset_handler 240 241 el3_arch_init_common 242 243 /* --------------------------------------------------------------------- 244 * Set the el3 execution context(i.e. root_context). 245 * --------------------------------------------------------------------- 246 */ 247 setup_el3_execution_context 248 249 .if \_secondary_cold_boot 250 /* ------------------------------------------------------------- 251 * Check if this is a primary or secondary CPU cold boot. 252 * The primary CPU will set up the platform while the 253 * secondaries are placed in a platform-specific state until the 254 * primary CPU performs the necessary actions to bring them out 255 * of that state and allows entry into the OS. 256 * ------------------------------------------------------------- 257 */ 258 bl plat_is_my_cpu_primary 259 cbnz w0, do_primary_cold_boot 260 261 /* This is a cold boot on a secondary CPU */ 262 bl plat_secondary_cold_boot_setup 263 /* plat_secondary_cold_boot_setup() is not supposed to return */ 264 bl el3_panic 265 266 do_primary_cold_boot: 267 .endif /* _secondary_cold_boot */ 268 269 /* --------------------------------------------------------------------- 270 * Initialize memory now. Secondary CPU initialization won't get to this 271 * point. 272 * --------------------------------------------------------------------- 273 */ 274 275 .if \_init_memory 276 bl platform_mem_init 277 .endif /* _init_memory */ 278 279 /* --------------------------------------------------------------------- 280 * Init C runtime environment: 281 * - Zero-initialise the NOBITS sections. There are 2 of them: 282 * - the .bss section; 283 * - the coherent memory section (if any). 284 * - Relocate the data section from ROM to RAM, if required. 285 * --------------------------------------------------------------------- 286 */ 287 .if \_init_c_runtime 288#if defined(IMAGE_BL31) || (defined(IMAGE_BL2) && \ 289 ((RESET_TO_BL2 && BL2_INV_DCACHE) || ENABLE_RME)) 290 /* ------------------------------------------------------------- 291 * Invalidate the RW memory used by the BL31 image. This 292 * includes the data and NOBITS sections. This is done to 293 * safeguard against possible corruption of this memory by 294 * dirty cache lines in a system cache as a result of use by 295 * an earlier boot loader stage. If PIE is enabled however, 296 * RO sections including the GOT may be modified during 297 * pie fixup. Therefore, to be on the safe side, invalidate 298 * the entire image region if PIE is enabled. 299 * ------------------------------------------------------------- 300 */ 301#if ENABLE_PIE 302#if SEPARATE_CODE_AND_RODATA 303 adrp x0, __TEXT_START__ 304 add x0, x0, :lo12:__TEXT_START__ 305#else 306 adrp x0, __RO_START__ 307 add x0, x0, :lo12:__RO_START__ 308#endif /* SEPARATE_CODE_AND_RODATA */ 309#else 310 adrp x0, __RW_START__ 311 add x0, x0, :lo12:__RW_START__ 312#endif /* ENABLE_PIE */ 313 adrp x1, __RW_END__ 314 add x1, x1, :lo12:__RW_END__ 315 sub x1, x1, x0 316 bl inv_dcache_range 317#if defined(IMAGE_BL31) && SEPARATE_NOBITS_REGION 318 adrp x0, __NOBITS_START__ 319 add x0, x0, :lo12:__NOBITS_START__ 320 adrp x1, __NOBITS_END__ 321 add x1, x1, :lo12:__NOBITS_END__ 322 sub x1, x1, x0 323 bl inv_dcache_range 324#endif 325#if defined(IMAGE_BL2) && SEPARATE_BL2_NOLOAD_REGION 326 adrp x0, __BL2_NOLOAD_START__ 327 add x0, x0, :lo12:__BL2_NOLOAD_START__ 328 adrp x1, __BL2_NOLOAD_END__ 329 add x1, x1, :lo12:__BL2_NOLOAD_END__ 330 sub x1, x1, x0 331 bl inv_dcache_range 332#endif 333#endif 334 adrp x0, __BSS_START__ 335 add x0, x0, :lo12:__BSS_START__ 336 337 adrp x1, __BSS_END__ 338 add x1, x1, :lo12:__BSS_END__ 339 sub x1, x1, x0 340 bl zeromem 341 342#if USE_COHERENT_MEM 343 adrp x0, __COHERENT_RAM_START__ 344 add x0, x0, :lo12:__COHERENT_RAM_START__ 345 adrp x1, __COHERENT_RAM_END_UNALIGNED__ 346 add x1, x1, :lo12: __COHERENT_RAM_END_UNALIGNED__ 347 sub x1, x1, x0 348 bl zeromem 349#endif 350 351#if defined(IMAGE_BL1) || \ 352 (defined(IMAGE_BL2) && RESET_TO_BL2 && BL2_IN_XIP_MEM) || \ 353 (defined(IMAGE_BL31) && SEPARATE_RWDATA_REGION) 354 355 adrp x0, __DATA_RAM_START__ 356 add x0, x0, :lo12:__DATA_RAM_START__ 357 adrp x1, __DATA_ROM_START__ 358 add x1, x1, :lo12:__DATA_ROM_START__ 359 adrp x2, __DATA_RAM_END__ 360 add x2, x2, :lo12:__DATA_RAM_END__ 361 sub x2, x2, x0 362 bl memcpy16 363#endif 364 .endif /* _init_c_runtime */ 365 366 /* --------------------------------------------------------------------- 367 * Use SP_EL0 for the C runtime stack. 368 * --------------------------------------------------------------------- 369 */ 370 msr spsel, #0 371 372 /* --------------------------------------------------------------------- 373 * Allocate a stack whose memory will be marked as Normal-IS-WBWA when 374 * the MMU is enabled. There is no risk of reading stale stack memory 375 * after enabling the MMU as only the primary CPU is running at the 376 * moment. 377 * --------------------------------------------------------------------- 378 */ 379 bl plat_set_my_stack 380 381#if STACK_PROTECTOR_ENABLED 382 .if \_init_c_runtime 383 bl update_stack_protector_canary 384 .endif /* _init_c_runtime */ 385#endif 386 .endm 387 388 .macro apply_at_speculative_wa 389#if ERRATA_SPECULATIVE_AT 390 /* 391 * This function expects x30 has been saved. 392 * Also, save x29 which will be used in the called function. 393 */ 394 str x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29] 395 bl save_and_update_ptw_el1_sys_regs 396 ldr x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29] 397#endif 398 .endm 399 400 .macro restore_ptw_el1_sys_regs 401#if ERRATA_SPECULATIVE_AT 402 /* ----------------------------------------------------------- 403 * In case of ERRATA_SPECULATIVE_AT, must follow below order 404 * to ensure that page table walk is not enabled until 405 * restoration of all EL1 system registers. TCR_EL1 register 406 * should be updated at the end which restores previous page 407 * table walk setting of stage1 i.e.(TCR_EL1.EPDx) bits. ISB 408 * ensures that CPU does below steps in order. 409 * 410 * 1. Ensure all other system registers are written before 411 * updating SCTLR_EL1 using ISB. 412 * 2. Restore SCTLR_EL1 register. 413 * 3. Ensure SCTLR_EL1 written successfully using ISB. 414 * 4. Restore TCR_EL1 register. 415 * ----------------------------------------------------------- 416 */ 417 isb 418 ldp x28, x29, [sp, #CTX_ERRATA_SPEC_AT_OFFSET + CTX_ERRATA_SPEC_AT_SCTLR_EL1] 419 msr sctlr_el1, x28 420 isb 421 msr tcr_el1, x29 422#endif 423 .endm 424 425/* ----------------------------------------------------------------- 426 * The below macro reads SCR_EL3 from the context structure to 427 * determine the security state of the context upon ERET. 428 * ------------------------------------------------------------------ 429 */ 430 .macro get_security_state _ret:req, _scr_reg:req 431 ubfx \_ret, \_scr_reg, #SCR_NSE_SHIFT, #1 432 cmp \_ret, #1 433 beq realm_state 434 bfi \_ret, \_scr_reg, #0, #1 435 b end 436 realm_state: 437 mov \_ret, #2 438 end: 439 .endm 440 441/*----------------------------------------------------------------------------- 442 * Helper macro to configure EL3 registers we care about, while executing 443 * at EL3/Root world. Root world has its own execution environment and 444 * needs to have its settings configured to be independent of other worlds. 445 * ----------------------------------------------------------------------------- 446 */ 447 .macro setup_el3_execution_context 448 449 /* --------------------------------------------------------------------- 450 * The following registers need to be part of separate root context 451 * as their values are of importance during EL3 execution. 452 * Hence these registers are overwritten to their intital values, 453 * irrespective of whichever world they return from to ensure EL3 has a 454 * consistent execution context throughout the lifetime of TF-A. 455 * 456 * DAIF.A: Enable External Aborts and SError Interrupts at EL3. 457 * 458 * MDCR_EL3.SDD: Set to one to disable AArch64 Secure self-hosted debug. 459 * Debug exceptions, other than Breakpoint Instruction exceptions, are 460 * disabled from all ELs in Secure state. 461 * 462 * SCR_EL3.EA: Set to one to enable SError interrupts at EL3. 463 * 464 * SCR_EL3.SIF: Set to one to disable instruction fetches from 465 * Non-secure memory. 466 * 467 * PMCR_EL0.DP: Set to one so that the cycle counter, 468 * PMCCNTR_EL0 does not count when event counting is prohibited. 469 * Necessary on PMUv3 <= p7 where MDCR_EL3.{SCCD,MCCD} are not 470 * available. 471 * 472 * CPTR_EL3.EZ: Set to one so that accesses to ZCR_EL3 do not trap 473 * CPTR_EL3.TFP: Set to zero so that advanced SIMD operations don't trap 474 * CPTR_EL3.ESM: Set to one so that SME related registers don't trap 475 * 476 * PSTATE.DIT: Set to one to enable the Data Independent Timing (DIT) 477 * functionality, if implemented in EL3. 478 * --------------------------------------------------------------------- 479 */ 480 msr daifclr, #DAIF_ABT_BIT 481 482 mrs x15, mdcr_el3 483 orr x15, x15, #MDCR_SDD_BIT 484 msr mdcr_el3, x15 485 486 mrs x15, scr_el3 487 orr x15, x15, #SCR_EA_BIT 488 orr x15, x15, #SCR_SIF_BIT 489 msr scr_el3, x15 490 491 mrs x15, pmcr_el0 492 orr x15, x15, #PMCR_EL0_DP_BIT 493 msr pmcr_el0, x15 494 495 mrs x15, cptr_el3 496 orr x15, x15, #CPTR_EZ_BIT 497 orr x15, x15, #ESM_BIT 498 bic x15, x15, #TFP_BIT 499 msr cptr_el3, x15 500 501#if ENABLE_FEAT_DIT 502#if ENABLE_FEAT_DIT > 1 503 mrs x15, id_aa64pfr0_el1 504 ubfx x15, x15, #ID_AA64PFR0_DIT_SHIFT, #ID_AA64PFR0_DIT_LENGTH 505 cbz x15, 1f 506#endif 507 mov x15, #DIT_BIT 508 msr DIT, x15 509 1: 510#endif 511 512 isb 513 .endm 514 515#endif /* EL3_COMMON_MACROS_S */ 516