1 /* 2 * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef ARCH_HELPERS_H 8 #define ARCH_HELPERS_H 9 10 #include <arch.h> 11 #include <cdefs.h> 12 #include <stdbool.h> 13 #include <stdint.h> 14 #include <string.h> 15 16 /********************************************************************** 17 * Macros which create inline functions to read or write CPU system 18 * registers 19 *********************************************************************/ 20 21 #define _DEFINE_SYSREG_READ_FUNC(_name, _reg_name) \ 22 static inline u_register_t read_ ## _name(void) \ 23 { \ 24 u_register_t v; \ 25 __asm__ volatile ("mrs %0, " #_reg_name : "=r" (v)); \ 26 return v; \ 27 } 28 29 #define _DEFINE_SYSREG_WRITE_FUNC(_name, _reg_name) \ 30 static inline void write_ ## _name(u_register_t v) \ 31 { \ 32 __asm__ volatile ("msr " #_reg_name ", %0" : : "r" (v)); \ 33 } 34 35 #define SYSREG_WRITE_CONST(reg_name, v) \ 36 __asm__ volatile ("msr " #reg_name ", %0" : : "i" (v)) 37 38 /* Define read function for system register */ 39 #define DEFINE_SYSREG_READ_FUNC(_name) \ 40 _DEFINE_SYSREG_READ_FUNC(_name, _name) 41 42 /* Define read & write function for system register */ 43 #define DEFINE_SYSREG_RW_FUNCS(_name) \ 44 _DEFINE_SYSREG_READ_FUNC(_name, _name) \ 45 _DEFINE_SYSREG_WRITE_FUNC(_name, _name) 46 47 /* Define read & write function for renamed system register */ 48 #define DEFINE_RENAME_SYSREG_RW_FUNCS(_name, _reg_name) \ 49 _DEFINE_SYSREG_READ_FUNC(_name, _reg_name) \ 50 _DEFINE_SYSREG_WRITE_FUNC(_name, _reg_name) 51 52 /* Define read function for renamed system register */ 53 #define DEFINE_RENAME_SYSREG_READ_FUNC(_name, _reg_name) \ 54 _DEFINE_SYSREG_READ_FUNC(_name, _reg_name) 55 56 /* Define write function for renamed system register */ 57 #define DEFINE_RENAME_SYSREG_WRITE_FUNC(_name, _reg_name) \ 58 _DEFINE_SYSREG_WRITE_FUNC(_name, _reg_name) 59 60 /********************************************************************** 61 * Macros to create inline functions for system instructions 62 *********************************************************************/ 63 64 /* Define function for simple system instruction */ 65 #define DEFINE_SYSOP_FUNC(_op) \ 66 static inline void _op(void) \ 67 { \ 68 __asm__ (#_op); \ 69 } 70 71 /* Define function for system instruction with type specifier */ 72 #define DEFINE_SYSOP_TYPE_FUNC(_op, _type) \ 73 static inline void _op ## _type(void) \ 74 { \ 75 __asm__ (#_op " " #_type); \ 76 } 77 78 /* Define function for system instruction with register parameter */ 79 #define DEFINE_SYSOP_TYPE_PARAM_FUNC(_op, _type) \ 80 static inline void _op ## _type(uint64_t v) \ 81 { \ 82 __asm__ (#_op " " #_type ", %0" : : "r" (v)); \ 83 } 84 85 /******************************************************************************* 86 * TLB maintenance accessor prototypes 87 ******************************************************************************/ 88 89 #if ERRATA_A57_813419 90 /* 91 * Define function for TLBI instruction with type specifier that implements 92 * the workaround for errata 813419 of Cortex-A57. 93 */ 94 #define DEFINE_TLBIOP_ERRATA_A57_813419_TYPE_FUNC(_type)\ 95 static inline void tlbi ## _type(void) \ 96 { \ 97 __asm__("tlbi " #_type "\n" \ 98 "dsb ish\n" \ 99 "tlbi " #_type); \ 100 } 101 102 /* 103 * Define function for TLBI instruction with register parameter that implements 104 * the workaround for errata 813419 of Cortex-A57. 105 */ 106 #define DEFINE_TLBIOP_ERRATA_A57_813419_TYPE_PARAM_FUNC(_type) \ 107 static inline void tlbi ## _type(uint64_t v) \ 108 { \ 109 __asm__("tlbi " #_type ", %0\n" \ 110 "dsb ish\n" \ 111 "tlbi " #_type ", %0" : : "r" (v)); \ 112 } 113 #endif /* ERRATA_A57_813419 */ 114 115 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle1) 116 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle1is) 117 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle2) 118 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle2is) 119 #if ERRATA_A57_813419 120 DEFINE_TLBIOP_ERRATA_A57_813419_TYPE_FUNC(alle3) 121 DEFINE_TLBIOP_ERRATA_A57_813419_TYPE_FUNC(alle3is) 122 #else 123 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle3) 124 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle3is) 125 #endif 126 DEFINE_SYSOP_TYPE_FUNC(tlbi, vmalle1) 127 128 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vaae1is) 129 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vaale1is) 130 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vae2is) 131 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vale2is) 132 #if ERRATA_A57_813419 133 DEFINE_TLBIOP_ERRATA_A57_813419_TYPE_PARAM_FUNC(vae3is) 134 DEFINE_TLBIOP_ERRATA_A57_813419_TYPE_PARAM_FUNC(vale3is) 135 #else 136 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vae3is) 137 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vale3is) 138 #endif 139 140 /******************************************************************************* 141 * Cache maintenance accessor prototypes 142 ******************************************************************************/ 143 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, isw) 144 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, cisw) 145 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, csw) 146 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, cvac) 147 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, ivac) 148 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, civac) 149 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, cvau) 150 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, zva) 151 152 /******************************************************************************* 153 * Address translation accessor prototypes 154 ******************************************************************************/ 155 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e1r) 156 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e1w) 157 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e0r) 158 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e0w) 159 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s1e1r) 160 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s1e2r) 161 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s1e3r) 162 163 void flush_dcache_range(uintptr_t addr, size_t size); 164 void clean_dcache_range(uintptr_t addr, size_t size); 165 void inv_dcache_range(uintptr_t addr, size_t size); 166 167 void dcsw_op_louis(u_register_t op_type); 168 void dcsw_op_all(u_register_t op_type); 169 170 void disable_mmu_el1(void); 171 void disable_mmu_el3(void); 172 void disable_mmu_icache_el1(void); 173 void disable_mmu_icache_el3(void); 174 175 /******************************************************************************* 176 * Misc. accessor prototypes 177 ******************************************************************************/ 178 179 #define write_daifclr(val) SYSREG_WRITE_CONST(daifclr, val) 180 #define write_daifset(val) SYSREG_WRITE_CONST(daifset, val) 181 182 DEFINE_SYSREG_RW_FUNCS(par_el1) 183 DEFINE_SYSREG_READ_FUNC(id_pfr1_el1) 184 DEFINE_SYSREG_READ_FUNC(id_aa64isar1_el1) 185 DEFINE_SYSREG_READ_FUNC(id_aa64pfr0_el1) 186 DEFINE_SYSREG_READ_FUNC(id_aa64dfr0_el1) 187 DEFINE_SYSREG_READ_FUNC(CurrentEl) 188 DEFINE_SYSREG_READ_FUNC(ctr_el0) 189 DEFINE_SYSREG_RW_FUNCS(daif) 190 DEFINE_SYSREG_RW_FUNCS(spsr_el1) 191 DEFINE_SYSREG_RW_FUNCS(spsr_el2) 192 DEFINE_SYSREG_RW_FUNCS(spsr_el3) 193 DEFINE_SYSREG_RW_FUNCS(elr_el1) 194 DEFINE_SYSREG_RW_FUNCS(elr_el2) 195 DEFINE_SYSREG_RW_FUNCS(elr_el3) 196 197 DEFINE_SYSOP_FUNC(wfi) 198 DEFINE_SYSOP_FUNC(wfe) 199 DEFINE_SYSOP_FUNC(sev) 200 DEFINE_SYSOP_TYPE_FUNC(dsb, sy) 201 DEFINE_SYSOP_TYPE_FUNC(dmb, sy) 202 DEFINE_SYSOP_TYPE_FUNC(dmb, st) 203 DEFINE_SYSOP_TYPE_FUNC(dmb, ld) 204 DEFINE_SYSOP_TYPE_FUNC(dsb, ish) 205 DEFINE_SYSOP_TYPE_FUNC(dsb, nsh) 206 DEFINE_SYSOP_TYPE_FUNC(dsb, ishst) 207 DEFINE_SYSOP_TYPE_FUNC(dmb, oshld) 208 DEFINE_SYSOP_TYPE_FUNC(dmb, oshst) 209 DEFINE_SYSOP_TYPE_FUNC(dmb, osh) 210 DEFINE_SYSOP_TYPE_FUNC(dmb, nshld) 211 DEFINE_SYSOP_TYPE_FUNC(dmb, nshst) 212 DEFINE_SYSOP_TYPE_FUNC(dmb, nsh) 213 DEFINE_SYSOP_TYPE_FUNC(dmb, ishld) 214 DEFINE_SYSOP_TYPE_FUNC(dmb, ishst) 215 DEFINE_SYSOP_TYPE_FUNC(dmb, ish) 216 DEFINE_SYSOP_FUNC(isb) 217 218 static inline void enable_irq(void) 219 { 220 /* 221 * The compiler memory barrier will prevent the compiler from 222 * scheduling non-volatile memory access after the write to the 223 * register. 224 * 225 * This could happen if some initialization code issues non-volatile 226 * accesses to an area used by an interrupt handler, in the assumption 227 * that it is safe as the interrupts are disabled at the time it does 228 * that (according to program order). However, non-volatile accesses 229 * are not necessarily in program order relatively with volatile inline 230 * assembly statements (and volatile accesses). 231 */ 232 COMPILER_BARRIER(); 233 write_daifclr(DAIF_IRQ_BIT); 234 isb(); 235 } 236 237 static inline void enable_fiq(void) 238 { 239 COMPILER_BARRIER(); 240 write_daifclr(DAIF_FIQ_BIT); 241 isb(); 242 } 243 244 static inline void enable_serror(void) 245 { 246 COMPILER_BARRIER(); 247 write_daifclr(DAIF_ABT_BIT); 248 isb(); 249 } 250 251 static inline void enable_debug_exceptions(void) 252 { 253 COMPILER_BARRIER(); 254 write_daifclr(DAIF_DBG_BIT); 255 isb(); 256 } 257 258 static inline void disable_irq(void) 259 { 260 COMPILER_BARRIER(); 261 write_daifset(DAIF_IRQ_BIT); 262 isb(); 263 } 264 265 static inline void disable_fiq(void) 266 { 267 COMPILER_BARRIER(); 268 write_daifset(DAIF_FIQ_BIT); 269 isb(); 270 } 271 272 static inline void disable_serror(void) 273 { 274 COMPILER_BARRIER(); 275 write_daifset(DAIF_ABT_BIT); 276 isb(); 277 } 278 279 static inline void disable_debug_exceptions(void) 280 { 281 COMPILER_BARRIER(); 282 write_daifset(DAIF_DBG_BIT); 283 isb(); 284 } 285 286 #if !ERROR_DEPRECATED 287 uint32_t get_afflvl_shift(uint32_t); 288 uint32_t mpidr_mask_lower_afflvls(uint64_t, uint32_t); 289 290 void __dead2 eret(uint64_t x0, uint64_t x1, uint64_t x2, uint64_t x3, 291 uint64_t x4, uint64_t x5, uint64_t x6, uint64_t x7); 292 #endif 293 void __dead2 smc(uint64_t x0, uint64_t x1, uint64_t x2, uint64_t x3, 294 uint64_t x4, uint64_t x5, uint64_t x6, uint64_t x7); 295 296 /******************************************************************************* 297 * System register accessor prototypes 298 ******************************************************************************/ 299 DEFINE_SYSREG_READ_FUNC(midr_el1) 300 DEFINE_SYSREG_READ_FUNC(mpidr_el1) 301 DEFINE_SYSREG_READ_FUNC(id_aa64mmfr0_el1) 302 303 DEFINE_SYSREG_RW_FUNCS(scr_el3) 304 DEFINE_SYSREG_RW_FUNCS(hcr_el2) 305 306 DEFINE_SYSREG_RW_FUNCS(vbar_el1) 307 DEFINE_SYSREG_RW_FUNCS(vbar_el2) 308 DEFINE_SYSREG_RW_FUNCS(vbar_el3) 309 310 DEFINE_SYSREG_RW_FUNCS(sctlr_el1) 311 DEFINE_SYSREG_RW_FUNCS(sctlr_el2) 312 DEFINE_SYSREG_RW_FUNCS(sctlr_el3) 313 314 DEFINE_SYSREG_RW_FUNCS(actlr_el1) 315 DEFINE_SYSREG_RW_FUNCS(actlr_el2) 316 DEFINE_SYSREG_RW_FUNCS(actlr_el3) 317 318 DEFINE_SYSREG_RW_FUNCS(esr_el1) 319 DEFINE_SYSREG_RW_FUNCS(esr_el2) 320 DEFINE_SYSREG_RW_FUNCS(esr_el3) 321 322 DEFINE_SYSREG_RW_FUNCS(afsr0_el1) 323 DEFINE_SYSREG_RW_FUNCS(afsr0_el2) 324 DEFINE_SYSREG_RW_FUNCS(afsr0_el3) 325 326 DEFINE_SYSREG_RW_FUNCS(afsr1_el1) 327 DEFINE_SYSREG_RW_FUNCS(afsr1_el2) 328 DEFINE_SYSREG_RW_FUNCS(afsr1_el3) 329 330 DEFINE_SYSREG_RW_FUNCS(far_el1) 331 DEFINE_SYSREG_RW_FUNCS(far_el2) 332 DEFINE_SYSREG_RW_FUNCS(far_el3) 333 334 DEFINE_SYSREG_RW_FUNCS(mair_el1) 335 DEFINE_SYSREG_RW_FUNCS(mair_el2) 336 DEFINE_SYSREG_RW_FUNCS(mair_el3) 337 338 DEFINE_SYSREG_RW_FUNCS(amair_el1) 339 DEFINE_SYSREG_RW_FUNCS(amair_el2) 340 DEFINE_SYSREG_RW_FUNCS(amair_el3) 341 342 DEFINE_SYSREG_READ_FUNC(rvbar_el1) 343 DEFINE_SYSREG_READ_FUNC(rvbar_el2) 344 DEFINE_SYSREG_READ_FUNC(rvbar_el3) 345 346 DEFINE_SYSREG_RW_FUNCS(rmr_el1) 347 DEFINE_SYSREG_RW_FUNCS(rmr_el2) 348 DEFINE_SYSREG_RW_FUNCS(rmr_el3) 349 350 DEFINE_SYSREG_RW_FUNCS(tcr_el1) 351 DEFINE_SYSREG_RW_FUNCS(tcr_el2) 352 DEFINE_SYSREG_RW_FUNCS(tcr_el3) 353 354 DEFINE_SYSREG_RW_FUNCS(ttbr0_el1) 355 DEFINE_SYSREG_RW_FUNCS(ttbr0_el2) 356 DEFINE_SYSREG_RW_FUNCS(ttbr0_el3) 357 358 DEFINE_SYSREG_RW_FUNCS(ttbr1_el1) 359 360 DEFINE_SYSREG_RW_FUNCS(vttbr_el2) 361 362 DEFINE_SYSREG_RW_FUNCS(cptr_el2) 363 DEFINE_SYSREG_RW_FUNCS(cptr_el3) 364 365 DEFINE_SYSREG_RW_FUNCS(cpacr_el1) 366 DEFINE_SYSREG_RW_FUNCS(cntfrq_el0) 367 DEFINE_SYSREG_RW_FUNCS(cnthp_ctl_el2) 368 DEFINE_SYSREG_RW_FUNCS(cnthp_tval_el2) 369 DEFINE_SYSREG_RW_FUNCS(cnthp_cval_el2) 370 DEFINE_SYSREG_RW_FUNCS(cntps_ctl_el1) 371 DEFINE_SYSREG_RW_FUNCS(cntps_tval_el1) 372 DEFINE_SYSREG_RW_FUNCS(cntps_cval_el1) 373 DEFINE_SYSREG_RW_FUNCS(cntp_ctl_el0) 374 DEFINE_SYSREG_RW_FUNCS(cntp_tval_el0) 375 DEFINE_SYSREG_RW_FUNCS(cntp_cval_el0) 376 DEFINE_SYSREG_READ_FUNC(cntpct_el0) 377 DEFINE_SYSREG_RW_FUNCS(cnthctl_el2) 378 379 #define get_cntp_ctl_enable(x) (((x) >> CNTP_CTL_ENABLE_SHIFT) & \ 380 CNTP_CTL_ENABLE_MASK) 381 #define get_cntp_ctl_imask(x) (((x) >> CNTP_CTL_IMASK_SHIFT) & \ 382 CNTP_CTL_IMASK_MASK) 383 #define get_cntp_ctl_istatus(x) (((x) >> CNTP_CTL_ISTATUS_SHIFT) & \ 384 CNTP_CTL_ISTATUS_MASK) 385 386 #define set_cntp_ctl_enable(x) ((x) |= (U(1) << CNTP_CTL_ENABLE_SHIFT)) 387 #define set_cntp_ctl_imask(x) ((x) |= (U(1) << CNTP_CTL_IMASK_SHIFT)) 388 389 #define clr_cntp_ctl_enable(x) ((x) &= ~(U(1) << CNTP_CTL_ENABLE_SHIFT)) 390 #define clr_cntp_ctl_imask(x) ((x) &= ~(U(1) << CNTP_CTL_IMASK_SHIFT)) 391 392 DEFINE_SYSREG_RW_FUNCS(tpidr_el3) 393 394 DEFINE_SYSREG_RW_FUNCS(cntvoff_el2) 395 396 DEFINE_SYSREG_RW_FUNCS(vpidr_el2) 397 DEFINE_SYSREG_RW_FUNCS(vmpidr_el2) 398 399 DEFINE_SYSREG_READ_FUNC(isr_el1) 400 401 DEFINE_SYSREG_RW_FUNCS(mdcr_el2) 402 DEFINE_SYSREG_RW_FUNCS(mdcr_el3) 403 DEFINE_SYSREG_RW_FUNCS(hstr_el2) 404 DEFINE_SYSREG_RW_FUNCS(pmcr_el0) 405 406 /* GICv3 System Registers */ 407 408 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el1, ICC_SRE_EL1) 409 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el2, ICC_SRE_EL2) 410 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el3, ICC_SRE_EL3) 411 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_pmr_el1, ICC_PMR_EL1) 412 DEFINE_RENAME_SYSREG_READ_FUNC(icc_rpr_el1, ICC_RPR_EL1) 413 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_igrpen1_el3, ICC_IGRPEN1_EL3) 414 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_igrpen1_el1, ICC_IGRPEN1_EL1) 415 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_igrpen0_el1, ICC_IGRPEN0_EL1) 416 DEFINE_RENAME_SYSREG_READ_FUNC(icc_hppir0_el1, ICC_HPPIR0_EL1) 417 DEFINE_RENAME_SYSREG_READ_FUNC(icc_hppir1_el1, ICC_HPPIR1_EL1) 418 DEFINE_RENAME_SYSREG_READ_FUNC(icc_iar0_el1, ICC_IAR0_EL1) 419 DEFINE_RENAME_SYSREG_READ_FUNC(icc_iar1_el1, ICC_IAR1_EL1) 420 DEFINE_RENAME_SYSREG_WRITE_FUNC(icc_eoir0_el1, ICC_EOIR0_EL1) 421 DEFINE_RENAME_SYSREG_WRITE_FUNC(icc_eoir1_el1, ICC_EOIR1_EL1) 422 DEFINE_RENAME_SYSREG_WRITE_FUNC(icc_sgi0r_el1, ICC_SGI0R_EL1) 423 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sgi1r, ICC_SGI1R) 424 425 DEFINE_RENAME_SYSREG_RW_FUNCS(amcgcr_el0, AMCGCR_EL0) 426 DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenclr0_el0, AMCNTENCLR0_EL0) 427 DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenset0_el0, AMCNTENSET0_EL0) 428 DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenclr1_el0, AMCNTENCLR1_EL0) 429 DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenset1_el0, AMCNTENSET1_EL0) 430 431 DEFINE_RENAME_SYSREG_READ_FUNC(mpamidr_el1, MPAMIDR_EL1) 432 DEFINE_RENAME_SYSREG_RW_FUNCS(mpam3_el3, MPAM3_EL3) 433 DEFINE_RENAME_SYSREG_RW_FUNCS(mpam2_el2, MPAM2_EL2) 434 DEFINE_RENAME_SYSREG_RW_FUNCS(mpamhcr_el2, MPAMHCR_EL2) 435 436 DEFINE_RENAME_SYSREG_RW_FUNCS(pmblimitr_el1, PMBLIMITR_EL1) 437 438 DEFINE_RENAME_SYSREG_WRITE_FUNC(zcr_el3, ZCR_EL3) 439 DEFINE_RENAME_SYSREG_WRITE_FUNC(zcr_el2, ZCR_EL2) 440 441 DEFINE_RENAME_SYSREG_READ_FUNC(erridr_el1, ERRIDR_EL1) 442 DEFINE_RENAME_SYSREG_WRITE_FUNC(errselr_el1, ERRSELR_EL1) 443 444 DEFINE_RENAME_SYSREG_READ_FUNC(erxfr_el1, ERXFR_EL1) 445 DEFINE_RENAME_SYSREG_RW_FUNCS(erxctlr_el1, ERXCTLR_EL1) 446 DEFINE_RENAME_SYSREG_RW_FUNCS(erxstatus_el1, ERXSTATUS_EL1) 447 DEFINE_RENAME_SYSREG_READ_FUNC(erxaddr_el1, ERXADDR_EL1) 448 DEFINE_RENAME_SYSREG_READ_FUNC(erxmisc0_el1, ERXMISC0_EL1) 449 DEFINE_RENAME_SYSREG_READ_FUNC(erxmisc1_el1, ERXMISC1_EL1) 450 451 /* Armv8.3 Pointer Authentication Registers */ 452 DEFINE_RENAME_SYSREG_RW_FUNCS(apgakeylo_el1, APGAKeyLo_EL1) 453 454 #define IS_IN_EL(x) \ 455 (GET_EL(read_CurrentEl()) == MODE_EL##x) 456 457 #define IS_IN_EL1() IS_IN_EL(1) 458 #define IS_IN_EL2() IS_IN_EL(2) 459 #define IS_IN_EL3() IS_IN_EL(3) 460 461 static inline unsigned int get_current_el(void) 462 { 463 return GET_EL(read_CurrentEl()); 464 } 465 466 /* 467 * Check if an EL is implemented from AA64PFR0 register fields. 468 */ 469 static inline uint64_t el_implemented(unsigned int el) 470 { 471 if (el > 3U) { 472 return EL_IMPL_NONE; 473 } else { 474 unsigned int shift = ID_AA64PFR0_EL1_SHIFT * el; 475 476 return (read_id_aa64pfr0_el1() >> shift) & ID_AA64PFR0_ELX_MASK; 477 } 478 } 479 480 #if !ERROR_DEPRECATED 481 #define EL_IMPLEMENTED(_el) el_implemented(_el) 482 #endif 483 484 /* Previously defined accesor functions with incomplete register names */ 485 486 #define read_current_el() read_CurrentEl() 487 488 #define dsb() dsbsy() 489 490 #define read_midr() read_midr_el1() 491 492 #define read_mpidr() read_mpidr_el1() 493 494 #define read_scr() read_scr_el3() 495 #define write_scr(_v) write_scr_el3(_v) 496 497 #define read_hcr() read_hcr_el2() 498 #define write_hcr(_v) write_hcr_el2(_v) 499 500 #define read_cpacr() read_cpacr_el1() 501 #define write_cpacr(_v) write_cpacr_el1(_v) 502 503 #endif /* ARCH_HELPERS_H */ 504