1 /* 2 * Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef ARCH_HELPERS_H 8 #define ARCH_HELPERS_H 9 10 #include <cdefs.h> 11 #include <stdbool.h> 12 #include <stdint.h> 13 #include <string.h> 14 15 #include <arch.h> 16 17 /********************************************************************** 18 * Macros which create inline functions to read or write CPU system 19 * registers 20 *********************************************************************/ 21 22 #define _DEFINE_SYSREG_READ_FUNC(_name, _reg_name) \ 23 static inline u_register_t read_ ## _name(void) \ 24 { \ 25 u_register_t v; \ 26 __asm__ volatile ("mrs %0, " #_reg_name : "=r" (v)); \ 27 return v; \ 28 } 29 30 #define _DEFINE_SYSREG_READ_FUNC_NV(_name, _reg_name) \ 31 static inline u_register_t read_ ## _name(void) \ 32 { \ 33 u_register_t v; \ 34 __asm__ ("mrs %0, " #_reg_name : "=r" (v)); \ 35 return v; \ 36 } 37 38 #define _DEFINE_SYSREG_WRITE_FUNC(_name, _reg_name) \ 39 static inline void write_ ## _name(u_register_t v) \ 40 { \ 41 __asm__ volatile ("msr " #_reg_name ", %0" : : "r" (v)); \ 42 } 43 44 #define SYSREG_WRITE_CONST(reg_name, v) \ 45 __asm__ volatile ("msr " #reg_name ", %0" : : "i" (v)) 46 47 /* Define read function for system register */ 48 #define DEFINE_SYSREG_READ_FUNC(_name) \ 49 _DEFINE_SYSREG_READ_FUNC(_name, _name) 50 51 /* Define read & write function for system register */ 52 #define DEFINE_SYSREG_RW_FUNCS(_name) \ 53 _DEFINE_SYSREG_READ_FUNC(_name, _name) \ 54 _DEFINE_SYSREG_WRITE_FUNC(_name, _name) 55 56 /* Define read & write function for renamed system register */ 57 #define DEFINE_RENAME_SYSREG_RW_FUNCS(_name, _reg_name) \ 58 _DEFINE_SYSREG_READ_FUNC(_name, _reg_name) \ 59 _DEFINE_SYSREG_WRITE_FUNC(_name, _reg_name) 60 61 /* Define read function for renamed system register */ 62 #define DEFINE_RENAME_SYSREG_READ_FUNC(_name, _reg_name) \ 63 _DEFINE_SYSREG_READ_FUNC(_name, _reg_name) 64 65 /* Define write function for renamed system register */ 66 #define DEFINE_RENAME_SYSREG_WRITE_FUNC(_name, _reg_name) \ 67 _DEFINE_SYSREG_WRITE_FUNC(_name, _reg_name) 68 69 /* Define read function for ID register (w/o volatile qualifier) */ 70 #define DEFINE_IDREG_READ_FUNC(_name) \ 71 _DEFINE_SYSREG_READ_FUNC_NV(_name, _name) 72 73 /* Define read function for renamed ID register (w/o volatile qualifier) */ 74 #define DEFINE_RENAME_IDREG_READ_FUNC(_name, _reg_name) \ 75 _DEFINE_SYSREG_READ_FUNC_NV(_name, _reg_name) 76 77 /********************************************************************** 78 * Macros to create inline functions for system instructions 79 *********************************************************************/ 80 81 /* Define function for simple system instruction */ 82 #define DEFINE_SYSOP_FUNC(_op) \ 83 static inline void _op(void) \ 84 { \ 85 __asm__ (#_op); \ 86 } 87 88 /* Define function for system instruction with register parameter */ 89 #define DEFINE_SYSOP_PARAM_FUNC(_op) \ 90 static inline void _op(uint64_t v) \ 91 { \ 92 __asm__ (#_op " %0" : : "r" (v)); \ 93 } 94 95 /* Define function for system instruction with type specifier */ 96 #define DEFINE_SYSOP_TYPE_FUNC(_op, _type) \ 97 static inline void _op ## _type(void) \ 98 { \ 99 __asm__ (#_op " " #_type : : : "memory"); \ 100 } 101 102 /* Define function for system instruction with register parameter */ 103 #define DEFINE_SYSOP_TYPE_PARAM_FUNC(_op, _type) \ 104 static inline void _op ## _type(uint64_t v) \ 105 { \ 106 __asm__ (#_op " " #_type ", %0" : : "r" (v)); \ 107 } 108 109 /******************************************************************************* 110 * TLB maintenance accessor prototypes 111 ******************************************************************************/ 112 113 #if ERRATA_A57_813419 || ERRATA_A76_1286807 114 /* 115 * Define function for TLBI instruction with type specifier that implements 116 * the workaround for errata 813419 of Cortex-A57 or errata 1286807 of 117 * Cortex-A76. 118 */ 119 #define DEFINE_TLBIOP_ERRATA_TYPE_FUNC(_type)\ 120 static inline void tlbi ## _type(void) \ 121 { \ 122 __asm__("tlbi " #_type "\n" \ 123 "dsb ish\n" \ 124 "tlbi " #_type); \ 125 } 126 127 /* 128 * Define function for TLBI instruction with register parameter that implements 129 * the workaround for errata 813419 of Cortex-A57 or errata 1286807 of 130 * Cortex-A76. 131 */ 132 #define DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(_type) \ 133 static inline void tlbi ## _type(uint64_t v) \ 134 { \ 135 __asm__("tlbi " #_type ", %0\n" \ 136 "dsb ish\n" \ 137 "tlbi " #_type ", %0" : : "r" (v)); \ 138 } 139 #endif /* ERRATA_A57_813419 */ 140 141 #if ERRATA_A53_819472 || ERRATA_A53_824069 || ERRATA_A53_827319 142 /* 143 * Define function for DC instruction with register parameter that enables 144 * the workaround for errata 819472, 824069 and 827319 of Cortex-A53. 145 */ 146 #define DEFINE_DCOP_ERRATA_A53_TYPE_PARAM_FUNC(_name, _type) \ 147 static inline void dc ## _name(uint64_t v) \ 148 { \ 149 __asm__("dc " #_type ", %0" : : "r" (v)); \ 150 } 151 #endif /* ERRATA_A53_819472 || ERRATA_A53_824069 || ERRATA_A53_827319 */ 152 153 #if ERRATA_A57_813419 154 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle1) 155 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle1is) 156 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle2) 157 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle2is) 158 DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle3) 159 DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle3is) 160 DEFINE_SYSOP_TYPE_FUNC(tlbi, vmalle1) 161 #elif ERRATA_A76_1286807 162 DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle1) 163 DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle1is) 164 DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle2) 165 DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle2is) 166 DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle3) 167 DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle3is) 168 DEFINE_TLBIOP_ERRATA_TYPE_FUNC(vmalle1) 169 #else 170 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle1) 171 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle1is) 172 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle2) 173 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle2is) 174 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle3) 175 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle3is) 176 DEFINE_SYSOP_TYPE_FUNC(tlbi, vmalle1) 177 #endif 178 179 #if ERRATA_A57_813419 180 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vaae1is) 181 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vaale1is) 182 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vae2is) 183 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vale2is) 184 DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vae3is) 185 DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vale3is) 186 #elif ERRATA_A76_1286807 187 DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vaae1is) 188 DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vaale1is) 189 DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vae2is) 190 DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vale2is) 191 DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vae3is) 192 DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vale3is) 193 #else 194 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vaae1is) 195 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vaale1is) 196 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vae2is) 197 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vale2is) 198 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vae3is) 199 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vale3is) 200 #endif 201 202 /******************************************************************************* 203 * Cache maintenance accessor prototypes 204 ******************************************************************************/ 205 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, isw) 206 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, cisw) 207 #if ERRATA_A53_827319 208 DEFINE_DCOP_ERRATA_A53_TYPE_PARAM_FUNC(csw, cisw) 209 #else 210 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, csw) 211 #endif 212 #if ERRATA_A53_819472 || ERRATA_A53_824069 || ERRATA_A53_827319 213 DEFINE_DCOP_ERRATA_A53_TYPE_PARAM_FUNC(cvac, civac) 214 #else 215 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, cvac) 216 #endif 217 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, ivac) 218 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, civac) 219 #if ERRATA_A53_819472 || ERRATA_A53_824069 || ERRATA_A53_827319 220 DEFINE_DCOP_ERRATA_A53_TYPE_PARAM_FUNC(cvau, civac) 221 #else 222 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, cvau) 223 #endif 224 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, zva) 225 226 /******************************************************************************* 227 * Address translation accessor prototypes 228 ******************************************************************************/ 229 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e1r) 230 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e1w) 231 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e0r) 232 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e0w) 233 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s1e1r) 234 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s1e2r) 235 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s1e3r) 236 237 /******************************************************************************* 238 * Strip Pointer Authentication Code 239 ******************************************************************************/ 240 DEFINE_SYSOP_PARAM_FUNC(xpaci) 241 242 void flush_dcache_range(uintptr_t addr, size_t size); 243 void flush_dcache_to_popa_range(uintptr_t addr, size_t size); 244 void clean_dcache_range(uintptr_t addr, size_t size); 245 void inv_dcache_range(uintptr_t addr, size_t size); 246 bool is_dcache_enabled(void); 247 248 void dcsw_op_louis(u_register_t op_type); 249 void dcsw_op_all(u_register_t op_type); 250 251 void disable_mmu_el1(void); 252 void disable_mmu_el3(void); 253 void disable_mpu_el2(void); 254 void disable_mmu_icache_el1(void); 255 void disable_mmu_icache_el3(void); 256 void disable_mpu_icache_el2(void); 257 258 /******************************************************************************* 259 * Misc. accessor prototypes 260 ******************************************************************************/ 261 262 #define write_daifclr(val) SYSREG_WRITE_CONST(daifclr, val) 263 #define write_daifset(val) SYSREG_WRITE_CONST(daifset, val) 264 265 DEFINE_SYSREG_RW_FUNCS(par_el1) 266 DEFINE_IDREG_READ_FUNC(id_pfr1_el1) 267 DEFINE_IDREG_READ_FUNC(id_aa64isar0_el1) 268 DEFINE_IDREG_READ_FUNC(id_aa64isar1_el1) 269 DEFINE_RENAME_IDREG_READ_FUNC(id_aa64isar2_el1, ID_AA64ISAR2_EL1) 270 DEFINE_IDREG_READ_FUNC(id_aa64pfr0_el1) 271 DEFINE_IDREG_READ_FUNC(id_aa64pfr1_el1) 272 DEFINE_IDREG_READ_FUNC(id_aa64dfr0_el1) 273 DEFINE_IDREG_READ_FUNC(id_afr0_el1) 274 DEFINE_SYSREG_READ_FUNC(CurrentEl) 275 DEFINE_SYSREG_READ_FUNC(ctr_el0) 276 DEFINE_SYSREG_RW_FUNCS(daif) 277 DEFINE_SYSREG_RW_FUNCS(spsr_el1) 278 DEFINE_SYSREG_RW_FUNCS(spsr_el2) 279 DEFINE_SYSREG_RW_FUNCS(spsr_el3) 280 DEFINE_SYSREG_RW_FUNCS(elr_el1) 281 DEFINE_SYSREG_RW_FUNCS(elr_el2) 282 DEFINE_SYSREG_RW_FUNCS(elr_el3) 283 DEFINE_SYSREG_RW_FUNCS(mdccsr_el0) 284 DEFINE_SYSREG_RW_FUNCS(dbgdtrrx_el0) 285 DEFINE_SYSREG_RW_FUNCS(dbgdtrtx_el0) 286 DEFINE_SYSREG_RW_FUNCS(sp_el1) 287 DEFINE_SYSREG_RW_FUNCS(sp_el2) 288 289 DEFINE_SYSOP_FUNC(wfi) 290 DEFINE_SYSOP_FUNC(wfe) 291 DEFINE_SYSOP_FUNC(sev) 292 DEFINE_SYSOP_TYPE_FUNC(dsb, sy) 293 DEFINE_SYSOP_TYPE_FUNC(dmb, sy) 294 DEFINE_SYSOP_TYPE_FUNC(dmb, st) 295 DEFINE_SYSOP_TYPE_FUNC(dmb, ld) 296 DEFINE_SYSOP_TYPE_FUNC(dsb, ish) 297 DEFINE_SYSOP_TYPE_FUNC(dsb, osh) 298 DEFINE_SYSOP_TYPE_FUNC(dsb, nsh) 299 DEFINE_SYSOP_TYPE_FUNC(dsb, ishst) 300 DEFINE_SYSOP_TYPE_FUNC(dsb, oshst) 301 DEFINE_SYSOP_TYPE_FUNC(dmb, oshld) 302 DEFINE_SYSOP_TYPE_FUNC(dmb, oshst) 303 DEFINE_SYSOP_TYPE_FUNC(dmb, osh) 304 DEFINE_SYSOP_TYPE_FUNC(dmb, nshld) 305 DEFINE_SYSOP_TYPE_FUNC(dmb, nshst) 306 DEFINE_SYSOP_TYPE_FUNC(dmb, nsh) 307 DEFINE_SYSOP_TYPE_FUNC(dmb, ishld) 308 DEFINE_SYSOP_TYPE_FUNC(dmb, ishst) 309 DEFINE_SYSOP_TYPE_FUNC(dmb, ish) 310 DEFINE_SYSOP_FUNC(isb) 311 312 static inline void enable_irq(void) 313 { 314 /* 315 * The compiler memory barrier will prevent the compiler from 316 * scheduling non-volatile memory access after the write to the 317 * register. 318 * 319 * This could happen if some initialization code issues non-volatile 320 * accesses to an area used by an interrupt handler, in the assumption 321 * that it is safe as the interrupts are disabled at the time it does 322 * that (according to program order). However, non-volatile accesses 323 * are not necessarily in program order relatively with volatile inline 324 * assembly statements (and volatile accesses). 325 */ 326 COMPILER_BARRIER(); 327 write_daifclr(DAIF_IRQ_BIT); 328 isb(); 329 } 330 331 static inline void enable_fiq(void) 332 { 333 COMPILER_BARRIER(); 334 write_daifclr(DAIF_FIQ_BIT); 335 isb(); 336 } 337 338 static inline void enable_serror(void) 339 { 340 COMPILER_BARRIER(); 341 write_daifclr(DAIF_ABT_BIT); 342 isb(); 343 } 344 345 static inline void enable_debug_exceptions(void) 346 { 347 COMPILER_BARRIER(); 348 write_daifclr(DAIF_DBG_BIT); 349 isb(); 350 } 351 352 static inline void disable_irq(void) 353 { 354 COMPILER_BARRIER(); 355 write_daifset(DAIF_IRQ_BIT); 356 isb(); 357 } 358 359 static inline void disable_fiq(void) 360 { 361 COMPILER_BARRIER(); 362 write_daifset(DAIF_FIQ_BIT); 363 isb(); 364 } 365 366 static inline void disable_serror(void) 367 { 368 COMPILER_BARRIER(); 369 write_daifset(DAIF_ABT_BIT); 370 isb(); 371 } 372 373 static inline void disable_debug_exceptions(void) 374 { 375 COMPILER_BARRIER(); 376 write_daifset(DAIF_DBG_BIT); 377 isb(); 378 } 379 380 void __dead2 smc(uint64_t x0, uint64_t x1, uint64_t x2, uint64_t x3, 381 uint64_t x4, uint64_t x5, uint64_t x6, uint64_t x7); 382 383 /******************************************************************************* 384 * System register accessor prototypes 385 ******************************************************************************/ 386 DEFINE_IDREG_READ_FUNC(midr_el1) 387 DEFINE_SYSREG_READ_FUNC(mpidr_el1) 388 DEFINE_IDREG_READ_FUNC(id_aa64mmfr0_el1) 389 DEFINE_IDREG_READ_FUNC(id_aa64mmfr1_el1) 390 391 DEFINE_SYSREG_RW_FUNCS(scr_el3) 392 DEFINE_SYSREG_RW_FUNCS(hcr_el2) 393 394 DEFINE_SYSREG_RW_FUNCS(vbar_el1) 395 DEFINE_SYSREG_RW_FUNCS(vbar_el2) 396 DEFINE_SYSREG_RW_FUNCS(vbar_el3) 397 398 DEFINE_SYSREG_RW_FUNCS(sctlr_el1) 399 DEFINE_SYSREG_RW_FUNCS(sctlr_el2) 400 DEFINE_SYSREG_RW_FUNCS(sctlr_el3) 401 402 DEFINE_SYSREG_RW_FUNCS(actlr_el1) 403 DEFINE_SYSREG_RW_FUNCS(actlr_el2) 404 DEFINE_SYSREG_RW_FUNCS(actlr_el3) 405 406 DEFINE_SYSREG_RW_FUNCS(esr_el1) 407 DEFINE_SYSREG_RW_FUNCS(esr_el2) 408 DEFINE_SYSREG_RW_FUNCS(esr_el3) 409 410 DEFINE_SYSREG_RW_FUNCS(afsr0_el1) 411 DEFINE_SYSREG_RW_FUNCS(afsr0_el2) 412 DEFINE_SYSREG_RW_FUNCS(afsr0_el3) 413 414 DEFINE_SYSREG_RW_FUNCS(afsr1_el1) 415 DEFINE_SYSREG_RW_FUNCS(afsr1_el2) 416 DEFINE_SYSREG_RW_FUNCS(afsr1_el3) 417 418 DEFINE_SYSREG_RW_FUNCS(far_el1) 419 DEFINE_SYSREG_RW_FUNCS(far_el2) 420 DEFINE_SYSREG_RW_FUNCS(far_el3) 421 422 DEFINE_SYSREG_RW_FUNCS(mair_el1) 423 DEFINE_SYSREG_RW_FUNCS(mair_el2) 424 DEFINE_SYSREG_RW_FUNCS(mair_el3) 425 426 DEFINE_SYSREG_RW_FUNCS(amair_el1) 427 DEFINE_SYSREG_RW_FUNCS(amair_el2) 428 DEFINE_SYSREG_RW_FUNCS(amair_el3) 429 430 DEFINE_SYSREG_READ_FUNC(rvbar_el1) 431 DEFINE_SYSREG_READ_FUNC(rvbar_el2) 432 DEFINE_SYSREG_READ_FUNC(rvbar_el3) 433 434 DEFINE_SYSREG_RW_FUNCS(rmr_el1) 435 DEFINE_SYSREG_RW_FUNCS(rmr_el2) 436 DEFINE_SYSREG_RW_FUNCS(rmr_el3) 437 438 DEFINE_SYSREG_RW_FUNCS(tcr_el1) 439 DEFINE_SYSREG_RW_FUNCS(tcr_el2) 440 DEFINE_SYSREG_RW_FUNCS(tcr_el3) 441 442 DEFINE_SYSREG_RW_FUNCS(ttbr0_el1) 443 DEFINE_SYSREG_RW_FUNCS(ttbr0_el2) 444 DEFINE_SYSREG_RW_FUNCS(ttbr0_el3) 445 446 DEFINE_SYSREG_RW_FUNCS(ttbr1_el1) 447 448 DEFINE_SYSREG_RW_FUNCS(vttbr_el2) 449 450 DEFINE_SYSREG_RW_FUNCS(cptr_el2) 451 DEFINE_SYSREG_RW_FUNCS(cptr_el3) 452 453 DEFINE_SYSREG_RW_FUNCS(cpacr_el1) 454 DEFINE_SYSREG_RW_FUNCS(cntfrq_el0) 455 DEFINE_SYSREG_RW_FUNCS(cnthp_ctl_el2) 456 DEFINE_SYSREG_RW_FUNCS(cnthp_tval_el2) 457 DEFINE_SYSREG_RW_FUNCS(cnthp_cval_el2) 458 DEFINE_SYSREG_RW_FUNCS(cntps_ctl_el1) 459 DEFINE_SYSREG_RW_FUNCS(cntps_tval_el1) 460 DEFINE_SYSREG_RW_FUNCS(cntps_cval_el1) 461 DEFINE_SYSREG_RW_FUNCS(cntp_ctl_el0) 462 DEFINE_SYSREG_RW_FUNCS(cntp_tval_el0) 463 DEFINE_SYSREG_RW_FUNCS(cntp_cval_el0) 464 DEFINE_SYSREG_READ_FUNC(cntpct_el0) 465 DEFINE_SYSREG_RW_FUNCS(cnthctl_el2) 466 467 DEFINE_SYSREG_RW_FUNCS(vtcr_el2) 468 469 #define get_cntp_ctl_enable(x) (((x) >> CNTP_CTL_ENABLE_SHIFT) & \ 470 CNTP_CTL_ENABLE_MASK) 471 #define get_cntp_ctl_imask(x) (((x) >> CNTP_CTL_IMASK_SHIFT) & \ 472 CNTP_CTL_IMASK_MASK) 473 #define get_cntp_ctl_istatus(x) (((x) >> CNTP_CTL_ISTATUS_SHIFT) & \ 474 CNTP_CTL_ISTATUS_MASK) 475 476 #define set_cntp_ctl_enable(x) ((x) |= (U(1) << CNTP_CTL_ENABLE_SHIFT)) 477 #define set_cntp_ctl_imask(x) ((x) |= (U(1) << CNTP_CTL_IMASK_SHIFT)) 478 479 #define clr_cntp_ctl_enable(x) ((x) &= ~(U(1) << CNTP_CTL_ENABLE_SHIFT)) 480 #define clr_cntp_ctl_imask(x) ((x) &= ~(U(1) << CNTP_CTL_IMASK_SHIFT)) 481 482 DEFINE_SYSREG_RW_FUNCS(tpidr_el3) 483 484 DEFINE_SYSREG_RW_FUNCS(cntvoff_el2) 485 486 DEFINE_SYSREG_RW_FUNCS(vpidr_el2) 487 DEFINE_SYSREG_RW_FUNCS(vmpidr_el2) 488 489 DEFINE_SYSREG_READ_FUNC(isr_el1) 490 491 DEFINE_SYSREG_RW_FUNCS(mdcr_el2) 492 DEFINE_SYSREG_RW_FUNCS(mdcr_el3) 493 DEFINE_SYSREG_RW_FUNCS(hstr_el2) 494 DEFINE_SYSREG_RW_FUNCS(pmcr_el0) 495 496 /* GICv3 System Registers */ 497 498 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el1, ICC_SRE_EL1) 499 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el2, ICC_SRE_EL2) 500 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el3, ICC_SRE_EL3) 501 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_pmr_el1, ICC_PMR_EL1) 502 DEFINE_RENAME_SYSREG_READ_FUNC(icc_rpr_el1, ICC_RPR_EL1) 503 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_igrpen1_el3, ICC_IGRPEN1_EL3) 504 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_igrpen1_el1, ICC_IGRPEN1_EL1) 505 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_igrpen0_el1, ICC_IGRPEN0_EL1) 506 DEFINE_RENAME_SYSREG_READ_FUNC(icc_hppir0_el1, ICC_HPPIR0_EL1) 507 DEFINE_RENAME_SYSREG_READ_FUNC(icc_hppir1_el1, ICC_HPPIR1_EL1) 508 DEFINE_RENAME_SYSREG_READ_FUNC(icc_iar0_el1, ICC_IAR0_EL1) 509 DEFINE_RENAME_SYSREG_READ_FUNC(icc_iar1_el1, ICC_IAR1_EL1) 510 DEFINE_RENAME_SYSREG_WRITE_FUNC(icc_eoir0_el1, ICC_EOIR0_EL1) 511 DEFINE_RENAME_SYSREG_WRITE_FUNC(icc_eoir1_el1, ICC_EOIR1_EL1) 512 DEFINE_RENAME_SYSREG_WRITE_FUNC(icc_sgi0r_el1, ICC_SGI0R_EL1) 513 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sgi1r, ICC_SGI1R) 514 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_asgi1r, ICC_ASGI1R) 515 516 DEFINE_RENAME_SYSREG_READ_FUNC(amcfgr_el0, AMCFGR_EL0) 517 DEFINE_RENAME_SYSREG_READ_FUNC(amcgcr_el0, AMCGCR_EL0) 518 DEFINE_RENAME_SYSREG_READ_FUNC(amcg1idr_el0, AMCG1IDR_EL0) 519 DEFINE_RENAME_SYSREG_RW_FUNCS(amcr_el0, AMCR_EL0) 520 DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenclr0_el0, AMCNTENCLR0_EL0) 521 DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenset0_el0, AMCNTENSET0_EL0) 522 DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenclr1_el0, AMCNTENCLR1_EL0) 523 DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenset1_el0, AMCNTENSET1_EL0) 524 525 DEFINE_RENAME_SYSREG_READ_FUNC(mpamidr_el1, MPAMIDR_EL1) 526 DEFINE_RENAME_SYSREG_RW_FUNCS(mpam3_el3, MPAM3_EL3) 527 DEFINE_RENAME_SYSREG_RW_FUNCS(mpam2_el2, MPAM2_EL2) 528 DEFINE_RENAME_SYSREG_RW_FUNCS(mpamhcr_el2, MPAMHCR_EL2) 529 530 DEFINE_RENAME_SYSREG_RW_FUNCS(pmblimitr_el1, PMBLIMITR_EL1) 531 532 DEFINE_RENAME_SYSREG_WRITE_FUNC(zcr_el3, ZCR_EL3) 533 DEFINE_RENAME_SYSREG_WRITE_FUNC(zcr_el2, ZCR_EL2) 534 535 DEFINE_RENAME_IDREG_READ_FUNC(id_aa64smfr0_el1, ID_AA64SMFR0_EL1) 536 DEFINE_RENAME_SYSREG_RW_FUNCS(smcr_el3, SMCR_EL3) 537 538 DEFINE_RENAME_SYSREG_READ_FUNC(erridr_el1, ERRIDR_EL1) 539 DEFINE_RENAME_SYSREG_WRITE_FUNC(errselr_el1, ERRSELR_EL1) 540 541 DEFINE_RENAME_SYSREG_READ_FUNC(erxfr_el1, ERXFR_EL1) 542 DEFINE_RENAME_SYSREG_RW_FUNCS(erxctlr_el1, ERXCTLR_EL1) 543 DEFINE_RENAME_SYSREG_RW_FUNCS(erxstatus_el1, ERXSTATUS_EL1) 544 DEFINE_RENAME_SYSREG_READ_FUNC(erxaddr_el1, ERXADDR_EL1) 545 DEFINE_RENAME_SYSREG_READ_FUNC(erxmisc0_el1, ERXMISC0_EL1) 546 DEFINE_RENAME_SYSREG_READ_FUNC(erxmisc1_el1, ERXMISC1_EL1) 547 548 /* Armv8.2 Registers */ 549 DEFINE_RENAME_IDREG_READ_FUNC(id_aa64mmfr2_el1, ID_AA64MMFR2_EL1) 550 551 /* Armv8.3 Pointer Authentication Registers */ 552 DEFINE_RENAME_SYSREG_RW_FUNCS(apiakeyhi_el1, APIAKeyHi_EL1) 553 DEFINE_RENAME_SYSREG_RW_FUNCS(apiakeylo_el1, APIAKeyLo_EL1) 554 555 /* Armv8.4 Data Independent Timing Register */ 556 DEFINE_RENAME_SYSREG_RW_FUNCS(dit, DIT) 557 558 /* Armv8.4 FEAT_TRF Register */ 559 DEFINE_RENAME_SYSREG_RW_FUNCS(trfcr_el2, TRFCR_EL2) 560 561 /* Armv8.5 MTE Registers */ 562 DEFINE_RENAME_SYSREG_RW_FUNCS(tfsre0_el1, TFSRE0_EL1) 563 DEFINE_RENAME_SYSREG_RW_FUNCS(tfsr_el1, TFSR_EL1) 564 DEFINE_RENAME_SYSREG_RW_FUNCS(rgsr_el1, RGSR_EL1) 565 DEFINE_RENAME_SYSREG_RW_FUNCS(gcr_el1, GCR_EL1) 566 567 /* Armv8.5 FEAT_RNG Registers */ 568 DEFINE_RENAME_SYSREG_READ_FUNC(rndr, RNDR) 569 DEFINE_RENAME_SYSREG_READ_FUNC(rndrrs, RNDRRS) 570 571 /* Armv8.6 FEAT_FGT Registers */ 572 DEFINE_RENAME_SYSREG_RW_FUNCS(hdfgrtr_el2, HDFGRTR_EL2) 573 DEFINE_RENAME_SYSREG_RW_FUNCS(hafgrtr_el2, HAFGRTR_EL2) 574 DEFINE_RENAME_SYSREG_RW_FUNCS(hdfgwtr_el2, HDFGWTR_EL2) 575 DEFINE_RENAME_SYSREG_RW_FUNCS(hfgitr_el2, HFGITR_EL2) 576 DEFINE_RENAME_SYSREG_RW_FUNCS(hfgrtr_el2, HFGRTR_EL2) 577 DEFINE_RENAME_SYSREG_RW_FUNCS(hfgwtr_el2, HFGWTR_EL2) 578 579 /* FEAT_HCX Register */ 580 DEFINE_RENAME_SYSREG_RW_FUNCS(hcrx_el2, HCRX_EL2) 581 582 /* DynamIQ Shared Unit power management */ 583 DEFINE_RENAME_SYSREG_RW_FUNCS(clusterpwrdn_el1, CLUSTERPWRDN_EL1) 584 585 /* CPU Power/Performance Management registers */ 586 DEFINE_RENAME_SYSREG_RW_FUNCS(cpuppmcr_el3, CPUPPMCR_EL3) 587 DEFINE_RENAME_SYSREG_RW_FUNCS(cpumpmmcr_el3, CPUMPMMCR_EL3) 588 589 /* Armv9.2 RME Registers */ 590 DEFINE_RENAME_SYSREG_RW_FUNCS(gptbr_el3, GPTBR_EL3) 591 DEFINE_RENAME_SYSREG_RW_FUNCS(gpccr_el3, GPCCR_EL3) 592 593 #define IS_IN_EL(x) \ 594 (GET_EL(read_CurrentEl()) == MODE_EL##x) 595 596 #define IS_IN_EL1() IS_IN_EL(1) 597 #define IS_IN_EL2() IS_IN_EL(2) 598 #define IS_IN_EL3() IS_IN_EL(3) 599 600 static inline unsigned int get_current_el(void) 601 { 602 return GET_EL(read_CurrentEl()); 603 } 604 605 static inline unsigned int get_current_el_maybe_constant(void) 606 { 607 #if defined(IMAGE_AT_EL1) 608 return 1; 609 #elif defined(IMAGE_AT_EL2) 610 return 2; /* no use-case in TF-A */ 611 #elif defined(IMAGE_AT_EL3) 612 return 3; 613 #else 614 /* 615 * If we do not know which exception level this is being built for 616 * (e.g. built for library), fall back to run-time detection. 617 */ 618 return get_current_el(); 619 #endif 620 } 621 622 /* 623 * Check if an EL is implemented from AA64PFR0 register fields. 624 */ 625 static inline uint64_t el_implemented(unsigned int el) 626 { 627 if (el > 3U) { 628 return EL_IMPL_NONE; 629 } else { 630 unsigned int shift = ID_AA64PFR0_EL1_SHIFT * el; 631 632 return (read_id_aa64pfr0_el1() >> shift) & ID_AA64PFR0_ELX_MASK; 633 } 634 } 635 636 /* 637 * TLBIPAALLOS instruction 638 * (TLB Inivalidate GPT Information by PA, 639 * All Entries, Outer Shareable) 640 */ 641 static inline void tlbipaallos(void) 642 { 643 __asm__("SYS #6,c8,c1,#4"); 644 } 645 646 /* 647 * Invalidate TLBs of GPT entries by Physical address, last level. 648 * 649 * @pa: the starting address for the range 650 * of invalidation 651 * @size: size of the range of invalidation 652 */ 653 void gpt_tlbi_by_pa_ll(uint64_t pa, size_t size); 654 655 656 /* Previously defined accessor functions with incomplete register names */ 657 658 #define read_current_el() read_CurrentEl() 659 660 #define dsb() dsbsy() 661 662 #define read_midr() read_midr_el1() 663 664 #define read_mpidr() read_mpidr_el1() 665 666 #define read_scr() read_scr_el3() 667 #define write_scr(_v) write_scr_el3(_v) 668 669 #define read_hcr() read_hcr_el2() 670 #define write_hcr(_v) write_hcr_el2(_v) 671 672 #define read_cpacr() read_cpacr_el1() 673 #define write_cpacr(_v) write_cpacr_el1(_v) 674 675 #define read_clusterpwrdn() read_clusterpwrdn_el1() 676 #define write_clusterpwrdn(_v) write_clusterpwrdn_el1(_v) 677 678 #if ERRATA_SPECULATIVE_AT 679 /* 680 * Assuming SCTLR.M bit is already enabled 681 * 1. Enable page table walk by clearing TCR_EL1.EPDx bits 682 * 2. Execute AT instruction for lower EL1/0 683 * 3. Disable page table walk by setting TCR_EL1.EPDx bits 684 */ 685 #define AT(_at_inst, _va) \ 686 { \ 687 assert((read_sctlr_el1() & SCTLR_M_BIT) != 0ULL); \ 688 write_tcr_el1(read_tcr_el1() & ~(TCR_EPD0_BIT | TCR_EPD1_BIT)); \ 689 isb(); \ 690 _at_inst(_va); \ 691 write_tcr_el1(read_tcr_el1() | (TCR_EPD0_BIT | TCR_EPD1_BIT)); \ 692 isb(); \ 693 } 694 #else 695 #define AT(_at_inst, _va) _at_inst(_va) 696 #endif 697 698 #endif /* ARCH_HELPERS_H */ 699