1 /* 2 * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef ARCH_HELPERS_H 8 #define ARCH_HELPERS_H 9 10 #include <cdefs.h> 11 #include <stdbool.h> 12 #include <stdint.h> 13 #include <string.h> 14 15 #include <arch.h> 16 17 /********************************************************************** 18 * Macros which create inline functions to read or write CPU system 19 * registers 20 *********************************************************************/ 21 22 #define _DEFINE_SYSREG_READ_FUNC(_name, _reg_name) \ 23 static inline u_register_t read_ ## _name(void) \ 24 { \ 25 u_register_t v; \ 26 __asm__ volatile ("mrs %0, " #_reg_name : "=r" (v)); \ 27 return v; \ 28 } 29 30 #define _DEFINE_SYSREG_WRITE_FUNC(_name, _reg_name) \ 31 static inline void write_ ## _name(u_register_t v) \ 32 { \ 33 __asm__ volatile ("msr " #_reg_name ", %0" : : "r" (v)); \ 34 } 35 36 #define SYSREG_WRITE_CONST(reg_name, v) \ 37 __asm__ volatile ("msr " #reg_name ", %0" : : "i" (v)) 38 39 /* Define read function for system register */ 40 #define DEFINE_SYSREG_READ_FUNC(_name) \ 41 _DEFINE_SYSREG_READ_FUNC(_name, _name) 42 43 /* Define read & write function for system register */ 44 #define DEFINE_SYSREG_RW_FUNCS(_name) \ 45 _DEFINE_SYSREG_READ_FUNC(_name, _name) \ 46 _DEFINE_SYSREG_WRITE_FUNC(_name, _name) 47 48 /* Define read & write function for renamed system register */ 49 #define DEFINE_RENAME_SYSREG_RW_FUNCS(_name, _reg_name) \ 50 _DEFINE_SYSREG_READ_FUNC(_name, _reg_name) \ 51 _DEFINE_SYSREG_WRITE_FUNC(_name, _reg_name) 52 53 /* Define read function for renamed system register */ 54 #define DEFINE_RENAME_SYSREG_READ_FUNC(_name, _reg_name) \ 55 _DEFINE_SYSREG_READ_FUNC(_name, _reg_name) 56 57 /* Define write function for renamed system register */ 58 #define DEFINE_RENAME_SYSREG_WRITE_FUNC(_name, _reg_name) \ 59 _DEFINE_SYSREG_WRITE_FUNC(_name, _reg_name) 60 61 /********************************************************************** 62 * Macros to create inline functions for system instructions 63 *********************************************************************/ 64 65 /* Define function for simple system instruction */ 66 #define DEFINE_SYSOP_FUNC(_op) \ 67 static inline void _op(void) \ 68 { \ 69 __asm__ (#_op); \ 70 } 71 72 /* Define function for system instruction with type specifier */ 73 #define DEFINE_SYSOP_TYPE_FUNC(_op, _type) \ 74 static inline void _op ## _type(void) \ 75 { \ 76 __asm__ (#_op " " #_type); \ 77 } 78 79 /* Define function for system instruction with register parameter */ 80 #define DEFINE_SYSOP_TYPE_PARAM_FUNC(_op, _type) \ 81 static inline void _op ## _type(uint64_t v) \ 82 { \ 83 __asm__ (#_op " " #_type ", %0" : : "r" (v)); \ 84 } 85 86 /******************************************************************************* 87 * TLB maintenance accessor prototypes 88 ******************************************************************************/ 89 90 #if ERRATA_A57_813419 || ERRATA_A76_1286807 91 /* 92 * Define function for TLBI instruction with type specifier that implements 93 * the workaround for errata 813419 of Cortex-A57 or errata 1286807 of 94 * Cortex-A76. 95 */ 96 #define DEFINE_TLBIOP_ERRATA_TYPE_FUNC(_type)\ 97 static inline void tlbi ## _type(void) \ 98 { \ 99 __asm__("tlbi " #_type "\n" \ 100 "dsb ish\n" \ 101 "tlbi " #_type); \ 102 } 103 104 /* 105 * Define function for TLBI instruction with register parameter that implements 106 * the workaround for errata 813419 of Cortex-A57 or errata 1286807 of 107 * Cortex-A76. 108 */ 109 #define DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(_type) \ 110 static inline void tlbi ## _type(uint64_t v) \ 111 { \ 112 __asm__("tlbi " #_type ", %0\n" \ 113 "dsb ish\n" \ 114 "tlbi " #_type ", %0" : : "r" (v)); \ 115 } 116 #endif /* ERRATA_A57_813419 */ 117 118 #if ERRATA_A53_819472 || ERRATA_A53_824069 || ERRATA_A53_827319 119 /* 120 * Define function for DC instruction with register parameter that enables 121 * the workaround for errata 819472, 824069 and 827319 of Cortex-A53. 122 */ 123 #define DEFINE_DCOP_ERRATA_A53_TYPE_PARAM_FUNC(_name, _type) \ 124 static inline void dc ## _name(uint64_t v) \ 125 { \ 126 __asm__("dc " #_type ", %0" : : "r" (v)); \ 127 } 128 #endif /* ERRATA_A53_819472 || ERRATA_A53_824069 || ERRATA_A53_827319 */ 129 130 #if ERRATA_A57_813419 131 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle1) 132 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle1is) 133 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle2) 134 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle2is) 135 DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle3) 136 DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle3is) 137 DEFINE_SYSOP_TYPE_FUNC(tlbi, vmalle1) 138 #elif ERRATA_A76_1286807 139 DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle1) 140 DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle1is) 141 DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle2) 142 DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle2is) 143 DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle3) 144 DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle3is) 145 DEFINE_TLBIOP_ERRATA_TYPE_FUNC(vmalle1) 146 #else 147 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle1) 148 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle1is) 149 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle2) 150 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle2is) 151 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle3) 152 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle3is) 153 DEFINE_SYSOP_TYPE_FUNC(tlbi, vmalle1) 154 #endif 155 156 #if ERRATA_A57_813419 157 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vaae1is) 158 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vaale1is) 159 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vae2is) 160 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vale2is) 161 DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vae3is) 162 DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vale3is) 163 #elif ERRATA_A76_1286807 164 DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vaae1is) 165 DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vaale1is) 166 DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vae2is) 167 DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vale2is) 168 DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vae3is) 169 DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vale3is) 170 #else 171 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vaae1is) 172 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vaale1is) 173 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vae2is) 174 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vale2is) 175 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vae3is) 176 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vale3is) 177 #endif 178 179 /******************************************************************************* 180 * Cache maintenance accessor prototypes 181 ******************************************************************************/ 182 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, isw) 183 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, cisw) 184 #if ERRATA_A53_827319 185 DEFINE_DCOP_ERRATA_A53_TYPE_PARAM_FUNC(csw, cisw) 186 #else 187 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, csw) 188 #endif 189 #if ERRATA_A53_819472 || ERRATA_A53_824069 || ERRATA_A53_827319 190 DEFINE_DCOP_ERRATA_A53_TYPE_PARAM_FUNC(cvac, civac) 191 #else 192 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, cvac) 193 #endif 194 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, ivac) 195 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, civac) 196 #if ERRATA_A53_819472 || ERRATA_A53_824069 || ERRATA_A53_827319 197 DEFINE_DCOP_ERRATA_A53_TYPE_PARAM_FUNC(cvau, civac) 198 #else 199 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, cvau) 200 #endif 201 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, zva) 202 203 /******************************************************************************* 204 * Address translation accessor prototypes 205 ******************************************************************************/ 206 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e1r) 207 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e1w) 208 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e0r) 209 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e0w) 210 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s1e1r) 211 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s1e2r) 212 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s1e3r) 213 214 void flush_dcache_range(uintptr_t addr, size_t size); 215 void clean_dcache_range(uintptr_t addr, size_t size); 216 void inv_dcache_range(uintptr_t addr, size_t size); 217 218 void dcsw_op_louis(u_register_t op_type); 219 void dcsw_op_all(u_register_t op_type); 220 221 void disable_mmu_el1(void); 222 void disable_mmu_el3(void); 223 void disable_mmu_icache_el1(void); 224 void disable_mmu_icache_el3(void); 225 226 /******************************************************************************* 227 * Misc. accessor prototypes 228 ******************************************************************************/ 229 230 #define write_daifclr(val) SYSREG_WRITE_CONST(daifclr, val) 231 #define write_daifset(val) SYSREG_WRITE_CONST(daifset, val) 232 233 DEFINE_SYSREG_RW_FUNCS(par_el1) 234 DEFINE_SYSREG_READ_FUNC(id_pfr1_el1) 235 DEFINE_SYSREG_READ_FUNC(id_aa64isar1_el1) 236 DEFINE_SYSREG_READ_FUNC(id_aa64pfr0_el1) 237 DEFINE_SYSREG_READ_FUNC(id_aa64pfr1_el1) 238 DEFINE_SYSREG_READ_FUNC(id_aa64dfr0_el1) 239 DEFINE_SYSREG_READ_FUNC(id_afr0_el1) 240 DEFINE_SYSREG_READ_FUNC(CurrentEl) 241 DEFINE_SYSREG_READ_FUNC(ctr_el0) 242 DEFINE_SYSREG_RW_FUNCS(daif) 243 DEFINE_SYSREG_RW_FUNCS(spsr_el1) 244 DEFINE_SYSREG_RW_FUNCS(spsr_el2) 245 DEFINE_SYSREG_RW_FUNCS(spsr_el3) 246 DEFINE_SYSREG_RW_FUNCS(elr_el1) 247 DEFINE_SYSREG_RW_FUNCS(elr_el2) 248 DEFINE_SYSREG_RW_FUNCS(elr_el3) 249 250 DEFINE_SYSOP_FUNC(wfi) 251 DEFINE_SYSOP_FUNC(wfe) 252 DEFINE_SYSOP_FUNC(sev) 253 DEFINE_SYSOP_TYPE_FUNC(dsb, sy) 254 DEFINE_SYSOP_TYPE_FUNC(dmb, sy) 255 DEFINE_SYSOP_TYPE_FUNC(dmb, st) 256 DEFINE_SYSOP_TYPE_FUNC(dmb, ld) 257 DEFINE_SYSOP_TYPE_FUNC(dsb, ish) 258 DEFINE_SYSOP_TYPE_FUNC(dsb, nsh) 259 DEFINE_SYSOP_TYPE_FUNC(dsb, ishst) 260 DEFINE_SYSOP_TYPE_FUNC(dmb, oshld) 261 DEFINE_SYSOP_TYPE_FUNC(dmb, oshst) 262 DEFINE_SYSOP_TYPE_FUNC(dmb, osh) 263 DEFINE_SYSOP_TYPE_FUNC(dmb, nshld) 264 DEFINE_SYSOP_TYPE_FUNC(dmb, nshst) 265 DEFINE_SYSOP_TYPE_FUNC(dmb, nsh) 266 DEFINE_SYSOP_TYPE_FUNC(dmb, ishld) 267 DEFINE_SYSOP_TYPE_FUNC(dmb, ishst) 268 DEFINE_SYSOP_TYPE_FUNC(dmb, ish) 269 DEFINE_SYSOP_FUNC(isb) 270 271 static inline void enable_irq(void) 272 { 273 /* 274 * The compiler memory barrier will prevent the compiler from 275 * scheduling non-volatile memory access after the write to the 276 * register. 277 * 278 * This could happen if some initialization code issues non-volatile 279 * accesses to an area used by an interrupt handler, in the assumption 280 * that it is safe as the interrupts are disabled at the time it does 281 * that (according to program order). However, non-volatile accesses 282 * are not necessarily in program order relatively with volatile inline 283 * assembly statements (and volatile accesses). 284 */ 285 COMPILER_BARRIER(); 286 write_daifclr(DAIF_IRQ_BIT); 287 isb(); 288 } 289 290 static inline void enable_fiq(void) 291 { 292 COMPILER_BARRIER(); 293 write_daifclr(DAIF_FIQ_BIT); 294 isb(); 295 } 296 297 static inline void enable_serror(void) 298 { 299 COMPILER_BARRIER(); 300 write_daifclr(DAIF_ABT_BIT); 301 isb(); 302 } 303 304 static inline void enable_debug_exceptions(void) 305 { 306 COMPILER_BARRIER(); 307 write_daifclr(DAIF_DBG_BIT); 308 isb(); 309 } 310 311 static inline void disable_irq(void) 312 { 313 COMPILER_BARRIER(); 314 write_daifset(DAIF_IRQ_BIT); 315 isb(); 316 } 317 318 static inline void disable_fiq(void) 319 { 320 COMPILER_BARRIER(); 321 write_daifset(DAIF_FIQ_BIT); 322 isb(); 323 } 324 325 static inline void disable_serror(void) 326 { 327 COMPILER_BARRIER(); 328 write_daifset(DAIF_ABT_BIT); 329 isb(); 330 } 331 332 static inline void disable_debug_exceptions(void) 333 { 334 COMPILER_BARRIER(); 335 write_daifset(DAIF_DBG_BIT); 336 isb(); 337 } 338 339 void __dead2 smc(uint64_t x0, uint64_t x1, uint64_t x2, uint64_t x3, 340 uint64_t x4, uint64_t x5, uint64_t x6, uint64_t x7); 341 342 /******************************************************************************* 343 * System register accessor prototypes 344 ******************************************************************************/ 345 DEFINE_SYSREG_READ_FUNC(midr_el1) 346 DEFINE_SYSREG_READ_FUNC(mpidr_el1) 347 DEFINE_SYSREG_READ_FUNC(id_aa64mmfr0_el1) 348 349 DEFINE_SYSREG_RW_FUNCS(scr_el3) 350 DEFINE_SYSREG_RW_FUNCS(hcr_el2) 351 352 DEFINE_SYSREG_RW_FUNCS(vbar_el1) 353 DEFINE_SYSREG_RW_FUNCS(vbar_el2) 354 DEFINE_SYSREG_RW_FUNCS(vbar_el3) 355 356 DEFINE_SYSREG_RW_FUNCS(sctlr_el1) 357 DEFINE_SYSREG_RW_FUNCS(sctlr_el2) 358 DEFINE_SYSREG_RW_FUNCS(sctlr_el3) 359 360 DEFINE_SYSREG_RW_FUNCS(actlr_el1) 361 DEFINE_SYSREG_RW_FUNCS(actlr_el2) 362 DEFINE_SYSREG_RW_FUNCS(actlr_el3) 363 364 DEFINE_SYSREG_RW_FUNCS(esr_el1) 365 DEFINE_SYSREG_RW_FUNCS(esr_el2) 366 DEFINE_SYSREG_RW_FUNCS(esr_el3) 367 368 DEFINE_SYSREG_RW_FUNCS(afsr0_el1) 369 DEFINE_SYSREG_RW_FUNCS(afsr0_el2) 370 DEFINE_SYSREG_RW_FUNCS(afsr0_el3) 371 372 DEFINE_SYSREG_RW_FUNCS(afsr1_el1) 373 DEFINE_SYSREG_RW_FUNCS(afsr1_el2) 374 DEFINE_SYSREG_RW_FUNCS(afsr1_el3) 375 376 DEFINE_SYSREG_RW_FUNCS(far_el1) 377 DEFINE_SYSREG_RW_FUNCS(far_el2) 378 DEFINE_SYSREG_RW_FUNCS(far_el3) 379 380 DEFINE_SYSREG_RW_FUNCS(mair_el1) 381 DEFINE_SYSREG_RW_FUNCS(mair_el2) 382 DEFINE_SYSREG_RW_FUNCS(mair_el3) 383 384 DEFINE_SYSREG_RW_FUNCS(amair_el1) 385 DEFINE_SYSREG_RW_FUNCS(amair_el2) 386 DEFINE_SYSREG_RW_FUNCS(amair_el3) 387 388 DEFINE_SYSREG_READ_FUNC(rvbar_el1) 389 DEFINE_SYSREG_READ_FUNC(rvbar_el2) 390 DEFINE_SYSREG_READ_FUNC(rvbar_el3) 391 392 DEFINE_SYSREG_RW_FUNCS(rmr_el1) 393 DEFINE_SYSREG_RW_FUNCS(rmr_el2) 394 DEFINE_SYSREG_RW_FUNCS(rmr_el3) 395 396 DEFINE_SYSREG_RW_FUNCS(tcr_el1) 397 DEFINE_SYSREG_RW_FUNCS(tcr_el2) 398 DEFINE_SYSREG_RW_FUNCS(tcr_el3) 399 400 DEFINE_SYSREG_RW_FUNCS(ttbr0_el1) 401 DEFINE_SYSREG_RW_FUNCS(ttbr0_el2) 402 DEFINE_SYSREG_RW_FUNCS(ttbr0_el3) 403 404 DEFINE_SYSREG_RW_FUNCS(ttbr1_el1) 405 406 DEFINE_SYSREG_RW_FUNCS(vttbr_el2) 407 408 DEFINE_SYSREG_RW_FUNCS(cptr_el2) 409 DEFINE_SYSREG_RW_FUNCS(cptr_el3) 410 411 DEFINE_SYSREG_RW_FUNCS(cpacr_el1) 412 DEFINE_SYSREG_RW_FUNCS(cntfrq_el0) 413 DEFINE_SYSREG_RW_FUNCS(cnthp_ctl_el2) 414 DEFINE_SYSREG_RW_FUNCS(cnthp_tval_el2) 415 DEFINE_SYSREG_RW_FUNCS(cnthp_cval_el2) 416 DEFINE_SYSREG_RW_FUNCS(cntps_ctl_el1) 417 DEFINE_SYSREG_RW_FUNCS(cntps_tval_el1) 418 DEFINE_SYSREG_RW_FUNCS(cntps_cval_el1) 419 DEFINE_SYSREG_RW_FUNCS(cntp_ctl_el0) 420 DEFINE_SYSREG_RW_FUNCS(cntp_tval_el0) 421 DEFINE_SYSREG_RW_FUNCS(cntp_cval_el0) 422 DEFINE_SYSREG_READ_FUNC(cntpct_el0) 423 DEFINE_SYSREG_RW_FUNCS(cnthctl_el2) 424 425 #define get_cntp_ctl_enable(x) (((x) >> CNTP_CTL_ENABLE_SHIFT) & \ 426 CNTP_CTL_ENABLE_MASK) 427 #define get_cntp_ctl_imask(x) (((x) >> CNTP_CTL_IMASK_SHIFT) & \ 428 CNTP_CTL_IMASK_MASK) 429 #define get_cntp_ctl_istatus(x) (((x) >> CNTP_CTL_ISTATUS_SHIFT) & \ 430 CNTP_CTL_ISTATUS_MASK) 431 432 #define set_cntp_ctl_enable(x) ((x) |= (U(1) << CNTP_CTL_ENABLE_SHIFT)) 433 #define set_cntp_ctl_imask(x) ((x) |= (U(1) << CNTP_CTL_IMASK_SHIFT)) 434 435 #define clr_cntp_ctl_enable(x) ((x) &= ~(U(1) << CNTP_CTL_ENABLE_SHIFT)) 436 #define clr_cntp_ctl_imask(x) ((x) &= ~(U(1) << CNTP_CTL_IMASK_SHIFT)) 437 438 DEFINE_SYSREG_RW_FUNCS(tpidr_el3) 439 440 DEFINE_SYSREG_RW_FUNCS(cntvoff_el2) 441 442 DEFINE_SYSREG_RW_FUNCS(vpidr_el2) 443 DEFINE_SYSREG_RW_FUNCS(vmpidr_el2) 444 445 DEFINE_SYSREG_READ_FUNC(isr_el1) 446 447 DEFINE_SYSREG_RW_FUNCS(mdcr_el2) 448 DEFINE_SYSREG_RW_FUNCS(mdcr_el3) 449 DEFINE_SYSREG_RW_FUNCS(hstr_el2) 450 DEFINE_SYSREG_RW_FUNCS(pmcr_el0) 451 452 /* GICv3 System Registers */ 453 454 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el1, ICC_SRE_EL1) 455 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el2, ICC_SRE_EL2) 456 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el3, ICC_SRE_EL3) 457 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_pmr_el1, ICC_PMR_EL1) 458 DEFINE_RENAME_SYSREG_READ_FUNC(icc_rpr_el1, ICC_RPR_EL1) 459 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_igrpen1_el3, ICC_IGRPEN1_EL3) 460 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_igrpen1_el1, ICC_IGRPEN1_EL1) 461 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_igrpen0_el1, ICC_IGRPEN0_EL1) 462 DEFINE_RENAME_SYSREG_READ_FUNC(icc_hppir0_el1, ICC_HPPIR0_EL1) 463 DEFINE_RENAME_SYSREG_READ_FUNC(icc_hppir1_el1, ICC_HPPIR1_EL1) 464 DEFINE_RENAME_SYSREG_READ_FUNC(icc_iar0_el1, ICC_IAR0_EL1) 465 DEFINE_RENAME_SYSREG_READ_FUNC(icc_iar1_el1, ICC_IAR1_EL1) 466 DEFINE_RENAME_SYSREG_WRITE_FUNC(icc_eoir0_el1, ICC_EOIR0_EL1) 467 DEFINE_RENAME_SYSREG_WRITE_FUNC(icc_eoir1_el1, ICC_EOIR1_EL1) 468 DEFINE_RENAME_SYSREG_WRITE_FUNC(icc_sgi0r_el1, ICC_SGI0R_EL1) 469 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sgi1r, ICC_SGI1R) 470 471 DEFINE_RENAME_SYSREG_RW_FUNCS(amcgcr_el0, AMCGCR_EL0) 472 DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenclr0_el0, AMCNTENCLR0_EL0) 473 DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenset0_el0, AMCNTENSET0_EL0) 474 DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenclr1_el0, AMCNTENCLR1_EL0) 475 DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenset1_el0, AMCNTENSET1_EL0) 476 477 DEFINE_RENAME_SYSREG_READ_FUNC(mpamidr_el1, MPAMIDR_EL1) 478 DEFINE_RENAME_SYSREG_RW_FUNCS(mpam3_el3, MPAM3_EL3) 479 DEFINE_RENAME_SYSREG_RW_FUNCS(mpam2_el2, MPAM2_EL2) 480 DEFINE_RENAME_SYSREG_RW_FUNCS(mpamhcr_el2, MPAMHCR_EL2) 481 482 DEFINE_RENAME_SYSREG_RW_FUNCS(pmblimitr_el1, PMBLIMITR_EL1) 483 484 DEFINE_RENAME_SYSREG_WRITE_FUNC(zcr_el3, ZCR_EL3) 485 DEFINE_RENAME_SYSREG_WRITE_FUNC(zcr_el2, ZCR_EL2) 486 487 DEFINE_RENAME_SYSREG_READ_FUNC(erridr_el1, ERRIDR_EL1) 488 DEFINE_RENAME_SYSREG_WRITE_FUNC(errselr_el1, ERRSELR_EL1) 489 490 DEFINE_RENAME_SYSREG_READ_FUNC(erxfr_el1, ERXFR_EL1) 491 DEFINE_RENAME_SYSREG_RW_FUNCS(erxctlr_el1, ERXCTLR_EL1) 492 DEFINE_RENAME_SYSREG_RW_FUNCS(erxstatus_el1, ERXSTATUS_EL1) 493 DEFINE_RENAME_SYSREG_READ_FUNC(erxaddr_el1, ERXADDR_EL1) 494 DEFINE_RENAME_SYSREG_READ_FUNC(erxmisc0_el1, ERXMISC0_EL1) 495 DEFINE_RENAME_SYSREG_READ_FUNC(erxmisc1_el1, ERXMISC1_EL1) 496 497 /* Armv8.2 Registers */ 498 DEFINE_RENAME_SYSREG_READ_FUNC(id_aa64mmfr2_el1, ID_AA64MMFR2_EL1) 499 500 /* Armv8.3 Pointer Authentication Registers */ 501 DEFINE_RENAME_SYSREG_RW_FUNCS(apiakeyhi_el1, APIAKeyHi_EL1) 502 DEFINE_RENAME_SYSREG_RW_FUNCS(apiakeylo_el1, APIAKeyLo_EL1) 503 504 /* Armv8.5 MTE Registers */ 505 DEFINE_RENAME_SYSREG_RW_FUNCS(tfsre0_el1, TFSRE0_EL1) 506 DEFINE_RENAME_SYSREG_RW_FUNCS(tfsr_el1, TFSR_EL1) 507 DEFINE_RENAME_SYSREG_RW_FUNCS(rgsr_el1, RGSR_EL1) 508 DEFINE_RENAME_SYSREG_RW_FUNCS(gcr_el1, GCR_EL1) 509 510 #define IS_IN_EL(x) \ 511 (GET_EL(read_CurrentEl()) == MODE_EL##x) 512 513 #define IS_IN_EL1() IS_IN_EL(1) 514 #define IS_IN_EL2() IS_IN_EL(2) 515 #define IS_IN_EL3() IS_IN_EL(3) 516 517 static inline unsigned int get_current_el(void) 518 { 519 return GET_EL(read_CurrentEl()); 520 } 521 522 /* 523 * Check if an EL is implemented from AA64PFR0 register fields. 524 */ 525 static inline uint64_t el_implemented(unsigned int el) 526 { 527 if (el > 3U) { 528 return EL_IMPL_NONE; 529 } else { 530 unsigned int shift = ID_AA64PFR0_EL1_SHIFT * el; 531 532 return (read_id_aa64pfr0_el1() >> shift) & ID_AA64PFR0_ELX_MASK; 533 } 534 } 535 536 /* Previously defined accesor functions with incomplete register names */ 537 538 #define read_current_el() read_CurrentEl() 539 540 #define dsb() dsbsy() 541 542 #define read_midr() read_midr_el1() 543 544 #define read_mpidr() read_mpidr_el1() 545 546 #define read_scr() read_scr_el3() 547 #define write_scr(_v) write_scr_el3(_v) 548 549 #define read_hcr() read_hcr_el2() 550 #define write_hcr(_v) write_hcr_el2(_v) 551 552 #define read_cpacr() read_cpacr_el1() 553 #define write_cpacr(_v) write_cpacr_el1(_v) 554 555 #endif /* ARCH_HELPERS_H */ 556