1 /* 2 * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef ARCH_HELPERS_H 8 #define ARCH_HELPERS_H 9 10 #include <cdefs.h> 11 #include <stdbool.h> 12 #include <stdint.h> 13 #include <string.h> 14 15 #include <arch.h> 16 17 /********************************************************************** 18 * Macros which create inline functions to read or write CPU system 19 * registers 20 *********************************************************************/ 21 22 #define _DEFINE_SYSREG_READ_FUNC(_name, _reg_name) \ 23 static inline u_register_t read_ ## _name(void) \ 24 { \ 25 u_register_t v; \ 26 __asm__ volatile ("mrs %0, " #_reg_name : "=r" (v)); \ 27 return v; \ 28 } 29 30 #define _DEFINE_SYSREG_WRITE_FUNC(_name, _reg_name) \ 31 static inline void write_ ## _name(u_register_t v) \ 32 { \ 33 __asm__ volatile ("msr " #_reg_name ", %0" : : "r" (v)); \ 34 } 35 36 #define SYSREG_WRITE_CONST(reg_name, v) \ 37 __asm__ volatile ("msr " #reg_name ", %0" : : "i" (v)) 38 39 /* Define read function for system register */ 40 #define DEFINE_SYSREG_READ_FUNC(_name) \ 41 _DEFINE_SYSREG_READ_FUNC(_name, _name) 42 43 /* Define read & write function for system register */ 44 #define DEFINE_SYSREG_RW_FUNCS(_name) \ 45 _DEFINE_SYSREG_READ_FUNC(_name, _name) \ 46 _DEFINE_SYSREG_WRITE_FUNC(_name, _name) 47 48 /* Define read & write function for renamed system register */ 49 #define DEFINE_RENAME_SYSREG_RW_FUNCS(_name, _reg_name) \ 50 _DEFINE_SYSREG_READ_FUNC(_name, _reg_name) \ 51 _DEFINE_SYSREG_WRITE_FUNC(_name, _reg_name) 52 53 /* Define read function for renamed system register */ 54 #define DEFINE_RENAME_SYSREG_READ_FUNC(_name, _reg_name) \ 55 _DEFINE_SYSREG_READ_FUNC(_name, _reg_name) 56 57 /* Define write function for renamed system register */ 58 #define DEFINE_RENAME_SYSREG_WRITE_FUNC(_name, _reg_name) \ 59 _DEFINE_SYSREG_WRITE_FUNC(_name, _reg_name) 60 61 /********************************************************************** 62 * Macros to create inline functions for system instructions 63 *********************************************************************/ 64 65 /* Define function for simple system instruction */ 66 #define DEFINE_SYSOP_FUNC(_op) \ 67 static inline void _op(void) \ 68 { \ 69 __asm__ (#_op); \ 70 } 71 72 /* Define function for system instruction with register parameter */ 73 #define DEFINE_SYSOP_PARAM_FUNC(_op) \ 74 static inline void _op(uint64_t v) \ 75 { \ 76 __asm__ (#_op " %0" : : "r" (v)); \ 77 } 78 79 /* Define function for system instruction with type specifier */ 80 #define DEFINE_SYSOP_TYPE_FUNC(_op, _type) \ 81 static inline void _op ## _type(void) \ 82 { \ 83 __asm__ (#_op " " #_type); \ 84 } 85 86 /* Define function for system instruction with register parameter */ 87 #define DEFINE_SYSOP_TYPE_PARAM_FUNC(_op, _type) \ 88 static inline void _op ## _type(uint64_t v) \ 89 { \ 90 __asm__ (#_op " " #_type ", %0" : : "r" (v)); \ 91 } 92 93 /******************************************************************************* 94 * TLB maintenance accessor prototypes 95 ******************************************************************************/ 96 97 #if ERRATA_A57_813419 || ERRATA_A76_1286807 98 /* 99 * Define function for TLBI instruction with type specifier that implements 100 * the workaround for errata 813419 of Cortex-A57 or errata 1286807 of 101 * Cortex-A76. 102 */ 103 #define DEFINE_TLBIOP_ERRATA_TYPE_FUNC(_type)\ 104 static inline void tlbi ## _type(void) \ 105 { \ 106 __asm__("tlbi " #_type "\n" \ 107 "dsb ish\n" \ 108 "tlbi " #_type); \ 109 } 110 111 /* 112 * Define function for TLBI instruction with register parameter that implements 113 * the workaround for errata 813419 of Cortex-A57 or errata 1286807 of 114 * Cortex-A76. 115 */ 116 #define DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(_type) \ 117 static inline void tlbi ## _type(uint64_t v) \ 118 { \ 119 __asm__("tlbi " #_type ", %0\n" \ 120 "dsb ish\n" \ 121 "tlbi " #_type ", %0" : : "r" (v)); \ 122 } 123 #endif /* ERRATA_A57_813419 */ 124 125 #if ERRATA_A53_819472 || ERRATA_A53_824069 || ERRATA_A53_827319 126 /* 127 * Define function for DC instruction with register parameter that enables 128 * the workaround for errata 819472, 824069 and 827319 of Cortex-A53. 129 */ 130 #define DEFINE_DCOP_ERRATA_A53_TYPE_PARAM_FUNC(_name, _type) \ 131 static inline void dc ## _name(uint64_t v) \ 132 { \ 133 __asm__("dc " #_type ", %0" : : "r" (v)); \ 134 } 135 #endif /* ERRATA_A53_819472 || ERRATA_A53_824069 || ERRATA_A53_827319 */ 136 137 #if ERRATA_A57_813419 138 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle1) 139 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle1is) 140 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle2) 141 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle2is) 142 DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle3) 143 DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle3is) 144 DEFINE_SYSOP_TYPE_FUNC(tlbi, vmalle1) 145 #elif ERRATA_A76_1286807 146 DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle1) 147 DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle1is) 148 DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle2) 149 DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle2is) 150 DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle3) 151 DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle3is) 152 DEFINE_TLBIOP_ERRATA_TYPE_FUNC(vmalle1) 153 #else 154 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle1) 155 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle1is) 156 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle2) 157 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle2is) 158 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle3) 159 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle3is) 160 DEFINE_SYSOP_TYPE_FUNC(tlbi, vmalle1) 161 #endif 162 163 #if ERRATA_A57_813419 164 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vaae1is) 165 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vaale1is) 166 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vae2is) 167 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vale2is) 168 DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vae3is) 169 DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vale3is) 170 #elif ERRATA_A76_1286807 171 DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vaae1is) 172 DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vaale1is) 173 DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vae2is) 174 DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vale2is) 175 DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vae3is) 176 DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vale3is) 177 #else 178 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vaae1is) 179 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vaale1is) 180 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vae2is) 181 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vale2is) 182 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vae3is) 183 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vale3is) 184 #endif 185 186 /******************************************************************************* 187 * Cache maintenance accessor prototypes 188 ******************************************************************************/ 189 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, isw) 190 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, cisw) 191 #if ERRATA_A53_827319 192 DEFINE_DCOP_ERRATA_A53_TYPE_PARAM_FUNC(csw, cisw) 193 #else 194 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, csw) 195 #endif 196 #if ERRATA_A53_819472 || ERRATA_A53_824069 || ERRATA_A53_827319 197 DEFINE_DCOP_ERRATA_A53_TYPE_PARAM_FUNC(cvac, civac) 198 #else 199 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, cvac) 200 #endif 201 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, ivac) 202 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, civac) 203 #if ERRATA_A53_819472 || ERRATA_A53_824069 || ERRATA_A53_827319 204 DEFINE_DCOP_ERRATA_A53_TYPE_PARAM_FUNC(cvau, civac) 205 #else 206 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, cvau) 207 #endif 208 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, zva) 209 210 /******************************************************************************* 211 * Address translation accessor prototypes 212 ******************************************************************************/ 213 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e1r) 214 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e1w) 215 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e0r) 216 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e0w) 217 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s1e1r) 218 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s1e2r) 219 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s1e3r) 220 221 /******************************************************************************* 222 * Strip Pointer Authentication Code 223 ******************************************************************************/ 224 DEFINE_SYSOP_PARAM_FUNC(xpaci) 225 226 void flush_dcache_range(uintptr_t addr, size_t size); 227 void clean_dcache_range(uintptr_t addr, size_t size); 228 void inv_dcache_range(uintptr_t addr, size_t size); 229 bool is_dcache_enabled(void); 230 231 void dcsw_op_louis(u_register_t op_type); 232 void dcsw_op_all(u_register_t op_type); 233 234 void disable_mmu_el1(void); 235 void disable_mmu_el3(void); 236 void disable_mmu_icache_el1(void); 237 void disable_mmu_icache_el3(void); 238 239 /******************************************************************************* 240 * Misc. accessor prototypes 241 ******************************************************************************/ 242 243 #define write_daifclr(val) SYSREG_WRITE_CONST(daifclr, val) 244 #define write_daifset(val) SYSREG_WRITE_CONST(daifset, val) 245 246 DEFINE_SYSREG_RW_FUNCS(par_el1) 247 DEFINE_SYSREG_READ_FUNC(id_pfr1_el1) 248 DEFINE_SYSREG_READ_FUNC(id_aa64isar1_el1) 249 DEFINE_SYSREG_READ_FUNC(id_aa64pfr0_el1) 250 DEFINE_SYSREG_READ_FUNC(id_aa64pfr1_el1) 251 DEFINE_SYSREG_READ_FUNC(id_aa64dfr0_el1) 252 DEFINE_SYSREG_READ_FUNC(id_afr0_el1) 253 DEFINE_SYSREG_READ_FUNC(CurrentEl) 254 DEFINE_SYSREG_READ_FUNC(ctr_el0) 255 DEFINE_SYSREG_RW_FUNCS(daif) 256 DEFINE_SYSREG_RW_FUNCS(spsr_el1) 257 DEFINE_SYSREG_RW_FUNCS(spsr_el2) 258 DEFINE_SYSREG_RW_FUNCS(spsr_el3) 259 DEFINE_SYSREG_RW_FUNCS(elr_el1) 260 DEFINE_SYSREG_RW_FUNCS(elr_el2) 261 DEFINE_SYSREG_RW_FUNCS(elr_el3) 262 263 DEFINE_SYSOP_FUNC(wfi) 264 DEFINE_SYSOP_FUNC(wfe) 265 DEFINE_SYSOP_FUNC(sev) 266 DEFINE_SYSOP_TYPE_FUNC(dsb, sy) 267 DEFINE_SYSOP_TYPE_FUNC(dmb, sy) 268 DEFINE_SYSOP_TYPE_FUNC(dmb, st) 269 DEFINE_SYSOP_TYPE_FUNC(dmb, ld) 270 DEFINE_SYSOP_TYPE_FUNC(dsb, ish) 271 DEFINE_SYSOP_TYPE_FUNC(dsb, nsh) 272 DEFINE_SYSOP_TYPE_FUNC(dsb, ishst) 273 DEFINE_SYSOP_TYPE_FUNC(dmb, oshld) 274 DEFINE_SYSOP_TYPE_FUNC(dmb, oshst) 275 DEFINE_SYSOP_TYPE_FUNC(dmb, osh) 276 DEFINE_SYSOP_TYPE_FUNC(dmb, nshld) 277 DEFINE_SYSOP_TYPE_FUNC(dmb, nshst) 278 DEFINE_SYSOP_TYPE_FUNC(dmb, nsh) 279 DEFINE_SYSOP_TYPE_FUNC(dmb, ishld) 280 DEFINE_SYSOP_TYPE_FUNC(dmb, ishst) 281 DEFINE_SYSOP_TYPE_FUNC(dmb, ish) 282 DEFINE_SYSOP_FUNC(isb) 283 284 static inline void enable_irq(void) 285 { 286 /* 287 * The compiler memory barrier will prevent the compiler from 288 * scheduling non-volatile memory access after the write to the 289 * register. 290 * 291 * This could happen if some initialization code issues non-volatile 292 * accesses to an area used by an interrupt handler, in the assumption 293 * that it is safe as the interrupts are disabled at the time it does 294 * that (according to program order). However, non-volatile accesses 295 * are not necessarily in program order relatively with volatile inline 296 * assembly statements (and volatile accesses). 297 */ 298 COMPILER_BARRIER(); 299 write_daifclr(DAIF_IRQ_BIT); 300 isb(); 301 } 302 303 static inline void enable_fiq(void) 304 { 305 COMPILER_BARRIER(); 306 write_daifclr(DAIF_FIQ_BIT); 307 isb(); 308 } 309 310 static inline void enable_serror(void) 311 { 312 COMPILER_BARRIER(); 313 write_daifclr(DAIF_ABT_BIT); 314 isb(); 315 } 316 317 static inline void enable_debug_exceptions(void) 318 { 319 COMPILER_BARRIER(); 320 write_daifclr(DAIF_DBG_BIT); 321 isb(); 322 } 323 324 static inline void disable_irq(void) 325 { 326 COMPILER_BARRIER(); 327 write_daifset(DAIF_IRQ_BIT); 328 isb(); 329 } 330 331 static inline void disable_fiq(void) 332 { 333 COMPILER_BARRIER(); 334 write_daifset(DAIF_FIQ_BIT); 335 isb(); 336 } 337 338 static inline void disable_serror(void) 339 { 340 COMPILER_BARRIER(); 341 write_daifset(DAIF_ABT_BIT); 342 isb(); 343 } 344 345 static inline void disable_debug_exceptions(void) 346 { 347 COMPILER_BARRIER(); 348 write_daifset(DAIF_DBG_BIT); 349 isb(); 350 } 351 352 void __dead2 smc(uint64_t x0, uint64_t x1, uint64_t x2, uint64_t x3, 353 uint64_t x4, uint64_t x5, uint64_t x6, uint64_t x7); 354 355 /******************************************************************************* 356 * System register accessor prototypes 357 ******************************************************************************/ 358 DEFINE_SYSREG_READ_FUNC(midr_el1) 359 DEFINE_SYSREG_READ_FUNC(mpidr_el1) 360 DEFINE_SYSREG_READ_FUNC(id_aa64mmfr0_el1) 361 362 DEFINE_SYSREG_RW_FUNCS(scr_el3) 363 DEFINE_SYSREG_RW_FUNCS(hcr_el2) 364 365 DEFINE_SYSREG_RW_FUNCS(vbar_el1) 366 DEFINE_SYSREG_RW_FUNCS(vbar_el2) 367 DEFINE_SYSREG_RW_FUNCS(vbar_el3) 368 369 DEFINE_SYSREG_RW_FUNCS(sctlr_el1) 370 DEFINE_SYSREG_RW_FUNCS(sctlr_el2) 371 DEFINE_SYSREG_RW_FUNCS(sctlr_el3) 372 373 DEFINE_SYSREG_RW_FUNCS(actlr_el1) 374 DEFINE_SYSREG_RW_FUNCS(actlr_el2) 375 DEFINE_SYSREG_RW_FUNCS(actlr_el3) 376 377 DEFINE_SYSREG_RW_FUNCS(esr_el1) 378 DEFINE_SYSREG_RW_FUNCS(esr_el2) 379 DEFINE_SYSREG_RW_FUNCS(esr_el3) 380 381 DEFINE_SYSREG_RW_FUNCS(afsr0_el1) 382 DEFINE_SYSREG_RW_FUNCS(afsr0_el2) 383 DEFINE_SYSREG_RW_FUNCS(afsr0_el3) 384 385 DEFINE_SYSREG_RW_FUNCS(afsr1_el1) 386 DEFINE_SYSREG_RW_FUNCS(afsr1_el2) 387 DEFINE_SYSREG_RW_FUNCS(afsr1_el3) 388 389 DEFINE_SYSREG_RW_FUNCS(far_el1) 390 DEFINE_SYSREG_RW_FUNCS(far_el2) 391 DEFINE_SYSREG_RW_FUNCS(far_el3) 392 393 DEFINE_SYSREG_RW_FUNCS(mair_el1) 394 DEFINE_SYSREG_RW_FUNCS(mair_el2) 395 DEFINE_SYSREG_RW_FUNCS(mair_el3) 396 397 DEFINE_SYSREG_RW_FUNCS(amair_el1) 398 DEFINE_SYSREG_RW_FUNCS(amair_el2) 399 DEFINE_SYSREG_RW_FUNCS(amair_el3) 400 401 DEFINE_SYSREG_READ_FUNC(rvbar_el1) 402 DEFINE_SYSREG_READ_FUNC(rvbar_el2) 403 DEFINE_SYSREG_READ_FUNC(rvbar_el3) 404 405 DEFINE_SYSREG_RW_FUNCS(rmr_el1) 406 DEFINE_SYSREG_RW_FUNCS(rmr_el2) 407 DEFINE_SYSREG_RW_FUNCS(rmr_el3) 408 409 DEFINE_SYSREG_RW_FUNCS(tcr_el1) 410 DEFINE_SYSREG_RW_FUNCS(tcr_el2) 411 DEFINE_SYSREG_RW_FUNCS(tcr_el3) 412 413 DEFINE_SYSREG_RW_FUNCS(ttbr0_el1) 414 DEFINE_SYSREG_RW_FUNCS(ttbr0_el2) 415 DEFINE_SYSREG_RW_FUNCS(ttbr0_el3) 416 417 DEFINE_SYSREG_RW_FUNCS(ttbr1_el1) 418 419 DEFINE_SYSREG_RW_FUNCS(vttbr_el2) 420 421 DEFINE_SYSREG_RW_FUNCS(cptr_el2) 422 DEFINE_SYSREG_RW_FUNCS(cptr_el3) 423 424 DEFINE_SYSREG_RW_FUNCS(cpacr_el1) 425 DEFINE_SYSREG_RW_FUNCS(cntfrq_el0) 426 DEFINE_SYSREG_RW_FUNCS(cnthp_ctl_el2) 427 DEFINE_SYSREG_RW_FUNCS(cnthp_tval_el2) 428 DEFINE_SYSREG_RW_FUNCS(cnthp_cval_el2) 429 DEFINE_SYSREG_RW_FUNCS(cntps_ctl_el1) 430 DEFINE_SYSREG_RW_FUNCS(cntps_tval_el1) 431 DEFINE_SYSREG_RW_FUNCS(cntps_cval_el1) 432 DEFINE_SYSREG_RW_FUNCS(cntp_ctl_el0) 433 DEFINE_SYSREG_RW_FUNCS(cntp_tval_el0) 434 DEFINE_SYSREG_RW_FUNCS(cntp_cval_el0) 435 DEFINE_SYSREG_READ_FUNC(cntpct_el0) 436 DEFINE_SYSREG_RW_FUNCS(cnthctl_el2) 437 438 #define get_cntp_ctl_enable(x) (((x) >> CNTP_CTL_ENABLE_SHIFT) & \ 439 CNTP_CTL_ENABLE_MASK) 440 #define get_cntp_ctl_imask(x) (((x) >> CNTP_CTL_IMASK_SHIFT) & \ 441 CNTP_CTL_IMASK_MASK) 442 #define get_cntp_ctl_istatus(x) (((x) >> CNTP_CTL_ISTATUS_SHIFT) & \ 443 CNTP_CTL_ISTATUS_MASK) 444 445 #define set_cntp_ctl_enable(x) ((x) |= (U(1) << CNTP_CTL_ENABLE_SHIFT)) 446 #define set_cntp_ctl_imask(x) ((x) |= (U(1) << CNTP_CTL_IMASK_SHIFT)) 447 448 #define clr_cntp_ctl_enable(x) ((x) &= ~(U(1) << CNTP_CTL_ENABLE_SHIFT)) 449 #define clr_cntp_ctl_imask(x) ((x) &= ~(U(1) << CNTP_CTL_IMASK_SHIFT)) 450 451 DEFINE_SYSREG_RW_FUNCS(tpidr_el3) 452 453 DEFINE_SYSREG_RW_FUNCS(cntvoff_el2) 454 455 DEFINE_SYSREG_RW_FUNCS(vpidr_el2) 456 DEFINE_SYSREG_RW_FUNCS(vmpidr_el2) 457 458 DEFINE_SYSREG_READ_FUNC(isr_el1) 459 460 DEFINE_SYSREG_RW_FUNCS(mdcr_el2) 461 DEFINE_SYSREG_RW_FUNCS(mdcr_el3) 462 DEFINE_SYSREG_RW_FUNCS(hstr_el2) 463 DEFINE_SYSREG_RW_FUNCS(pmcr_el0) 464 465 /* GICv3 System Registers */ 466 467 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el1, ICC_SRE_EL1) 468 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el2, ICC_SRE_EL2) 469 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el3, ICC_SRE_EL3) 470 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_pmr_el1, ICC_PMR_EL1) 471 DEFINE_RENAME_SYSREG_READ_FUNC(icc_rpr_el1, ICC_RPR_EL1) 472 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_igrpen1_el3, ICC_IGRPEN1_EL3) 473 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_igrpen1_el1, ICC_IGRPEN1_EL1) 474 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_igrpen0_el1, ICC_IGRPEN0_EL1) 475 DEFINE_RENAME_SYSREG_READ_FUNC(icc_hppir0_el1, ICC_HPPIR0_EL1) 476 DEFINE_RENAME_SYSREG_READ_FUNC(icc_hppir1_el1, ICC_HPPIR1_EL1) 477 DEFINE_RENAME_SYSREG_READ_FUNC(icc_iar0_el1, ICC_IAR0_EL1) 478 DEFINE_RENAME_SYSREG_READ_FUNC(icc_iar1_el1, ICC_IAR1_EL1) 479 DEFINE_RENAME_SYSREG_WRITE_FUNC(icc_eoir0_el1, ICC_EOIR0_EL1) 480 DEFINE_RENAME_SYSREG_WRITE_FUNC(icc_eoir1_el1, ICC_EOIR1_EL1) 481 DEFINE_RENAME_SYSREG_WRITE_FUNC(icc_sgi0r_el1, ICC_SGI0R_EL1) 482 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sgi1r, ICC_SGI1R) 483 484 DEFINE_RENAME_SYSREG_RW_FUNCS(amcgcr_el0, AMCGCR_EL0) 485 DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenclr0_el0, AMCNTENCLR0_EL0) 486 DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenset0_el0, AMCNTENSET0_EL0) 487 DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenclr1_el0, AMCNTENCLR1_EL0) 488 DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenset1_el0, AMCNTENSET1_EL0) 489 490 DEFINE_RENAME_SYSREG_READ_FUNC(mpamidr_el1, MPAMIDR_EL1) 491 DEFINE_RENAME_SYSREG_RW_FUNCS(mpam3_el3, MPAM3_EL3) 492 DEFINE_RENAME_SYSREG_RW_FUNCS(mpam2_el2, MPAM2_EL2) 493 DEFINE_RENAME_SYSREG_RW_FUNCS(mpamhcr_el2, MPAMHCR_EL2) 494 495 DEFINE_RENAME_SYSREG_RW_FUNCS(pmblimitr_el1, PMBLIMITR_EL1) 496 497 DEFINE_RENAME_SYSREG_WRITE_FUNC(zcr_el3, ZCR_EL3) 498 DEFINE_RENAME_SYSREG_WRITE_FUNC(zcr_el2, ZCR_EL2) 499 500 DEFINE_RENAME_SYSREG_READ_FUNC(erridr_el1, ERRIDR_EL1) 501 DEFINE_RENAME_SYSREG_WRITE_FUNC(errselr_el1, ERRSELR_EL1) 502 503 DEFINE_RENAME_SYSREG_READ_FUNC(erxfr_el1, ERXFR_EL1) 504 DEFINE_RENAME_SYSREG_RW_FUNCS(erxctlr_el1, ERXCTLR_EL1) 505 DEFINE_RENAME_SYSREG_RW_FUNCS(erxstatus_el1, ERXSTATUS_EL1) 506 DEFINE_RENAME_SYSREG_READ_FUNC(erxaddr_el1, ERXADDR_EL1) 507 DEFINE_RENAME_SYSREG_READ_FUNC(erxmisc0_el1, ERXMISC0_EL1) 508 DEFINE_RENAME_SYSREG_READ_FUNC(erxmisc1_el1, ERXMISC1_EL1) 509 510 /* Armv8.2 Registers */ 511 DEFINE_RENAME_SYSREG_READ_FUNC(id_aa64mmfr2_el1, ID_AA64MMFR2_EL1) 512 513 /* Armv8.3 Pointer Authentication Registers */ 514 DEFINE_RENAME_SYSREG_RW_FUNCS(apiakeyhi_el1, APIAKeyHi_EL1) 515 DEFINE_RENAME_SYSREG_RW_FUNCS(apiakeylo_el1, APIAKeyLo_EL1) 516 517 /* Armv8.5 MTE Registers */ 518 DEFINE_RENAME_SYSREG_RW_FUNCS(tfsre0_el1, TFSRE0_EL1) 519 DEFINE_RENAME_SYSREG_RW_FUNCS(tfsr_el1, TFSR_EL1) 520 DEFINE_RENAME_SYSREG_RW_FUNCS(rgsr_el1, RGSR_EL1) 521 DEFINE_RENAME_SYSREG_RW_FUNCS(gcr_el1, GCR_EL1) 522 523 /* DynamIQ Shared Unit power management */ 524 DEFINE_RENAME_SYSREG_RW_FUNCS(clusterpwrdn_el1, CLUSTERPWRDN_EL1) 525 526 #define IS_IN_EL(x) \ 527 (GET_EL(read_CurrentEl()) == MODE_EL##x) 528 529 #define IS_IN_EL1() IS_IN_EL(1) 530 #define IS_IN_EL2() IS_IN_EL(2) 531 #define IS_IN_EL3() IS_IN_EL(3) 532 533 static inline unsigned int get_current_el(void) 534 { 535 return GET_EL(read_CurrentEl()); 536 } 537 538 static inline unsigned int get_current_el_maybe_constant(void) 539 { 540 #if defined(IMAGE_AT_EL1) 541 return 1; 542 #elif defined(IMAGE_AT_EL2) 543 return 2; /* no use-case in TF-A */ 544 #elif defined(IMAGE_AT_EL3) 545 return 3; 546 #else 547 /* 548 * If we do not know which exception level this is being built for 549 * (e.g. built for library), fall back to run-time detection. 550 */ 551 return get_current_el(); 552 #endif 553 } 554 555 /* 556 * Check if an EL is implemented from AA64PFR0 register fields. 557 */ 558 static inline uint64_t el_implemented(unsigned int el) 559 { 560 if (el > 3U) { 561 return EL_IMPL_NONE; 562 } else { 563 unsigned int shift = ID_AA64PFR0_EL1_SHIFT * el; 564 565 return (read_id_aa64pfr0_el1() >> shift) & ID_AA64PFR0_ELX_MASK; 566 } 567 } 568 569 /* Previously defined accesor functions with incomplete register names */ 570 571 #define read_current_el() read_CurrentEl() 572 573 #define dsb() dsbsy() 574 575 #define read_midr() read_midr_el1() 576 577 #define read_mpidr() read_mpidr_el1() 578 579 #define read_scr() read_scr_el3() 580 #define write_scr(_v) write_scr_el3(_v) 581 582 #define read_hcr() read_hcr_el2() 583 #define write_hcr(_v) write_hcr_el2(_v) 584 585 #define read_cpacr() read_cpacr_el1() 586 #define write_cpacr(_v) write_cpacr_el1(_v) 587 588 #define read_clusterpwrdn() read_clusterpwrdn_el1() 589 #define write_clusterpwrdn(_v) write_clusterpwrdn_el1(_v) 590 591 #endif /* ARCH_HELPERS_H */ 592