1 /* 2 * Copyright (c) 2019-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef ARCH_FEATURES_H 8 #define ARCH_FEATURES_H 9 10 #include <stdbool.h> 11 12 #include <arch_helpers.h> 13 #include <common/feat_detect.h> 14 15 #define ISOLATE_FIELD(reg, feat, mask) \ 16 ((unsigned int)(((reg) >> (feat)) & mask)) 17 18 #define CREATE_FEATURE_SUPPORTED(name, read_func, guard) \ 19 __attribute__((always_inline)) \ 20 static inline bool is_ ## name ## _supported(void) \ 21 { \ 22 if ((guard) == FEAT_STATE_DISABLED) { \ 23 return false; \ 24 } \ 25 if ((guard) == FEAT_STATE_ALWAYS) { \ 26 return true; \ 27 } \ 28 return read_func(); \ 29 } 30 31 #define CREATE_FEATURE_PRESENT(name, idreg, idfield, mask, idval) \ 32 __attribute__((always_inline)) \ 33 static inline bool is_ ## name ## _present(void) \ 34 { \ 35 return (ISOLATE_FIELD(read_ ## idreg(), idfield, mask) >= idval) \ 36 ? true : false; \ 37 } 38 39 #define CREATE_FEATURE_FUNCS(name, idreg, idfield, mask, idval, guard) \ 40 CREATE_FEATURE_PRESENT(name, idreg, idfield, mask, idval) \ 41 CREATE_FEATURE_SUPPORTED(name, is_ ## name ## _present, guard) 42 43 44 /* +----------------------------+ 45 * | Features supported | 46 * +----------------------------+ 47 * | GENTIMER | 48 * +----------------------------+ 49 * | FEAT_PAN | 50 * +----------------------------+ 51 * | FEAT_VHE | 52 * +----------------------------+ 53 * | FEAT_TTCNP | 54 * +----------------------------+ 55 * | FEAT_UAO | 56 * +----------------------------+ 57 * | FEAT_PACQARMA3 | 58 * +----------------------------+ 59 * | FEAT_PAUTH | 60 * +----------------------------+ 61 * | FEAT_TTST | 62 * +----------------------------+ 63 * | FEAT_BTI | 64 * +----------------------------+ 65 * | FEAT_MTE2 | 66 * +----------------------------+ 67 * | FEAT_SSBS | 68 * +----------------------------+ 69 * | FEAT_NMI | 70 * +----------------------------+ 71 * | FEAT_GCS | 72 * +----------------------------+ 73 * | FEAT_EBEP | 74 * +----------------------------+ 75 * | FEAT_SEBEP | 76 * +----------------------------+ 77 * | FEAT_SEL2 | 78 * +----------------------------+ 79 * | FEAT_TWED | 80 * +----------------------------+ 81 * | FEAT_FGT | 82 * +----------------------------+ 83 * | FEAT_EC/ECV2 | 84 * +----------------------------+ 85 * | FEAT_RNG | 86 * +----------------------------+ 87 * | FEAT_TCR2 | 88 * +----------------------------+ 89 * | FEAT_S2POE | 90 * +----------------------------+ 91 * | FEAT_S1POE | 92 * +----------------------------+ 93 * | FEAT_S2PIE | 94 * +----------------------------+ 95 * | FEAT_S1PIE | 96 * +----------------------------+ 97 * | FEAT_AMU/AMUV1P1 | 98 * +----------------------------+ 99 * | FEAT_MPAM | 100 * +----------------------------+ 101 * | FEAT_HCX | 102 * +----------------------------+ 103 * | FEAT_RNG_TRAP | 104 * +----------------------------+ 105 * | FEAT_RME | 106 * +----------------------------+ 107 * | FEAT_SB | 108 * +----------------------------+ 109 * | FEAT_CSV2/CSV3 | 110 * +----------------------------+ 111 * | FEAT_SPE | 112 * +----------------------------+ 113 * | FEAT_SVE | 114 * +----------------------------+ 115 * | FEAT_RAS | 116 * +----------------------------+ 117 * | FEAT_DIT | 118 * +----------------------------+ 119 * | FEAT_SYS_REG_TRACE | 120 * +----------------------------+ 121 * | FEAT_TRF | 122 * +----------------------------+ 123 * | FEAT_NV/NV2 | 124 * +----------------------------+ 125 * | FEAT_BRBE | 126 * +----------------------------+ 127 * | FEAT_TRBE | 128 * +----------------------------+ 129 * | FEAT_SME/SME2 | 130 * +----------------------------+ 131 * | FEAT_PMUV3 | 132 * +----------------------------+ 133 * | FEAT_MTPMU | 134 * +----------------------------+ 135 * | FEAT_FGT2 | 136 * +----------------------------+ 137 * | FEAT_THE | 138 * +----------------------------+ 139 * | FEAT_SCTLR2 | 140 * +----------------------------+ 141 * | FEAT_D128 | 142 * +----------------------------+ 143 * | FEAT_LS64_ACCDATA | 144 * +----------------------------+ 145 * | FEAT_FPMR | 146 * +----------------------------+ 147 * | FEAT_MOPS | 148 * +----------------------------+ 149 * | FEAT_PAUTH_LR | 150 * +----------------------------+ 151 */ 152 153 __attribute__((always_inline)) 154 static inline bool is_armv7_gentimer_present(void) 155 { 156 /* The Generic Timer is always present in an ARMv8-A implementation */ 157 return true; 158 } 159 160 /* FEAT_PAN: Privileged access never */ 161 CREATE_FEATURE_FUNCS(feat_pan, id_aa64mmfr1_el1, ID_AA64MMFR1_EL1_PAN_SHIFT, 162 ID_AA64MMFR1_EL1_PAN_MASK, 1U, ENABLE_FEAT_PAN) 163 164 /* FEAT_VHE: Virtualization Host Extensions */ 165 CREATE_FEATURE_FUNCS(feat_vhe, id_aa64mmfr1_el1, ID_AA64MMFR1_EL1_VHE_SHIFT, 166 ID_AA64MMFR1_EL1_VHE_MASK, 1U, ENABLE_FEAT_VHE) 167 168 /* FEAT_TTCNP: Translation table common not private */ 169 CREATE_FEATURE_PRESENT(feat_ttcnp, id_aa64mmfr2_el1, ID_AA64MMFR2_EL1_CNP_SHIFT, 170 ID_AA64MMFR2_EL1_CNP_MASK, 1U) 171 172 /* FEAT_UAO: User access override */ 173 CREATE_FEATURE_PRESENT(feat_uao, id_aa64mmfr2_el1, ID_AA64MMFR2_EL1_UAO_SHIFT, 174 ID_AA64MMFR2_EL1_UAO_MASK, 1U) 175 176 /* If any of the fields is not zero, QARMA3 algorithm is present */ 177 CREATE_FEATURE_PRESENT(feat_pacqarma3, id_aa64isar2_el1, 0, 178 ((ID_AA64ISAR2_GPA3_MASK << ID_AA64ISAR2_GPA3_SHIFT) | 179 (ID_AA64ISAR2_APA3_MASK << ID_AA64ISAR2_APA3_SHIFT)), 1U) 180 181 /* FEAT_PAUTH: Pointer Authentication */ 182 __attribute__((always_inline)) 183 static inline bool is_feat_pauth_present(void) 184 { 185 uint64_t mask_id_aa64isar1 = 186 (ID_AA64ISAR1_GPI_MASK << ID_AA64ISAR1_GPI_SHIFT) | 187 (ID_AA64ISAR1_GPA_MASK << ID_AA64ISAR1_GPA_SHIFT) | 188 (ID_AA64ISAR1_API_MASK << ID_AA64ISAR1_API_SHIFT) | 189 (ID_AA64ISAR1_APA_MASK << ID_AA64ISAR1_APA_SHIFT); 190 191 /* 192 * If any of the fields is not zero or QARMA3 is present, 193 * PAuth is present 194 */ 195 return ((read_id_aa64isar1_el1() & mask_id_aa64isar1) != 0U || 196 is_feat_pacqarma3_present()); 197 } 198 CREATE_FEATURE_SUPPORTED(feat_pauth, is_feat_pauth_present, ENABLE_PAUTH) 199 CREATE_FEATURE_SUPPORTED(ctx_pauth, is_feat_pauth_present, CTX_INCLUDE_PAUTH_REGS) 200 201 /* 202 * FEAT_PAUTH_LR 203 * This feature has a non-standard discovery method so define this function 204 * manually then call use the CREATE_FEATURE_SUPPORTED macro with it. This 205 * feature is enabled with ENABLE_PAUTH when present. 206 */ 207 __attribute__((always_inline)) 208 static inline bool is_feat_pauth_lr_present(void) 209 { 210 /* 211 * FEAT_PAUTH_LR support is indicated by up to 3 fields, if one or more 212 * of these is 0b0110 then the feature is present. 213 * 1) id_aa64isr1_el1.api 214 * 2) id_aa64isr1_el1.apa 215 * 3) id_aa64isr2_el1.apa3 216 */ 217 if (ISOLATE_FIELD(read_id_aa64isar1_el1(), ID_AA64ISAR1_API_SHIFT, ID_AA64ISAR1_API_MASK) == 0b0110) { 218 return true; 219 } 220 if (ISOLATE_FIELD(read_id_aa64isar1_el1(), ID_AA64ISAR1_APA_SHIFT, ID_AA64ISAR1_APA_MASK) == 0b0110) { 221 return true; 222 } 223 if (ISOLATE_FIELD(read_id_aa64isar2_el1(), ID_AA64ISAR2_APA3_SHIFT, ID_AA64ISAR2_APA3_MASK) == 0b0110) { 224 return true; 225 } 226 return false; 227 } 228 CREATE_FEATURE_SUPPORTED(feat_pauth_lr, is_feat_pauth_lr_present, ENABLE_FEAT_PAUTH_LR) 229 230 /* FEAT_TTST: Small translation tables */ 231 CREATE_FEATURE_PRESENT(feat_ttst, id_aa64mmfr2_el1, ID_AA64MMFR2_EL1_ST_SHIFT, 232 ID_AA64MMFR2_EL1_ST_MASK, 1U) 233 234 /* FEAT_BTI: Branch target identification */ 235 CREATE_FEATURE_FUNCS(feat_bti, id_aa64pfr1_el1, ID_AA64PFR1_EL1_BT_SHIFT, 236 ID_AA64PFR1_EL1_BT_MASK, BTI_IMPLEMENTED, ENABLE_BTI) 237 238 /* FEAT_MTE2: Memory tagging extension */ 239 CREATE_FEATURE_FUNCS(feat_mte2, id_aa64pfr1_el1, ID_AA64PFR1_EL1_MTE_SHIFT, 240 ID_AA64PFR1_EL1_MTE_MASK, MTE_IMPLEMENTED_ELX, ENABLE_FEAT_MTE2) 241 242 /* FEAT_SSBS: Speculative store bypass safe */ 243 CREATE_FEATURE_PRESENT(feat_ssbs, id_aa64pfr1_el1, ID_AA64PFR1_EL1_SSBS_SHIFT, 244 ID_AA64PFR1_EL1_SSBS_MASK, 1U) 245 246 /* FEAT_NMI: Non-maskable interrupts */ 247 CREATE_FEATURE_PRESENT(feat_nmi, id_aa64pfr1_el1, ID_AA64PFR1_EL1_NMI_SHIFT, 248 ID_AA64PFR1_EL1_NMI_MASK, NMI_IMPLEMENTED) 249 250 /* FEAT_EBEP */ 251 CREATE_FEATURE_PRESENT(feat_ebep, id_aa64dfr1_el1, ID_AA64DFR1_EBEP_SHIFT, 252 ID_AA64DFR1_EBEP_MASK, EBEP_IMPLEMENTED) 253 254 /* FEAT_SEBEP */ 255 CREATE_FEATURE_PRESENT(feat_sebep, id_aa64dfr0_el1, ID_AA64DFR0_SEBEP_SHIFT, 256 ID_AA64DFR0_SEBEP_MASK, SEBEP_IMPLEMENTED) 257 258 /* FEAT_SEL2: Secure EL2 */ 259 CREATE_FEATURE_FUNCS(feat_sel2, id_aa64pfr0_el1, ID_AA64PFR0_SEL2_SHIFT, 260 ID_AA64PFR0_SEL2_MASK, 1U, ENABLE_FEAT_SEL2) 261 262 /* FEAT_TWED: Delayed trapping of WFE */ 263 CREATE_FEATURE_FUNCS(feat_twed, id_aa64mmfr1_el1, ID_AA64MMFR1_EL1_TWED_SHIFT, 264 ID_AA64MMFR1_EL1_TWED_MASK, 1U, ENABLE_FEAT_TWED) 265 266 /* FEAT_FGT: Fine-grained traps */ 267 CREATE_FEATURE_FUNCS(feat_fgt, id_aa64mmfr0_el1, ID_AA64MMFR0_EL1_FGT_SHIFT, 268 ID_AA64MMFR0_EL1_FGT_MASK, 1U, ENABLE_FEAT_FGT) 269 270 /* FEAT_FGT2: Fine-grained traps extended */ 271 CREATE_FEATURE_FUNCS(feat_fgt2, id_aa64mmfr0_el1, ID_AA64MMFR0_EL1_FGT_SHIFT, 272 ID_AA64MMFR0_EL1_FGT_MASK, FGT2_IMPLEMENTED, ENABLE_FEAT_FGT2) 273 274 /* FEAT_ECV: Enhanced Counter Virtualization */ 275 CREATE_FEATURE_FUNCS(feat_ecv, id_aa64mmfr0_el1, ID_AA64MMFR0_EL1_ECV_SHIFT, 276 ID_AA64MMFR0_EL1_ECV_MASK, 1U, ENABLE_FEAT_ECV) 277 CREATE_FEATURE_FUNCS(feat_ecv_v2, id_aa64mmfr0_el1, ID_AA64MMFR0_EL1_ECV_SHIFT, 278 ID_AA64MMFR0_EL1_ECV_MASK, ID_AA64MMFR0_EL1_ECV_SELF_SYNCH, ENABLE_FEAT_ECV) 279 280 /* FEAT_RNG: Random number generator */ 281 CREATE_FEATURE_FUNCS(feat_rng, id_aa64isar0_el1, ID_AA64ISAR0_RNDR_SHIFT, 282 ID_AA64ISAR0_RNDR_MASK, 1U, ENABLE_FEAT_RNG) 283 284 /* FEAT_TCR2: Support TCR2_ELx regs */ 285 CREATE_FEATURE_FUNCS(feat_tcr2, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_TCRX_SHIFT, 286 ID_AA64MMFR3_EL1_TCRX_MASK, 1U, ENABLE_FEAT_TCR2) 287 288 /* FEAT_S2POE */ 289 CREATE_FEATURE_FUNCS(feat_s2poe, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_S2POE_SHIFT, 290 ID_AA64MMFR3_EL1_S2POE_MASK, 1U, ENABLE_FEAT_S2POE) 291 292 /* FEAT_S1POE */ 293 CREATE_FEATURE_FUNCS(feat_s1poe, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_S1POE_SHIFT, 294 ID_AA64MMFR3_EL1_S1POE_MASK, 1U, ENABLE_FEAT_S1POE) 295 296 __attribute__((always_inline)) 297 static inline bool is_feat_sxpoe_supported(void) 298 { 299 return is_feat_s1poe_supported() || is_feat_s2poe_supported(); 300 } 301 302 /* FEAT_S2PIE */ 303 CREATE_FEATURE_FUNCS(feat_s2pie, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_S2PIE_SHIFT, 304 ID_AA64MMFR3_EL1_S2PIE_MASK, 1U, ENABLE_FEAT_S2PIE) 305 306 /* FEAT_S1PIE */ 307 CREATE_FEATURE_FUNCS(feat_s1pie, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_S1PIE_SHIFT, 308 ID_AA64MMFR3_EL1_S1PIE_MASK, 1U, ENABLE_FEAT_S1PIE) 309 310 /* FEAT_THE: Translation Hardening Extension */ 311 CREATE_FEATURE_FUNCS(feat_the, id_aa64pfr1_el1, ID_AA64PFR1_EL1_THE_SHIFT, 312 ID_AA64PFR1_EL1_THE_MASK, THE_IMPLEMENTED, ENABLE_FEAT_THE) 313 314 /* FEAT_SCTLR2 */ 315 CREATE_FEATURE_FUNCS(feat_sctlr2, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_SCTLR2_SHIFT, 316 ID_AA64MMFR3_EL1_SCTLR2_MASK, SCTLR2_IMPLEMENTED, 317 ENABLE_FEAT_SCTLR2) 318 319 /* FEAT_D128 */ 320 CREATE_FEATURE_FUNCS(feat_d128, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_D128_SHIFT, 321 ID_AA64MMFR3_EL1_D128_MASK, D128_IMPLEMENTED, 322 ENABLE_FEAT_D128) 323 324 /* FEAT_FPMR */ 325 CREATE_FEATURE_FUNCS(feat_fpmr, id_aa64pfr2_el1, ID_AA64PFR2_EL1_FPMR_SHIFT, 326 ID_AA64PFR2_EL1_FPMR_MASK, FPMR_IMPLEMENTED, 327 ENABLE_FEAT_FPMR) 328 /* FEAT_MOPS */ 329 CREATE_FEATURE_FUNCS(feat_mops, id_aa64isar2_el1, ID_AA64ISAR2_EL1_MOPS_SHIFT, 330 ID_AA64ISAR2_EL1_MOPS_MASK, MOPS_IMPLEMENTED, 331 ENABLE_FEAT_MOPS) 332 333 __attribute__((always_inline)) 334 static inline bool is_feat_sxpie_supported(void) 335 { 336 return is_feat_s1pie_supported() || is_feat_s2pie_supported(); 337 } 338 339 /* FEAT_GCS: Guarded Control Stack */ 340 CREATE_FEATURE_FUNCS(feat_gcs, id_aa64pfr1_el1, ID_AA64PFR1_EL1_GCS_SHIFT, 341 ID_AA64PFR1_EL1_GCS_MASK, 1U, ENABLE_FEAT_GCS) 342 343 /* FEAT_AMU: Activity Monitors Extension */ 344 CREATE_FEATURE_FUNCS(feat_amu, id_aa64pfr0_el1, ID_AA64PFR0_AMU_SHIFT, 345 ID_AA64PFR0_AMU_MASK, 1U, ENABLE_FEAT_AMU) 346 347 /* Auxiliary counters for FEAT_AMU */ 348 CREATE_FEATURE_FUNCS(feat_amu_aux, amcfgr_el0, AMCFGR_EL0_NCG_SHIFT, 349 AMCFGR_EL0_NCG_MASK, 1U, ENABLE_AMU_AUXILIARY_COUNTERS) 350 351 /* FEAT_AMUV1P1: AMU Extension v1.1 */ 352 CREATE_FEATURE_FUNCS(feat_amuv1p1, id_aa64pfr0_el1, ID_AA64PFR0_AMU_SHIFT, 353 ID_AA64PFR0_AMU_MASK, ID_AA64PFR0_AMU_V1P1, ENABLE_FEAT_AMUv1p1) 354 355 /* 356 * Return MPAM version: 357 * 358 * 0x00: None Armv8.0 or later 359 * 0x01: v0.1 Armv8.4 or later 360 * 0x10: v1.0 Armv8.2 or later 361 * 0x11: v1.1 Armv8.4 or later 362 * 363 */ 364 __attribute__((always_inline)) 365 static inline bool is_feat_mpam_present(void) 366 { 367 unsigned int ret = (unsigned int)((((read_id_aa64pfr0_el1() >> 368 ID_AA64PFR0_MPAM_SHIFT) & ID_AA64PFR0_MPAM_MASK) << 4) | 369 ((read_id_aa64pfr1_el1() >> ID_AA64PFR1_MPAM_FRAC_SHIFT) 370 & ID_AA64PFR1_MPAM_FRAC_MASK)); 371 return ret; 372 } 373 374 CREATE_FEATURE_SUPPORTED(feat_mpam, is_feat_mpam_present, ENABLE_FEAT_MPAM) 375 376 /* 377 * FEAT_DebugV8P9: Debug extension. This function checks the field 3:0 of 378 * ID_AA64DFR0 Aarch64 Debug Feature Register 0 for the version of 379 * Feat_Debug supported. The value of the field determines feature presence 380 * 381 * 0b0110 - Arm v8.0 debug 382 * 0b0111 - Arm v8.0 debug architecture with Virtualization host extensions 383 * 0x1000 - FEAT_Debugv8p2 is supported 384 * 0x1001 - FEAT_Debugv8p4 is supported 385 * 0x1010 - FEAT_Debugv8p8 is supported 386 * 0x1011 - FEAT_Debugv8p9 is supported 387 * 388 */ 389 CREATE_FEATURE_FUNCS(feat_debugv8p9, id_aa64dfr0_el1, ID_AA64DFR0_DEBUGVER_SHIFT, 390 ID_AA64DFR0_DEBUGVER_MASK, DEBUGVER_V8P9_IMPLEMENTED, 391 ENABLE_FEAT_DEBUGV8P9) 392 393 /* FEAT_HCX: Extended Hypervisor Configuration Register */ 394 CREATE_FEATURE_FUNCS(feat_hcx, id_aa64mmfr1_el1, ID_AA64MMFR1_EL1_HCX_SHIFT, 395 ID_AA64MMFR1_EL1_HCX_MASK, 1U, ENABLE_FEAT_HCX) 396 397 /* FEAT_RNG_TRAP: Trapping support */ 398 CREATE_FEATURE_FUNCS(feat_rng_trap, id_aa64pfr1_el1, ID_AA64PFR1_EL1_RNDR_TRAP_SHIFT, 399 ID_AA64PFR1_EL1_RNDR_TRAP_MASK, RNG_TRAP_IMPLEMENTED, ENABLE_FEAT_RNG_TRAP) 400 401 /* Return the RME version, zero if not supported. */ 402 CREATE_FEATURE_FUNCS(feat_rme, id_aa64pfr0_el1, ID_AA64PFR0_FEAT_RME_SHIFT, 403 ID_AA64PFR0_FEAT_RME_MASK, 1U, ENABLE_RME) 404 405 /* FEAT_SB: Speculation barrier instruction */ 406 CREATE_FEATURE_PRESENT(feat_sb, id_aa64isar1_el1, ID_AA64ISAR1_SB_SHIFT, 407 ID_AA64ISAR1_SB_MASK, 1U) 408 409 /* FEAT_MEC: Memory Encryption Contexts */ 410 CREATE_FEATURE_FUNCS(feat_mec, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_MEC_SHIFT, 411 ID_AA64MMFR3_EL1_MEC_MASK, 1U, ENABLE_FEAT_MEC) 412 413 /* 414 * FEAT_CSV2: Cache Speculation Variant 2. This checks bit fields[56-59] 415 * of id_aa64pfr0_el1 register and can be used to check for below features: 416 * FEAT_CSV2_2: Cache Speculation Variant CSV2_2. 417 * FEAT_CSV2_3: Cache Speculation Variant CSV2_3. 418 * 0b0000 - Feature FEAT_CSV2 is not implemented. 419 * 0b0001 - Feature FEAT_CSV2 is implemented, but FEAT_CSV2_2 and FEAT_CSV2_3 420 * are not implemented. 421 * 0b0010 - Feature FEAT_CSV2_2 is implemented but FEAT_CSV2_3 is not 422 * implemented. 423 * 0b0011 - Feature FEAT_CSV2_3 is implemented. 424 */ 425 426 CREATE_FEATURE_FUNCS(feat_csv2_2, id_aa64pfr0_el1, ID_AA64PFR0_CSV2_SHIFT, 427 ID_AA64PFR0_CSV2_MASK, CSV2_2_IMPLEMENTED, ENABLE_FEAT_CSV2_2) 428 CREATE_FEATURE_FUNCS(feat_csv2_3, id_aa64pfr0_el1, ID_AA64PFR0_CSV2_SHIFT, 429 ID_AA64PFR0_CSV2_MASK, CSV2_3_IMPLEMENTED, ENABLE_FEAT_CSV2_3) 430 431 /* FEAT_SPE: Statistical Profiling Extension */ 432 CREATE_FEATURE_FUNCS(feat_spe, id_aa64dfr0_el1, ID_AA64DFR0_PMS_SHIFT, 433 ID_AA64DFR0_PMS_MASK, 1U, ENABLE_SPE_FOR_NS) 434 435 /* FEAT_SVE: Scalable Vector Extension */ 436 CREATE_FEATURE_FUNCS(feat_sve, id_aa64pfr0_el1, ID_AA64PFR0_SVE_SHIFT, 437 ID_AA64PFR0_SVE_MASK, 1U, ENABLE_SVE_FOR_NS) 438 439 /* FEAT_RAS: Reliability, Accessibility, Serviceability */ 440 CREATE_FEATURE_FUNCS(feat_ras, id_aa64pfr0_el1, ID_AA64PFR0_RAS_SHIFT, 441 ID_AA64PFR0_RAS_MASK, 1U, ENABLE_FEAT_RAS) 442 443 /* FEAT_DIT: Data Independent Timing instructions */ 444 CREATE_FEATURE_FUNCS(feat_dit, id_aa64pfr0_el1, ID_AA64PFR0_DIT_SHIFT, 445 ID_AA64PFR0_DIT_MASK, 1U, ENABLE_FEAT_DIT) 446 447 /* FEAT_SYS_REG_TRACE */ 448 CREATE_FEATURE_FUNCS(feat_sys_reg_trace, id_aa64dfr0_el1, ID_AA64DFR0_TRACEVER_SHIFT, 449 ID_AA64DFR0_TRACEVER_MASK, 1U, ENABLE_SYS_REG_TRACE_FOR_NS) 450 451 /* FEAT_TRF: TraceFilter */ 452 CREATE_FEATURE_FUNCS(feat_trf, id_aa64dfr0_el1, ID_AA64DFR0_TRACEFILT_SHIFT, 453 ID_AA64DFR0_TRACEFILT_MASK, 1U, ENABLE_TRF_FOR_NS) 454 455 /* FEAT_NV2: Enhanced Nested Virtualization */ 456 CREATE_FEATURE_FUNCS(feat_nv, id_aa64mmfr2_el1, ID_AA64MMFR2_EL1_NV_SHIFT, 457 ID_AA64MMFR2_EL1_NV_MASK, 1U, 0U) 458 CREATE_FEATURE_FUNCS(feat_nv2, id_aa64mmfr2_el1, ID_AA64MMFR2_EL1_NV_SHIFT, 459 ID_AA64MMFR2_EL1_NV_MASK, NV2_IMPLEMENTED, CTX_INCLUDE_NEVE_REGS) 460 461 /* FEAT_BRBE: Branch Record Buffer Extension */ 462 CREATE_FEATURE_FUNCS(feat_brbe, id_aa64dfr0_el1, ID_AA64DFR0_BRBE_SHIFT, 463 ID_AA64DFR0_BRBE_MASK, 1U, ENABLE_BRBE_FOR_NS) 464 465 /* FEAT_TRBE: Trace Buffer Extension */ 466 CREATE_FEATURE_FUNCS(feat_trbe, id_aa64dfr0_el1, ID_AA64DFR0_TRACEBUFFER_SHIFT, 467 ID_AA64DFR0_TRACEBUFFER_MASK, 1U, ENABLE_TRBE_FOR_NS) 468 469 /* FEAT_SME_FA64: Full A64 Instruction support in streaming SVE mode */ 470 CREATE_FEATURE_PRESENT(feat_sme_fa64, id_aa64smfr0_el1, ID_AA64SMFR0_EL1_SME_FA64_SHIFT, 471 ID_AA64SMFR0_EL1_SME_FA64_MASK, 1U) 472 473 /* FEAT_SMEx: Scalar Matrix Extension */ 474 CREATE_FEATURE_FUNCS(feat_sme, id_aa64pfr1_el1, ID_AA64PFR1_EL1_SME_SHIFT, 475 ID_AA64PFR1_EL1_SME_MASK, 1U, ENABLE_SME_FOR_NS) 476 477 CREATE_FEATURE_FUNCS(feat_sme2, id_aa64pfr1_el1, ID_AA64PFR1_EL1_SME_SHIFT, 478 ID_AA64PFR1_EL1_SME_MASK, SME2_IMPLEMENTED, ENABLE_SME2_FOR_NS) 479 480 /* FEAT_LS64_ACCDATA: */ 481 CREATE_FEATURE_FUNCS(feat_ls64_accdata, id_aa64isar1_el1, ID_AA64ISAR1_LS64_SHIFT, 482 ID_AA64ISAR1_LS64_MASK, LS64_ACCDATA_IMPLEMENTED, 483 ENABLE_FEAT_LS64_ACCDATA) 484 485 /******************************************************************************* 486 * Function to get hardware granularity support 487 ******************************************************************************/ 488 489 __attribute__((always_inline)) 490 static inline bool is_feat_tgran4K_present(void) 491 { 492 unsigned int tgranx = ISOLATE_FIELD(read_id_aa64mmfr0_el1(), 493 ID_AA64MMFR0_EL1_TGRAN4_SHIFT, ID_REG_FIELD_MASK); 494 return (tgranx < 8U); 495 } 496 497 CREATE_FEATURE_PRESENT(feat_tgran16K, id_aa64mmfr0_el1, ID_AA64MMFR0_EL1_TGRAN16_SHIFT, 498 ID_AA64MMFR0_EL1_TGRAN16_MASK, TGRAN16_IMPLEMENTED) 499 500 __attribute__((always_inline)) 501 static inline bool is_feat_tgran64K_present(void) 502 { 503 unsigned int tgranx = ISOLATE_FIELD(read_id_aa64mmfr0_el1(), 504 ID_AA64MMFR0_EL1_TGRAN64_SHIFT, ID_REG_FIELD_MASK); 505 return (tgranx < 8U); 506 } 507 508 /* FEAT_PMUV3 */ 509 CREATE_FEATURE_PRESENT(feat_pmuv3, id_aa64dfr0_el1, ID_AA64DFR0_PMUVER_SHIFT, 510 ID_AA64DFR0_PMUVER_MASK, 1U) 511 512 /* FEAT_MTPMU */ 513 __attribute__((always_inline)) 514 static inline bool is_feat_mtpmu_present(void) 515 { 516 unsigned int mtpmu = ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_MTPMU_SHIFT, 517 ID_AA64DFR0_MTPMU_MASK); 518 return (mtpmu != 0U) && (mtpmu != MTPMU_NOT_IMPLEMENTED); 519 } 520 521 CREATE_FEATURE_SUPPORTED(feat_mtpmu, is_feat_mtpmu_present, DISABLE_MTPMU) 522 523 /************************************************************************* 524 * Function to identify the presence of FEAT_GCIE (GICv5 CPU interface 525 * extension). 526 ************************************************************************/ 527 CREATE_FEATURE_FUNCS(feat_gcie, id_aa64pfr2_el1, ID_AA64PFR2_EL1_GCIE_SHIFT, 528 ID_AA64PFR2_EL1_GCIE_MASK, 1U, ENABLE_FEAT_GCIE) 529 530 #endif /* ARCH_FEATURES_H */ 531