1 /* 2 * Copyright (c) 2019-2022, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef ARCH_FEATURES_H 8 #define ARCH_FEATURES_H 9 10 #include <stdbool.h> 11 12 #include <arch_helpers.h> 13 14 static inline bool is_armv7_gentimer_present(void) 15 { 16 /* The Generic Timer is always present in an ARMv8-A implementation */ 17 return true; 18 } 19 20 static inline bool is_armv8_1_pan_present(void) 21 { 22 return ((read_id_aa64mmfr1_el1() >> ID_AA64MMFR1_EL1_PAN_SHIFT) & 23 ID_AA64MMFR1_EL1_PAN_MASK) != 0U; 24 } 25 26 static inline bool is_armv8_1_vhe_present(void) 27 { 28 return ((read_id_aa64mmfr1_el1() >> ID_AA64MMFR1_EL1_VHE_SHIFT) & 29 ID_AA64MMFR1_EL1_VHE_MASK) != 0U; 30 } 31 32 static inline bool is_armv8_2_ttcnp_present(void) 33 { 34 return ((read_id_aa64mmfr2_el1() >> ID_AA64MMFR2_EL1_CNP_SHIFT) & 35 ID_AA64MMFR2_EL1_CNP_MASK) != 0U; 36 } 37 38 static inline bool is_feat_pacqarma3_present(void) 39 { 40 uint64_t mask_id_aa64isar2 = 41 (ID_AA64ISAR2_GPA3_MASK << ID_AA64ISAR2_GPA3_SHIFT) | 42 (ID_AA64ISAR2_APA3_MASK << ID_AA64ISAR2_APA3_SHIFT); 43 44 /* If any of the fields is not zero, QARMA3 algorithm is present */ 45 return (read_id_aa64isar2_el1() & mask_id_aa64isar2) != 0U; 46 } 47 48 static inline bool is_armv8_3_pauth_present(void) 49 { 50 uint64_t mask_id_aa64isar1 = 51 (ID_AA64ISAR1_GPI_MASK << ID_AA64ISAR1_GPI_SHIFT) | 52 (ID_AA64ISAR1_GPA_MASK << ID_AA64ISAR1_GPA_SHIFT) | 53 (ID_AA64ISAR1_API_MASK << ID_AA64ISAR1_API_SHIFT) | 54 (ID_AA64ISAR1_APA_MASK << ID_AA64ISAR1_APA_SHIFT); 55 56 /* 57 * If any of the fields is not zero or QARMA3 is present, 58 * PAuth is present 59 */ 60 return ((read_id_aa64isar1_el1() & mask_id_aa64isar1) != 0U || 61 is_feat_pacqarma3_present()); 62 } 63 64 static inline bool is_armv8_4_dit_present(void) 65 { 66 return ((read_id_aa64pfr0_el1() >> ID_AA64PFR0_DIT_SHIFT) & 67 ID_AA64PFR0_DIT_MASK) == 1U; 68 } 69 70 static inline bool is_armv8_4_ttst_present(void) 71 { 72 return ((read_id_aa64mmfr2_el1() >> ID_AA64MMFR2_EL1_ST_SHIFT) & 73 ID_AA64MMFR2_EL1_ST_MASK) == 1U; 74 } 75 76 static inline bool is_armv8_5_bti_present(void) 77 { 78 return ((read_id_aa64pfr1_el1() >> ID_AA64PFR1_EL1_BT_SHIFT) & 79 ID_AA64PFR1_EL1_BT_MASK) == BTI_IMPLEMENTED; 80 } 81 82 static inline unsigned int get_armv8_5_mte_support(void) 83 { 84 return ((read_id_aa64pfr1_el1() >> ID_AA64PFR1_EL1_MTE_SHIFT) & 85 ID_AA64PFR1_EL1_MTE_MASK); 86 } 87 88 static inline bool is_armv8_4_sel2_present(void) 89 { 90 return ((read_id_aa64pfr0_el1() >> ID_AA64PFR0_SEL2_SHIFT) & 91 ID_AA64PFR0_SEL2_MASK) == 1ULL; 92 } 93 94 static inline bool is_armv8_6_twed_present(void) 95 { 96 return (((read_id_aa64mmfr1_el1() >> ID_AA64MMFR1_EL1_TWED_SHIFT) & 97 ID_AA64MMFR1_EL1_TWED_MASK) == ID_AA64MMFR1_EL1_TWED_SUPPORTED); 98 } 99 100 static inline bool is_armv8_6_fgt_present(void) 101 { 102 return ((read_id_aa64mmfr0_el1() >> ID_AA64MMFR0_EL1_FGT_SHIFT) & 103 ID_AA64MMFR0_EL1_FGT_MASK) == ID_AA64MMFR0_EL1_FGT_SUPPORTED; 104 } 105 106 static inline unsigned long int get_armv8_6_ecv_support(void) 107 { 108 return ((read_id_aa64mmfr0_el1() >> ID_AA64MMFR0_EL1_ECV_SHIFT) & 109 ID_AA64MMFR0_EL1_ECV_MASK); 110 } 111 112 static inline bool is_armv8_5_rng_present(void) 113 { 114 return ((read_id_aa64isar0_el1() >> ID_AA64ISAR0_RNDR_SHIFT) & 115 ID_AA64ISAR0_RNDR_MASK); 116 } 117 118 static inline bool is_armv8_6_feat_amuv1p1_present(void) 119 { 120 return (((read_id_aa64pfr0_el1() >> ID_AA64PFR0_AMU_SHIFT) & 121 ID_AA64PFR0_AMU_MASK) >= ID_AA64PFR0_AMU_V1P1); 122 } 123 124 /* 125 * Return MPAM version: 126 * 127 * 0x00: None Armv8.0 or later 128 * 0x01: v0.1 Armv8.4 or later 129 * 0x10: v1.0 Armv8.2 or later 130 * 0x11: v1.1 Armv8.4 or later 131 * 132 */ 133 static inline unsigned int get_mpam_version(void) 134 { 135 return (unsigned int)((((read_id_aa64pfr0_el1() >> 136 ID_AA64PFR0_MPAM_SHIFT) & ID_AA64PFR0_MPAM_MASK) << 4) | 137 ((read_id_aa64pfr1_el1() >> 138 ID_AA64PFR1_MPAM_FRAC_SHIFT) & ID_AA64PFR1_MPAM_FRAC_MASK)); 139 } 140 141 static inline bool is_feat_hcx_present(void) 142 { 143 return (((read_id_aa64mmfr1_el1() >> ID_AA64MMFR1_EL1_HCX_SHIFT) & 144 ID_AA64MMFR1_EL1_HCX_MASK) == ID_AA64MMFR1_EL1_HCX_SUPPORTED); 145 } 146 147 static inline unsigned int get_armv9_2_feat_rme_support(void) 148 { 149 /* 150 * Return the RME version, zero if not supported. This function can be 151 * used as both an integer value for the RME version or compared to zero 152 * to detect RME presence. 153 */ 154 return (unsigned int)(read_id_aa64pfr0_el1() >> 155 ID_AA64PFR0_FEAT_RME_SHIFT) & ID_AA64PFR0_FEAT_RME_MASK; 156 } 157 158 /********************************************************************************* 159 * Function to identify the presence of FEAT_SB (Speculation Barrier Instruction) 160 ********************************************************************************/ 161 static inline bool is_armv8_0_feat_sb_present(void) 162 { 163 return (((read_id_aa64isar1_el1() >> ID_AA64ISAR1_SB_SHIFT) & 164 ID_AA64ISAR1_SB_MASK) == ID_AA64ISAR1_SB_SUPPORTED); 165 } 166 167 /********************************************************************************* 168 * Function to identify the presence of FEAT_CSV2_2 (Cache Speculation Variant 2) 169 ********************************************************************************/ 170 static inline bool is_armv8_0_feat_csv2_2_present(void) 171 { 172 return (((read_id_aa64pfr0_el1() >> ID_AA64PFR0_CSV2_SHIFT) & 173 ID_AA64PFR0_CSV2_MASK) == ID_AA64PFR0_CSV2_2_SUPPORTED); 174 } 175 176 /********************************************************************************** 177 * Function to identify the presence of FEAT_SPE (Statistical Profiling Extension) 178 *********************************************************************************/ 179 static inline bool is_armv8_2_feat_spe_present(void) 180 { 181 return (((read_id_aa64dfr0_el1() >> ID_AA64DFR0_PMS_SHIFT) & 182 ID_AA64DFR0_PMS_MASK) != ID_AA64DFR0_SPE_NOT_SUPPORTED); 183 } 184 185 /******************************************************************************* 186 * Function to identify the presence of FEAT_SVE (Scalable Vector Extension) 187 ******************************************************************************/ 188 static inline bool is_armv8_2_feat_sve_present(void) 189 { 190 return (((read_id_aa64pfr0_el1() >> ID_AA64PFR0_SVE_SHIFT) & 191 ID_AA64PFR0_SVE_MASK) == ID_AA64PFR0_SVE_SUPPORTED); 192 } 193 194 /******************************************************************************* 195 * Function to identify the presence of FEAT_RAS (Reliability,Availability, 196 * and Serviceability Extension) 197 ******************************************************************************/ 198 static inline bool is_armv8_2_feat_ras_present(void) 199 { 200 return (((read_id_aa64pfr0_el1() >> ID_AA64PFR0_RAS_SHIFT) & 201 ID_AA64PFR0_RAS_MASK) != ID_AA64PFR0_RAS_NOT_SUPPORTED); 202 } 203 204 /************************************************************************** 205 * Function to identify the presence of FEAT_DIT (Data Independent Timing) 206 *************************************************************************/ 207 static inline bool is_armv8_4_feat_dit_present(void) 208 { 209 return (((read_id_aa64pfr0_el1() >> ID_AA64PFR0_DIT_SHIFT) & 210 ID_AA64PFR0_DIT_MASK) == ID_AA64PFR0_DIT_SUPPORTED); 211 } 212 213 /************************************************************************* 214 * Function to identify the presence of FEAT_TRF (TraceLift) 215 ************************************************************************/ 216 static inline bool is_arm8_4_feat_trf_present(void) 217 { 218 return (((read_id_aa64dfr0_el1() >> ID_AA64DFR0_TRACEFILT_SHIFT) & 219 ID_AA64DFR0_TRACEFILT_MASK) == ID_AA64DFR0_TRACEFILT_SUPPORTED); 220 } 221 222 /******************************************************************************* 223 * Function to identify the presence of FEAT_AMUv1 (Activity Monitors- 224 * Extension v1) 225 ******************************************************************************/ 226 static inline bool is_armv8_4_feat_amuv1_present(void) 227 { 228 return (((read_id_aa64pfr0_el1() >> ID_AA64PFR0_AMU_SHIFT) & 229 ID_AA64PFR0_AMU_MASK) >= ID_AA64PFR0_AMU_V1); 230 } 231 232 /******************************************************************************** 233 * Function to identify the presence of FEAT_NV2 (Enhanced Nested Virtualization 234 * Support) 235 *******************************************************************************/ 236 static inline unsigned int get_armv8_4_feat_nv_support(void) 237 { 238 return (((read_id_aa64mmfr2_el1() >> ID_AA64MMFR2_EL1_NV_SHIFT) & 239 ID_AA64MMFR2_EL1_NV_MASK)); 240 } 241 242 /******************************************************************************* 243 * Function to identify the presence of FEAT_BRBE (Branch Record Buffer 244 * Extension) 245 ******************************************************************************/ 246 static inline bool is_feat_brbe_present(void) 247 { 248 return (((read_id_aa64dfr0_el1() >> ID_AA64DFR0_BRBE_SHIFT) & 249 ID_AA64DFR0_BRBE_MASK) == ID_AA64DFR0_BRBE_SUPPORTED); 250 } 251 252 /******************************************************************************* 253 * Function to identify the presence of FEAT_TRBE (Trace Buffer Extension) 254 ******************************************************************************/ 255 static inline bool is_feat_trbe_present(void) 256 { 257 return (((read_id_aa64dfr0_el1() >> ID_AA64DFR0_TRACEBUFFER_SHIFT) & 258 ID_AA64DFR0_TRACEBUFFER_MASK) == ID_AA64DFR0_TRACEBUFFER_SUPPORTED); 259 } 260 261 #endif /* ARCH_FEATURES_H */ 262