1 /* 2 * Copyright (c) 2019-2026, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef ARCH_FEATURES_H 8 #define ARCH_FEATURES_H 9 10 #include <stdbool.h> 11 12 #include <arch_helpers.h> 13 #include <common/feat_detect.h> 14 #include <lib/cpus/errata.h> 15 #include <lib/el3_runtime/context_mgmt.h> 16 #include <lib/el3_runtime/cpu_data.h> 17 18 #if ENABLE_RME 19 #define FEAT_ENABLE_ALL_WORLDS \ 20 ((1u << CPU_CONTEXT_SECURE) | \ 21 (1u << CPU_CONTEXT_NS) | \ 22 (1u << CPU_CONTEXT_REALM)) 23 #define FEAT_ENABLE_REALM (1 << CPU_CONTEXT_REALM) 24 #else 25 #define FEAT_ENABLE_ALL_WORLDS \ 26 ((1u << CPU_CONTEXT_SECURE) | \ 27 (1u << CPU_CONTEXT_NS)) 28 #define FEAT_ENABLE_REALM U(0) 29 #endif 30 31 #define FEAT_ENABLE_SECURE (1 << CPU_CONTEXT_SECURE) 32 #define FEAT_ENABLE_NS (1 << CPU_CONTEXT_NS) 33 34 #define ISOLATE_FIELD(reg, feat, mask) \ 35 ((unsigned int)(((reg) >> (feat)) & mask)) 36 37 #define SHOULD_ID_FIELD_DISABLE(guard, enabled_worlds, world) \ 38 (((guard) == 0U) || ((((enabled_worlds) >> (world)) & 1U) == 0U)) 39 40 41 #define CREATE_FEATURE_SUPPORTED(name, read_func, guard) \ 42 __attribute__((always_inline)) \ 43 static inline bool is_ ## name ## _supported(void) \ 44 { \ 45 if ((guard) == FEAT_STATE_DISABLED) { \ 46 return false; \ 47 } \ 48 if ((guard) == FEAT_STATE_ALWAYS) { \ 49 return true; \ 50 } \ 51 return read_func(); \ 52 } 53 54 /* 55 * CREATE_IDREG_UPDATE and CREATE_PERCPU_IDREG_UPDATE are two macros that 56 * generate the update_feat_abc_idreg_field() function based on how its 57 * corresponding ID register is cached. 58 * The function disables ID register fields related to a feature if the build 59 * flag for that feature is 0 or if the feature should be disabled for that 60 * world. If the particular field has to be disabled, its field in the cached 61 * ID register is set to 0. 62 * 63 * Note: For most ID register fields, a value of 0 represents 64 * the Unimplemented state, and hence we use this macro to show features 65 * disabled in EL3 as unimplemented to lower ELs. However, certain feature's 66 * ID Register fields (like ID_AA64MMFR4_EL1.E2H0) deviate from this convention, 67 * where 0 does not represent Unimplemented. 68 * For those features, a custom update_feat_abc_idreg_field() 69 * needs to be created. This custom function should set the field to the 70 * feature's unimplemented state value if the feature is disabled in EL3. 71 * 72 * For example: 73 * 74 * __attribute__((always_inline)) 75 * static inline void update_feat_abc_idreg_field(size_t security_state) 76 * { 77 * if (SHOULD_ID_FIELD_DISABLE(guard, enabled_worlds, security_state)) { 78 * per_world_context_t *per_world_ctx = 79 * &per_world_context[security_state]; 80 * perworld_idregs_t *perworld_idregs = &(per_world_ctx->idregs); 81 * 82 * perworld_idregs->idreg &= 83 * ~((u_register_t)mask << idfield); 84 * perworld_idregs->idreg |= 85 * (((u_register_t)<unimplemented state value> & mask) << idfield); 86 * } 87 * } 88 */ 89 90 #if (ENABLE_FEAT_IDTE3 && IMAGE_BL31) 91 #define CREATE_IDREG_UPDATE(name, idreg, idfield, mask, guard, enabled_worlds) \ 92 __attribute__((always_inline)) \ 93 static inline void update_ ## name ## _idreg_field(size_t security_state) \ 94 { \ 95 if (SHOULD_ID_FIELD_DISABLE(guard, enabled_worlds, security_state)) { \ 96 per_world_context_t *per_world_ctx = \ 97 &per_world_context[security_state]; \ 98 perworld_idregs_t *perworld_idregs = &(per_world_ctx->idregs); \ 99 perworld_idregs->idreg &= ~((u_register_t)mask << idfield); \ 100 } \ 101 } 102 #define CREATE_PERCPU_IDREG_UPDATE(name, idreg, idfield, mask, guard, \ 103 enabled_worlds) \ 104 __attribute__((always_inline)) \ 105 static inline void update_ ## name ## _idreg_field(size_t security_state) \ 106 { \ 107 if (SHOULD_ID_FIELD_DISABLE(guard, enabled_worlds, security_state)) { \ 108 percpu_idregs_t *percpu_idregs = \ 109 &(get_cpu_data(idregs[security_state]));\ 110 percpu_idregs->idreg &= ~((u_register_t)mask << idfield); \ 111 } \ 112 } 113 #else 114 #define CREATE_IDREG_UPDATE(name, idreg, idfield, mask, guard, enabled_worlds) 115 #define CREATE_PERCPU_IDREG_UPDATE(name, idreg, idfield, mask, guard, \ 116 enabled_worlds) 117 #endif 118 119 #define _CREATE_FEATURE_PRESENT(name, idreg, idfield, mask, idval) \ 120 __attribute__((always_inline)) \ 121 static inline bool is_ ## name ## _present(void) \ 122 { \ 123 return (ISOLATE_FIELD(read_ ## idreg(), idfield, mask) >= idval) \ 124 ? true : false; \ 125 } 126 127 #define CREATE_FEATURE_PRESENT(name, idreg, idfield, mask, idval, \ 128 enabled_worlds) \ 129 _CREATE_FEATURE_PRESENT(name, idreg, idfield, mask, idval) \ 130 CREATE_IDREG_UPDATE(name, idreg, idfield, mask, 1U, enabled_worlds) 131 132 #define CREATE_PERCPU_FEATURE_PRESENT(name, idreg, idfield, mask, idval, \ 133 enabled_worlds) \ 134 _CREATE_FEATURE_PRESENT(name, idreg, idfield, mask, idval) \ 135 CREATE_PERCPU_IDREG_UPDATE(name, idreg, idfield, mask, 1U, \ 136 enabled_worlds) 137 138 #define CREATE_FEATURE_FUNCS(name, idreg, idfield, mask, idval, guard, \ 139 enabled_worlds) \ 140 CREATE_FEATURE_PRESENT(name, idreg, idfield, mask, idval, \ 141 enabled_worlds) \ 142 CREATE_FEATURE_SUPPORTED(name, is_ ## name ## _present, guard) 143 144 #define CREATE_PERCPU_FEATURE_FUNCS(name, idreg, idfield, mask, idval, guard, \ 145 enabled_worlds) \ 146 CREATE_PERCPU_FEATURE_PRESENT(name, idreg, idfield, mask, idval, \ 147 enabled_worlds) \ 148 CREATE_FEATURE_SUPPORTED(name, is_ ## name ## _present, guard) 149 150 __attribute__((always_inline)) 151 static inline bool is_armv7_gentimer_present(void) 152 { 153 /* The Generic Timer is always present in an ARMv8-A implementation */ 154 return true; 155 } 156 157 /* FEAT_PAN: Privileged access never */ 158 CREATE_FEATURE_FUNCS(feat_pan, id_aa64mmfr1_el1, ID_AA64MMFR1_EL1_PAN_SHIFT, 159 ID_AA64MMFR1_EL1_PAN_MASK, 1U, ENABLE_FEAT_PAN, 160 FEAT_ENABLE_ALL_WORLDS) 161 162 /* FEAT_VHE: Virtualization Host Extensions */ 163 CREATE_FEATURE_FUNCS(feat_vhe, id_aa64mmfr1_el1, ID_AA64MMFR1_EL1_VHE_SHIFT, 164 ID_AA64MMFR1_EL1_VHE_MASK, 1U, ENABLE_FEAT_VHE, 165 FEAT_ENABLE_ALL_WORLDS) 166 167 /* FEAT_TTCNP: Translation table common not private */ 168 CREATE_FEATURE_PRESENT(feat_ttcnp, id_aa64mmfr2_el1, ID_AA64MMFR2_EL1_CNP_SHIFT, 169 ID_AA64MMFR2_EL1_CNP_MASK, 1U, 170 FEAT_ENABLE_ALL_WORLDS) 171 172 /* FEAT_UAO: User access override */ 173 CREATE_FEATURE_PRESENT(feat_uao, id_aa64mmfr2_el1, ID_AA64MMFR2_EL1_UAO_SHIFT, 174 ID_AA64MMFR2_EL1_UAO_MASK, 1U, 175 FEAT_ENABLE_ALL_WORLDS) 176 177 /* If any of the fields is not zero, QARMA3 algorithm is present */ 178 CREATE_FEATURE_PRESENT(feat_pacqarma3, id_aa64isar2_el1, 0, 179 ((ID_AA64ISAR2_GPA3_MASK << ID_AA64ISAR2_GPA3_SHIFT) | 180 (ID_AA64ISAR2_APA3_MASK << ID_AA64ISAR2_APA3_SHIFT)), 1U, 181 FEAT_ENABLE_ALL_WORLDS) 182 183 /* FEAT_PAUTH: Pointer Authentication */ 184 __attribute__((always_inline)) 185 static inline bool is_feat_pauth_present(void) 186 { 187 uint64_t mask_id_aa64isar1 = 188 (ID_AA64ISAR1_GPI_MASK << ID_AA64ISAR1_GPI_SHIFT) | 189 (ID_AA64ISAR1_GPA_MASK << ID_AA64ISAR1_GPA_SHIFT) | 190 (ID_AA64ISAR1_API_MASK << ID_AA64ISAR1_API_SHIFT) | 191 (ID_AA64ISAR1_APA_MASK << ID_AA64ISAR1_APA_SHIFT); 192 193 /* 194 * If any of the fields is not zero or QARMA3 is present, 195 * PAuth is present 196 */ 197 return ((read_id_aa64isar1_el1() & mask_id_aa64isar1) != 0U || 198 is_feat_pacqarma3_present()); 199 } 200 CREATE_FEATURE_SUPPORTED(feat_pauth, is_feat_pauth_present, ENABLE_PAUTH) 201 CREATE_FEATURE_SUPPORTED(ctx_pauth, is_feat_pauth_present, CTX_INCLUDE_PAUTH_REGS) 202 203 /* FEAT_CRYPTO: SIMD Crypto Extensions */ 204 __attribute__((always_inline)) 205 static inline bool is_feat_crypto_present(void) 206 { 207 uint64_t mask_id_aa64isar0 = 208 (ID_AA64ISAR0_AES_MASK << ID_AA64ISAR0_AES_SHIFT) | 209 (ID_AA64ISAR0_SHA1_MASK << ID_AA64ISAR0_SHA1_SHIFT) | 210 (ID_AA64ISAR0_SHA2_MASK << ID_AA64ISAR0_SHA2_SHIFT); 211 212 /* 213 * Check if AES, SHA1, SHA2 extension presents. 214 */ 215 return ((read_id_aa64isar0_el1() & mask_id_aa64isar0) != 0U); 216 } 217 CREATE_FEATURE_SUPPORTED(feat_crypto, is_feat_crypto_present, ENABLE_FEAT_CRYPTO) 218 219 #if (ENABLE_FEAT_IDTE3 && IMAGE_BL31) 220 __attribute__((always_inline)) 221 static inline void update_feat_pauth_idreg_field(size_t security_state) 222 { 223 uint64_t mask_id_aa64isar1 = 224 (ID_AA64ISAR1_GPI_MASK << ID_AA64ISAR1_GPI_SHIFT) | 225 (ID_AA64ISAR1_GPA_MASK << ID_AA64ISAR1_GPA_SHIFT) | 226 (ID_AA64ISAR1_API_MASK << ID_AA64ISAR1_API_SHIFT) | 227 (ID_AA64ISAR1_APA_MASK << ID_AA64ISAR1_APA_SHIFT); 228 229 uint64_t mask_id_aa64isar2 = 230 (ID_AA64ISAR2_APA3_MASK << ID_AA64ISAR2_APA3_MASK) | 231 (ID_AA64ISAR2_GPA3_MASK << ID_AA64ISAR2_GPA3_MASK); 232 233 per_world_context_t *per_world_ctx = &per_world_context[security_state]; 234 perworld_idregs_t *perworld_idregs = 235 &(per_world_ctx->idregs); 236 237 if ((SHOULD_ID_FIELD_DISABLE(ENABLE_PAUTH, FEAT_ENABLE_NS, 238 security_state)) && 239 (SHOULD_ID_FIELD_DISABLE(CTX_INCLUDE_PAUTH_REGS, 240 FEAT_ENABLE_ALL_WORLDS, 241 security_state))) { 242 perworld_idregs->id_aa64isar1_el1 &= ~(mask_id_aa64isar1); 243 perworld_idregs->id_aa64isar2_el1 &= ~(mask_id_aa64isar2); 244 } 245 } 246 #endif 247 248 /* 249 * FEAT_PAUTH_LR 250 * This feature has a non-standard discovery method so define this function 251 * manually then call use the CREATE_FEATURE_SUPPORTED macro with it. This 252 * feature is enabled with ENABLE_PAUTH when present. 253 */ 254 __attribute__((always_inline)) 255 static inline bool is_feat_pauth_lr_present(void) 256 { 257 /* 258 * FEAT_PAUTH_LR support is indicated by up to 3 fields, if one or more 259 * of these is 0b0110 then the feature is present. 260 * 1) id_aa64isr1_el1.api 261 * 2) id_aa64isr1_el1.apa 262 * 3) id_aa64isr2_el1.apa3 263 */ 264 if (ISOLATE_FIELD(read_id_aa64isar1_el1(), ID_AA64ISAR1_API_SHIFT, ID_AA64ISAR1_API_MASK) == 0b0110) { 265 return true; 266 } 267 if (ISOLATE_FIELD(read_id_aa64isar1_el1(), ID_AA64ISAR1_APA_SHIFT, ID_AA64ISAR1_APA_MASK) == 0b0110) { 268 return true; 269 } 270 if (ISOLATE_FIELD(read_id_aa64isar2_el1(), ID_AA64ISAR2_APA3_SHIFT, ID_AA64ISAR2_APA3_MASK) == 0b0110) { 271 return true; 272 } 273 return false; 274 } 275 CREATE_FEATURE_SUPPORTED(feat_pauth_lr, is_feat_pauth_lr_present, ENABLE_FEAT_PAUTH_LR) 276 277 /* FEAT_TTST: Small translation tables */ 278 CREATE_FEATURE_PRESENT(feat_ttst, id_aa64mmfr2_el1, ID_AA64MMFR2_EL1_ST_SHIFT, 279 ID_AA64MMFR2_EL1_ST_MASK, 1U, 280 FEAT_ENABLE_ALL_WORLDS) 281 282 /* FEAT_BTI: Branch target identification */ 283 CREATE_FEATURE_FUNCS(feat_bti, id_aa64pfr1_el1, ID_AA64PFR1_EL1_BT_SHIFT, 284 ID_AA64PFR1_EL1_BT_MASK, BTI_IMPLEMENTED, ENABLE_BTI, 285 FEAT_ENABLE_ALL_WORLDS) 286 287 /* FEAT_MTE2: Memory tagging extension */ 288 CREATE_FEATURE_FUNCS(feat_mte2, id_aa64pfr1_el1, ID_AA64PFR1_EL1_MTE_SHIFT, 289 ID_AA64PFR1_EL1_MTE_MASK, MTE_IMPLEMENTED_ELX, ENABLE_FEAT_MTE2, 290 FEAT_ENABLE_SECURE | FEAT_ENABLE_NS) 291 292 /* FEAT_SSBS: Speculative store bypass safe */ 293 CREATE_FEATURE_PRESENT(feat_ssbs, id_aa64pfr1_el1, ID_AA64PFR1_EL1_SSBS_SHIFT, 294 ID_AA64PFR1_EL1_SSBS_MASK, 1U, 295 FEAT_ENABLE_ALL_WORLDS) 296 297 /* FEAT_NMI: Non-maskable interrupts */ 298 CREATE_FEATURE_PRESENT(feat_nmi, id_aa64pfr1_el1, ID_AA64PFR1_EL1_NMI_SHIFT, 299 ID_AA64PFR1_EL1_NMI_MASK, NMI_IMPLEMENTED, 300 FEAT_ENABLE_ALL_WORLDS) 301 302 /* FEAT_EBEP */ 303 CREATE_PERCPU_FEATURE_FUNCS(feat_ebep, id_aa64dfr1_el1, ID_AA64DFR1_EBEP_SHIFT, 304 ID_AA64DFR1_EBEP_MASK, 1U, ENABLE_FEAT_EBEP, 305 FEAT_ENABLE_ALL_WORLDS) 306 307 /* FEAT_SEBEP */ 308 CREATE_PERCPU_FEATURE_PRESENT(feat_sebep, id_aa64dfr0_el1, ID_AA64DFR0_SEBEP_SHIFT, 309 ID_AA64DFR0_SEBEP_MASK, SEBEP_IMPLEMENTED, 310 FEAT_ENABLE_ALL_WORLDS) 311 312 /* FEAT_SEL2: Secure EL2 */ 313 CREATE_FEATURE_FUNCS(feat_sel2, id_aa64pfr0_el1, ID_AA64PFR0_SEL2_SHIFT, 314 ID_AA64PFR0_SEL2_MASK, 1U, ENABLE_FEAT_SEL2, 315 FEAT_ENABLE_ALL_WORLDS) 316 317 /* FEAT_TWED: Delayed trapping of WFE */ 318 CREATE_FEATURE_FUNCS(feat_twed, id_aa64mmfr1_el1, ID_AA64MMFR1_EL1_TWED_SHIFT, 319 ID_AA64MMFR1_EL1_TWED_MASK, 1U, ENABLE_FEAT_TWED, 320 FEAT_ENABLE_ALL_WORLDS) 321 322 /* FEAT_FGT: Fine-grained traps */ 323 CREATE_FEATURE_FUNCS(feat_fgt, id_aa64mmfr0_el1, ID_AA64MMFR0_EL1_FGT_SHIFT, 324 ID_AA64MMFR0_EL1_FGT_MASK, 1U, ENABLE_FEAT_FGT, 325 FEAT_ENABLE_ALL_WORLDS) 326 327 /* FEAT_FGT2: Fine-grained traps extended */ 328 CREATE_FEATURE_FUNCS(feat_fgt2, id_aa64mmfr0_el1, ID_AA64MMFR0_EL1_FGT_SHIFT, 329 ID_AA64MMFR0_EL1_FGT_MASK, FGT2_IMPLEMENTED, ENABLE_FEAT_FGT2, 330 FEAT_ENABLE_ALL_WORLDS) 331 332 /* FEAT_FGWTE3: Fine-grained write traps EL3 */ 333 CREATE_FEATURE_FUNCS(feat_fgwte3, id_aa64mmfr4_el1, ID_AA64MMFR4_EL1_FGWTE3_SHIFT, 334 ID_AA64MMFR4_EL1_FGWTE3_MASK, FGWTE3_IMPLEMENTED, 335 ENABLE_FEAT_FGWTE3, FEAT_ENABLE_ALL_WORLDS) 336 337 /* FEAT_ECV: Enhanced Counter Virtualization */ 338 CREATE_FEATURE_FUNCS(feat_ecv, id_aa64mmfr0_el1, ID_AA64MMFR0_EL1_ECV_SHIFT, 339 ID_AA64MMFR0_EL1_ECV_MASK, 1U, ENABLE_FEAT_ECV, 340 FEAT_ENABLE_ALL_WORLDS) 341 CREATE_FEATURE_FUNCS(feat_ecv_v2, id_aa64mmfr0_el1, ID_AA64MMFR0_EL1_ECV_SHIFT, 342 ID_AA64MMFR0_EL1_ECV_MASK, ID_AA64MMFR0_EL1_ECV_SELF_SYNCH, 343 ENABLE_FEAT_ECV, FEAT_ENABLE_ALL_WORLDS) 344 345 /* FEAT_RNG: Random number generator */ 346 CREATE_FEATURE_FUNCS(feat_rng, id_aa64isar0_el1, ID_AA64ISAR0_RNDR_SHIFT, 347 ID_AA64ISAR0_RNDR_MASK, 1U, ENABLE_FEAT_RNG, 348 FEAT_ENABLE_ALL_WORLDS) 349 350 /* FEAT_TCR2: Support TCR2_ELx regs */ 351 CREATE_FEATURE_FUNCS(feat_tcr2, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_TCRX_SHIFT, 352 ID_AA64MMFR3_EL1_TCRX_MASK, 1U, ENABLE_FEAT_TCR2, 353 FEAT_ENABLE_ALL_WORLDS) 354 355 /* FEAT_S2POE */ 356 CREATE_FEATURE_FUNCS(feat_s2poe, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_S2POE_SHIFT, 357 ID_AA64MMFR3_EL1_S2POE_MASK, 1U, ENABLE_FEAT_S2POE, 358 FEAT_ENABLE_ALL_WORLDS) 359 360 /* FEAT_S1POE */ 361 CREATE_FEATURE_FUNCS(feat_s1poe, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_S1POE_SHIFT, 362 ID_AA64MMFR3_EL1_S1POE_MASK, 1U, ENABLE_FEAT_S1POE, 363 FEAT_ENABLE_ALL_WORLDS) 364 365 __attribute__((always_inline)) 366 static inline bool is_feat_sxpoe_supported(void) 367 { 368 return is_feat_s1poe_supported() || is_feat_s2poe_supported(); 369 } 370 371 /* FEAT_S2PIE */ 372 CREATE_FEATURE_FUNCS(feat_s2pie, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_S2PIE_SHIFT, 373 ID_AA64MMFR3_EL1_S2PIE_MASK, 1U, ENABLE_FEAT_S2PIE, 374 FEAT_ENABLE_ALL_WORLDS) 375 376 /* FEAT_S1PIE */ 377 CREATE_FEATURE_FUNCS(feat_s1pie, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_S1PIE_SHIFT, 378 ID_AA64MMFR3_EL1_S1PIE_MASK, 1U, ENABLE_FEAT_S1PIE, 379 FEAT_ENABLE_ALL_WORLDS) 380 381 /* FEAT_THE: Translation Hardening Extension */ 382 CREATE_FEATURE_FUNCS(feat_the, id_aa64pfr1_el1, ID_AA64PFR1_EL1_THE_SHIFT, 383 ID_AA64PFR1_EL1_THE_MASK, THE_IMPLEMENTED, ENABLE_FEAT_THE, 384 FEAT_ENABLE_NS) 385 386 /* FEAT_SCTLR2 */ 387 CREATE_FEATURE_FUNCS(feat_sctlr2, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_SCTLR2_SHIFT, 388 ID_AA64MMFR3_EL1_SCTLR2_MASK, SCTLR2_IMPLEMENTED, 389 ENABLE_FEAT_SCTLR2, 390 FEAT_ENABLE_NS | FEAT_ENABLE_REALM) 391 392 /* FEAT_D128 */ 393 CREATE_FEATURE_FUNCS(feat_d128, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_D128_SHIFT, 394 ID_AA64MMFR3_EL1_D128_MASK, D128_IMPLEMENTED, 395 ENABLE_FEAT_D128, FEAT_ENABLE_NS | FEAT_ENABLE_REALM) 396 397 /* FEAT_RME_GPC2 */ 398 _CREATE_FEATURE_PRESENT(feat_rme_gpc2, id_aa64pfr0_el1, 399 ID_AA64PFR0_FEAT_RME_SHIFT, ID_AA64PFR0_FEAT_RME_MASK, 400 RME_GPC2_IMPLEMENTED) 401 402 /* FEAT_RME_GDI */ 403 CREATE_FEATURE_FUNCS(feat_rme_gdi, id_aa64mmfr4_el1, 404 ID_AA64MMFR4_EL1_RME_GDI_SHIFT, 405 ID_AA64MMFR4_EL1_RME_GDI_MASK, RME_GDI_IMPLEMENTED, 406 ENABLE_FEAT_RME_GDI, FEAT_ENABLE_ALL_WORLDS) 407 408 /* FEAT_FPMR */ 409 CREATE_FEATURE_FUNCS(feat_fpmr, id_aa64pfr2_el1, ID_AA64PFR2_EL1_FPMR_SHIFT, 410 ID_AA64PFR2_EL1_FPMR_MASK, FPMR_IMPLEMENTED, 411 ENABLE_FEAT_FPMR, FEAT_ENABLE_NS) 412 /* FEAT_MOPS */ 413 CREATE_FEATURE_FUNCS(feat_mops, id_aa64isar2_el1, ID_AA64ISAR2_EL1_MOPS_SHIFT, 414 ID_AA64ISAR2_EL1_MOPS_MASK, MOPS_IMPLEMENTED, 415 ENABLE_FEAT_MOPS, FEAT_ENABLE_ALL_WORLDS) 416 417 __attribute__((always_inline)) 418 static inline bool is_feat_sxpie_supported(void) 419 { 420 return is_feat_s1pie_supported() || is_feat_s2pie_supported(); 421 } 422 423 /* FEAT_GCS: Guarded Control Stack */ 424 CREATE_FEATURE_FUNCS(feat_gcs, id_aa64pfr1_el1, ID_AA64PFR1_EL1_GCS_SHIFT, 425 ID_AA64PFR1_EL1_GCS_MASK, 1U, ENABLE_FEAT_GCS, 426 FEAT_ENABLE_ALL_WORLDS) 427 428 /* FEAT_AMU: Activity Monitors Extension */ 429 CREATE_FEATURE_FUNCS(feat_amu, id_aa64pfr0_el1, ID_AA64PFR0_AMU_SHIFT, 430 ID_AA64PFR0_AMU_MASK, 1U, ENABLE_FEAT_AMU, 431 FEAT_ENABLE_NS) 432 433 /* Auxiliary counters for FEAT_AMU */ 434 _CREATE_FEATURE_PRESENT(feat_amu_aux, amcfgr_el0, 435 AMCFGR_EL0_NCG_SHIFT, AMCFGR_EL0_NCG_MASK, 1U) 436 437 CREATE_FEATURE_SUPPORTED(feat_amu_aux, is_feat_amu_aux_present, 438 ENABLE_AMU_AUXILIARY_COUNTERS) 439 440 /* FEAT_AMUV1P1: AMU Extension v1.1 */ 441 CREATE_FEATURE_FUNCS(feat_amuv1p1, id_aa64pfr0_el1, ID_AA64PFR0_AMU_SHIFT, 442 ID_AA64PFR0_AMU_MASK, ID_AA64PFR0_AMU_V1P1, ENABLE_FEAT_AMUv1p1, 443 FEAT_ENABLE_NS) 444 445 /* 446 * Return MPAM version: 447 * 448 * 0x00: None Armv8.0 or later 449 * 0x01: v0.1 Armv8.4 or later 450 * 0x10: v1.0 Armv8.2 or later 451 * 0x11: v1.1 Armv8.4 or later 452 * 453 */ 454 __attribute__((always_inline)) 455 static inline bool is_feat_mpam_present(void) 456 { 457 unsigned int ret = (unsigned int)((((read_id_aa64pfr0_el1() >> 458 ID_AA64PFR0_MPAM_SHIFT) & ID_AA64PFR0_MPAM_MASK) << 4) | 459 ((read_id_aa64pfr1_el1() >> ID_AA64PFR1_MPAM_FRAC_SHIFT) 460 & ID_AA64PFR1_MPAM_FRAC_MASK)); 461 return ret; 462 } 463 464 CREATE_FEATURE_SUPPORTED(feat_mpam, is_feat_mpam_present, ENABLE_FEAT_MPAM) 465 466 467 #if (ENABLE_FEAT_IDTE3 && IMAGE_BL31) 468 __attribute__((always_inline)) 469 static inline void update_feat_mpam_idreg_field(size_t security_state) 470 { 471 if (SHOULD_ID_FIELD_DISABLE(ENABLE_FEAT_MPAM, 472 FEAT_ENABLE_NS | FEAT_ENABLE_REALM, security_state)) { 473 per_world_context_t *per_world_ctx = 474 &per_world_context[security_state]; 475 perworld_idregs_t *perworld_idregs = 476 &(per_world_ctx->idregs); 477 478 perworld_idregs->id_aa64pfr0_el1 &= 479 ~((u_register_t)ID_AA64PFR0_MPAM_MASK 480 << ID_AA64PFR0_MPAM_SHIFT); 481 482 perworld_idregs->id_aa64pfr1_el1 &= 483 ~((u_register_t)ID_AA64PFR1_MPAM_FRAC_MASK 484 << ID_AA64PFR1_MPAM_FRAC_SHIFT); 485 } 486 } 487 #endif 488 489 /* FEAT_MPAM_PE_BW_CTRL: MPAM PE-side bandwidth controls */ 490 __attribute__((always_inline)) 491 static inline bool is_feat_mpam_pe_bw_ctrl_present(void) 492 { 493 if (is_feat_mpam_present()) { 494 return ((unsigned long long)(read_mpamidr_el1() & 495 MPAMIDR_HAS_BW_CTRL_BIT) != 0U); 496 } 497 return false; 498 } 499 500 CREATE_FEATURE_SUPPORTED(feat_mpam_pe_bw_ctrl, is_feat_mpam_pe_bw_ctrl_present, 501 ENABLE_FEAT_MPAM_PE_BW_CTRL) 502 503 /* 504 * FEAT_DebugV8P9: Debug extension. This function checks the field 3:0 of 505 * ID_AA64DFR0 Aarch64 Debug Feature Register 0 for the version of 506 * Feat_Debug supported. The value of the field determines feature presence 507 * 508 * 0b0110 - Arm v8.0 debug 509 * 0b0111 - Arm v8.0 debug architecture with Virtualization host extensions 510 * 0x1000 - FEAT_Debugv8p2 is supported 511 * 0x1001 - FEAT_Debugv8p4 is supported 512 * 0x1010 - FEAT_Debugv8p8 is supported 513 * 0x1011 - FEAT_Debugv8p9 is supported 514 * 515 */ 516 CREATE_PERCPU_FEATURE_FUNCS(feat_debugv8p9, id_aa64dfr0_el1, 517 ID_AA64DFR0_DEBUGVER_SHIFT, ID_AA64DFR0_DEBUGVER_MASK, 518 DEBUGVER_V8P9_IMPLEMENTED, ENABLE_FEAT_DEBUGV8P9, 519 FEAT_ENABLE_NS | FEAT_ENABLE_REALM) 520 521 /* FEAT_HCX: Extended Hypervisor Configuration Register */ 522 CREATE_FEATURE_FUNCS(feat_hcx, id_aa64mmfr1_el1, ID_AA64MMFR1_EL1_HCX_SHIFT, 523 ID_AA64MMFR1_EL1_HCX_MASK, 1U, ENABLE_FEAT_HCX, 524 FEAT_ENABLE_ALL_WORLDS) 525 526 /* FEAT_RNG_TRAP: Trapping support */ 527 CREATE_FEATURE_FUNCS(feat_rng_trap, id_aa64pfr1_el1, ID_AA64PFR1_EL1_RNDR_TRAP_SHIFT, 528 ID_AA64PFR1_EL1_RNDR_TRAP_MASK, RNG_TRAP_IMPLEMENTED, ENABLE_FEAT_RNG_TRAP, 529 FEAT_ENABLE_ALL_WORLDS) 530 531 /* Return the RME version, zero if not supported. */ 532 _CREATE_FEATURE_PRESENT(feat_rme, id_aa64pfr0_el1, 533 ID_AA64PFR0_FEAT_RME_SHIFT, ID_AA64PFR0_FEAT_RME_MASK, 1U) 534 535 CREATE_FEATURE_SUPPORTED(feat_rme, is_feat_rme_present, ENABLE_RME) 536 537 /* FEAT_SB: Speculation barrier instruction */ 538 CREATE_FEATURE_PRESENT(feat_sb, id_aa64isar1_el1, ID_AA64ISAR1_SB_SHIFT, 539 ID_AA64ISAR1_SB_MASK, 1U, 540 FEAT_ENABLE_ALL_WORLDS) 541 542 /* FEAT_MEC: Memory Encryption Contexts */ 543 CREATE_FEATURE_FUNCS(feat_mec, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_MEC_SHIFT, 544 ID_AA64MMFR3_EL1_MEC_MASK, 1U, ENABLE_FEAT_MEC, 545 FEAT_ENABLE_ALL_WORLDS) 546 547 /* 548 * FEAT_CSV2: Cache Speculation Variant 2. This checks bit fields[56-59] 549 * of id_aa64pfr0_el1 register and can be used to check for below features: 550 * FEAT_CSV2_2: Cache Speculation Variant CSV2_2. 551 * FEAT_CSV2_3: Cache Speculation Variant CSV2_3. 552 * 0b0000 - Feature FEAT_CSV2 is not implemented. 553 * 0b0001 - Feature FEAT_CSV2 is implemented, but FEAT_CSV2_2 and FEAT_CSV2_3 554 * are not implemented. 555 * 0b0010 - Feature FEAT_CSV2_2 is implemented but FEAT_CSV2_3 is not 556 * implemented. 557 * 0b0011 - Feature FEAT_CSV2_3 is implemented. 558 */ 559 560 CREATE_FEATURE_FUNCS(feat_csv2_2, id_aa64pfr0_el1, ID_AA64PFR0_CSV2_SHIFT, 561 ID_AA64PFR0_CSV2_MASK, CSV2_2_IMPLEMENTED, ENABLE_FEAT_CSV2_2, 562 FEAT_ENABLE_NS | FEAT_ENABLE_REALM) 563 CREATE_FEATURE_FUNCS(feat_csv2_3, id_aa64pfr0_el1, ID_AA64PFR0_CSV2_SHIFT, 564 ID_AA64PFR0_CSV2_MASK, CSV2_3_IMPLEMENTED, ENABLE_FEAT_CSV2_3, 565 FEAT_ENABLE_ALL_WORLDS) 566 567 /* FEAT_SPE: Statistical Profiling Extension */ 568 CREATE_PERCPU_FEATURE_FUNCS(feat_spe, id_aa64dfr0_el1, ID_AA64DFR0_PMS_SHIFT, 569 ID_AA64DFR0_PMS_MASK, 1U, ENABLE_SPE_FOR_NS, 570 FEAT_ENABLE_ALL_WORLDS) 571 572 /* FEAT_SVE: Scalable Vector Extension */ 573 CREATE_FEATURE_FUNCS(feat_sve, id_aa64pfr0_el1, ID_AA64PFR0_SVE_SHIFT, 574 ID_AA64PFR0_SVE_MASK, 1U, ENABLE_SVE_FOR_NS, 575 FEAT_ENABLE_ALL_WORLDS) 576 577 /* FEAT_RAS: Reliability, Accessibility, Serviceability */ 578 CREATE_FEATURE_FUNCS(feat_ras, id_aa64pfr0_el1, ID_AA64PFR0_RAS_SHIFT, 579 ID_AA64PFR0_RAS_MASK, 1U, ENABLE_FEAT_RAS, 580 FEAT_ENABLE_ALL_WORLDS) 581 582 /* FEAT_DIT: Data Independent Timing instructions */ 583 CREATE_FEATURE_FUNCS(feat_dit, id_aa64pfr0_el1, ID_AA64PFR0_DIT_SHIFT, 584 ID_AA64PFR0_DIT_MASK, 1U, ENABLE_FEAT_DIT, 585 FEAT_ENABLE_ALL_WORLDS) 586 587 /* FEAT_SYS_REG_TRACE */ 588 CREATE_PERCPU_FEATURE_FUNCS(feat_sys_reg_trace, id_aa64dfr0_el1, 589 ID_AA64DFR0_TRACEVER_SHIFT, ID_AA64DFR0_TRACEVER_MASK, 590 1U, ENABLE_SYS_REG_TRACE_FOR_NS, 591 FEAT_ENABLE_ALL_WORLDS) 592 593 /* FEAT_TRF: TraceFilter */ 594 CREATE_PERCPU_FEATURE_FUNCS(feat_trf, id_aa64dfr0_el1, ID_AA64DFR0_TRACEFILT_SHIFT, 595 ID_AA64DFR0_TRACEFILT_MASK, 1U, ENABLE_TRF_FOR_NS, 596 FEAT_ENABLE_ALL_WORLDS) 597 598 /* FEAT_NV2: Enhanced Nested Virtualization */ 599 CREATE_FEATURE_FUNCS(feat_nv2, id_aa64mmfr2_el1, ID_AA64MMFR2_EL1_NV_SHIFT, 600 ID_AA64MMFR2_EL1_NV_MASK, NV2_IMPLEMENTED, CTX_INCLUDE_NEVE_REGS, 601 FEAT_ENABLE_ALL_WORLDS) 602 603 /* FEAT_BRBE: Branch Record Buffer Extension */ 604 CREATE_PERCPU_FEATURE_FUNCS(feat_brbe, id_aa64dfr0_el1, ID_AA64DFR0_BRBE_SHIFT, 605 ID_AA64DFR0_BRBE_MASK, 1U, ENABLE_BRBE_FOR_NS, 606 FEAT_ENABLE_NS | FEAT_ENABLE_REALM) 607 608 /* FEAT_TRBE: Trace Buffer Extension */ 609 _CREATE_FEATURE_PRESENT(feat_trbe, id_aa64dfr0_el1, ID_AA64DFR0_TRACEBUFFER_SHIFT, 610 ID_AA64DFR0_TRACEBUFFER_MASK, 1U) 611 612 CREATE_FEATURE_SUPPORTED(feat_trbe, is_feat_trbe_present, ENABLE_TRBE_FOR_NS) 613 614 CREATE_PERCPU_IDREG_UPDATE(feat_trbe, id_aa64dfr0_el1, ID_AA64DFR0_TRACEBUFFER_SHIFT, 615 ID_AA64DFR0_TRACEBUFFER_MASK, 616 ENABLE_TRBE_FOR_NS && !check_if_trbe_disable_affected_core(), 617 FEAT_ENABLE_NS) 618 619 /* FEAT_SME_FA64: Full A64 Instruction support in streaming SVE mode */ 620 CREATE_FEATURE_PRESENT(feat_sme_fa64, id_aa64smfr0_el1, ID_AA64SMFR0_EL1_SME_FA64_SHIFT, 621 ID_AA64SMFR0_EL1_SME_FA64_MASK, 1U, 622 FEAT_ENABLE_ALL_WORLDS) 623 624 /* FEAT_SMEx: Scalar Matrix Extension */ 625 CREATE_FEATURE_FUNCS(feat_sme, id_aa64pfr1_el1, ID_AA64PFR1_EL1_SME_SHIFT, 626 ID_AA64PFR1_EL1_SME_MASK, 1U, ENABLE_SME_FOR_NS, 627 FEAT_ENABLE_ALL_WORLDS) 628 629 CREATE_FEATURE_FUNCS(feat_sme2, id_aa64pfr1_el1, ID_AA64PFR1_EL1_SME_SHIFT, 630 ID_AA64PFR1_EL1_SME_MASK, SME2_IMPLEMENTED, ENABLE_SME2_FOR_NS, 631 FEAT_ENABLE_ALL_WORLDS) 632 633 /* FEAT_LS64_ACCDATA: Support for 64-byte EL0 stores with status */ 634 CREATE_FEATURE_FUNCS(feat_ls64_accdata, id_aa64isar1_el1, ID_AA64ISAR1_LS64_SHIFT, 635 ID_AA64ISAR1_LS64_MASK, LS64_ACCDATA_IMPLEMENTED, 636 ENABLE_FEAT_LS64_ACCDATA, FEAT_ENABLE_ALL_WORLDS) 637 638 /* FEAT_AIE: Memory Attribute Index Enhancement */ 639 CREATE_FEATURE_FUNCS(feat_aie, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_AIE_SHIFT, 640 ID_AA64MMFR3_EL1_AIE_MASK, 1U, ENABLE_FEAT_AIE, 641 FEAT_ENABLE_NS) 642 643 /* FEAT_PFAR: Physical Fault Address Register Extension */ 644 CREATE_FEATURE_FUNCS(feat_pfar, id_aa64pfr1_el1, ID_AA64PFR1_EL1_PFAR_SHIFT, 645 ID_AA64PFR1_EL1_PFAR_MASK, 1U, ENABLE_FEAT_PFAR, 646 FEAT_ENABLE_NS) 647 648 /* FEAT_IDTE3: Trapping lower EL ID Register access to EL3 */ 649 CREATE_FEATURE_FUNCS(feat_idte3, id_aa64mmfr2_el1, ID_AA64MMFR2_EL1_IDS_SHIFT, 650 ID_AA64MMFR2_EL1_IDS_MASK, 2U, ENABLE_FEAT_IDTE3, 651 FEAT_ENABLE_ALL_WORLDS) 652 653 /* FEAT_LSE: Atomic instructions */ 654 CREATE_FEATURE_FUNCS(feat_lse, id_aa64isar0_el1, ID_AA64ISAR0_ATOMIC_SHIFT, 655 ID_AA64ISAR0_ATOMIC_MASK, 1U, USE_SPINLOCK_CAS, 656 FEAT_ENABLE_ALL_WORLDS) 657 658 659 /******************************************************************************* 660 * Function to get hardware granularity support 661 ******************************************************************************/ 662 663 __attribute__((always_inline)) 664 static inline bool is_feat_tgran4K_present(void) 665 { 666 unsigned int tgranx = ISOLATE_FIELD(read_id_aa64mmfr0_el1(), 667 ID_AA64MMFR0_EL1_TGRAN4_SHIFT, ID_REG_FIELD_MASK); 668 return (tgranx < 8U); 669 } 670 671 CREATE_FEATURE_PRESENT(feat_tgran16K, id_aa64mmfr0_el1, ID_AA64MMFR0_EL1_TGRAN16_SHIFT, 672 ID_AA64MMFR0_EL1_TGRAN16_MASK, TGRAN16_IMPLEMENTED, 673 FEAT_ENABLE_ALL_WORLDS) 674 675 __attribute__((always_inline)) 676 static inline bool is_feat_tgran64K_present(void) 677 { 678 unsigned int tgranx = ISOLATE_FIELD(read_id_aa64mmfr0_el1(), 679 ID_AA64MMFR0_EL1_TGRAN64_SHIFT, ID_REG_FIELD_MASK); 680 return (tgranx < 8U); 681 } 682 683 /* FEAT_PMUV3 */ 684 _CREATE_FEATURE_PRESENT(feat_pmuv3, id_aa64dfr0_el1, ID_AA64DFR0_PMUVER_SHIFT, 685 ID_AA64DFR0_PMUVER_MASK, 1U) 686 687 /* FEAT_MTPMU */ 688 __attribute__((always_inline)) 689 static inline bool is_feat_mtpmu_present(void) 690 { 691 unsigned int mtpmu = ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_MTPMU_SHIFT, 692 ID_AA64DFR0_MTPMU_MASK); 693 return (mtpmu != 0U) && (mtpmu != MTPMU_NOT_IMPLEMENTED); 694 } 695 696 CREATE_FEATURE_SUPPORTED(feat_mtpmu, is_feat_mtpmu_present, DISABLE_MTPMU) 697 698 CREATE_PERCPU_IDREG_UPDATE(feat_mtpmu, id_aa64dfr0_el1, ID_AA64DFR0_MTPMU_SHIFT, 699 ID_AA64DFR0_MTPMU_MASK, DISABLE_MTPMU, 700 FEAT_ENABLE_ALL_WORLDS) 701 702 /************************************************************************* 703 * Function to identify the presence of FEAT_GCIE (GICv5 CPU interface 704 * extension). 705 ************************************************************************/ 706 CREATE_FEATURE_FUNCS(feat_gcie, id_aa64pfr2_el1, ID_AA64PFR2_EL1_GCIE_SHIFT, 707 ID_AA64PFR2_EL1_GCIE_MASK, 1U, ENABLE_FEAT_GCIE, 708 FEAT_ENABLE_ALL_WORLDS) 709 710 CREATE_FEATURE_FUNCS(feat_cpa2, id_aa64isar3_el1, ID_AA64ISAR3_EL1_CPA_SHIFT, 711 ID_AA64ISAR3_EL1_CPA_MASK, CPA2_IMPLEMENTED, 712 ENABLE_FEAT_CPA2, FEAT_ENABLE_ALL_WORLDS) 713 714 /* FEAT_UINJ: Injection of Undefined Instruction exceptions */ 715 CREATE_FEATURE_FUNCS(feat_uinj, id_aa64pfr2_el1, ID_AA64PFR2_EL1_UINJ_SHIFT, 716 ID_AA64PFR2_EL1_UINJ_MASK, UINJ_IMPLEMENTED, 717 ENABLE_FEAT_UINJ, FEAT_ENABLE_ALL_WORLDS) 718 719 /* FEAT_MORELLO_PRESENT */ 720 CREATE_FEATURE_FUNCS(feat_morello, id_aa64pfr1_el1, ID_AA64PFR1_EL1_CE_SHIFT, 721 ID_AA64PFR1_EL1_CE_MASK, MORELLO_EXTENSION_IMPLEMENTED, 722 ENABLE_FEAT_MORELLO, FEAT_ENABLE_ALL_WORLDS) 723 724 /* FEAT_STEP2: Enhanced Software Step Extension */ 725 CREATE_FEATURE_FUNCS(feat_step2, id_aa64dfr2_el1, ID_AA64DFR2_STEP_SHIFT, 726 ID_AA64DFR2_STEP_MASK, 1U, ENABLE_FEAT_STEP2, 727 FEAT_ENABLE_ALL_WORLDS) 728 729 /* FEAT_HDBSS: Hardware Dirty state tracking structure */ 730 CREATE_FEATURE_FUNCS(feat_hdbss, id_aa64mmfr1_el1, ID_AA64MMFR1_EL1_HAFDBS_SHIFT, 731 ID_AA64MMFR1_EL1_HAFDBS_MASK, HDBSS_IMPLEMENTED, 732 ENABLE_FEAT_HDBSS, FEAT_ENABLE_NS) 733 734 /* FEAT_HACDBS: Hardware accelerator for cleaning Dirty state */ 735 CREATE_FEATURE_FUNCS(feat_hacdbs, id_aa64mmfr4_el1, ID_AA64MMFR4_EL1_HACDBS_SHIFT, 736 ID_AA64MMFR4_EL1_HACDBS_MASK, HACDBS_IMPLEMENTED, 737 ENABLE_FEAT_HACDBS, FEAT_ENABLE_NS) 738 739 #endif /* ARCH_FEATURES_H */ 740