1 /* 2 * Copyright (c) 2019-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef ARCH_FEATURES_H 8 #define ARCH_FEATURES_H 9 10 #include <stdbool.h> 11 12 #include <arch_helpers.h> 13 #include <common/feat_detect.h> 14 15 #define ISOLATE_FIELD(reg, feat, mask) \ 16 ((unsigned int)(((reg) >> (feat)) & mask)) 17 18 #define CREATE_FEATURE_SUPPORTED(name, read_func, guard) \ 19 __attribute__((always_inline)) \ 20 static inline bool is_ ## name ## _supported(void) \ 21 { \ 22 if ((guard) == FEAT_STATE_DISABLED) { \ 23 return false; \ 24 } \ 25 if ((guard) == FEAT_STATE_ALWAYS) { \ 26 return true; \ 27 } \ 28 return read_func(); \ 29 } 30 31 #define CREATE_FEATURE_PRESENT(name, idreg, idfield, mask, idval) \ 32 __attribute__((always_inline)) \ 33 static inline bool is_ ## name ## _present(void) \ 34 { \ 35 return (ISOLATE_FIELD(read_ ## idreg(), idfield, mask) >= idval) \ 36 ? true : false; \ 37 } 38 39 #define CREATE_FEATURE_FUNCS(name, idreg, idfield, mask, idval, guard) \ 40 CREATE_FEATURE_PRESENT(name, idreg, idfield, mask, idval) \ 41 CREATE_FEATURE_SUPPORTED(name, is_ ## name ## _present, guard) 42 43 44 /* +----------------------------+ 45 * | Features supported | 46 * +----------------------------+ 47 * | GENTIMER | 48 * +----------------------------+ 49 * | FEAT_PAN | 50 * +----------------------------+ 51 * | FEAT_VHE | 52 * +----------------------------+ 53 * | FEAT_TTCNP | 54 * +----------------------------+ 55 * | FEAT_UAO | 56 * +----------------------------+ 57 * | FEAT_PACQARMA3 | 58 * +----------------------------+ 59 * | FEAT_PAUTH | 60 * +----------------------------+ 61 * | FEAT_TTST | 62 * +----------------------------+ 63 * | FEAT_BTI | 64 * +----------------------------+ 65 * | FEAT_MTE2 | 66 * +----------------------------+ 67 * | FEAT_SSBS | 68 * +----------------------------+ 69 * | FEAT_NMI | 70 * +----------------------------+ 71 * | FEAT_GCS | 72 * +----------------------------+ 73 * | FEAT_EBEP | 74 * +----------------------------+ 75 * | FEAT_SEBEP | 76 * +----------------------------+ 77 * | FEAT_SEL2 | 78 * +----------------------------+ 79 * | FEAT_TWED | 80 * +----------------------------+ 81 * | FEAT_FGT | 82 * +----------------------------+ 83 * | FEAT_EC/ECV2 | 84 * +----------------------------+ 85 * | FEAT_RNG | 86 * +----------------------------+ 87 * | FEAT_TCR2 | 88 * +----------------------------+ 89 * | FEAT_S2POE | 90 * +----------------------------+ 91 * | FEAT_S1POE | 92 * +----------------------------+ 93 * | FEAT_S2PIE | 94 * +----------------------------+ 95 * | FEAT_S1PIE | 96 * +----------------------------+ 97 * | FEAT_AMU/AMUV1P1 | 98 * +----------------------------+ 99 * | FEAT_MPAM | 100 * +----------------------------+ 101 * | FEAT_HCX | 102 * +----------------------------+ 103 * | FEAT_RNG_TRAP | 104 * +----------------------------+ 105 * | FEAT_RME | 106 * +----------------------------+ 107 * | FEAT_SB | 108 * +----------------------------+ 109 * | FEAT_CSV2/CSV3 | 110 * +----------------------------+ 111 * | FEAT_SPE | 112 * +----------------------------+ 113 * | FEAT_SVE | 114 * +----------------------------+ 115 * | FEAT_RAS | 116 * +----------------------------+ 117 * | FEAT_DIT | 118 * +----------------------------+ 119 * | FEAT_SYS_REG_TRACE | 120 * +----------------------------+ 121 * | FEAT_TRF | 122 * +----------------------------+ 123 * | FEAT_NV2 | 124 * +----------------------------+ 125 * | FEAT_BRBE | 126 * +----------------------------+ 127 * | FEAT_TRBE | 128 * +----------------------------+ 129 * | FEAT_SME/SME2 | 130 * +----------------------------+ 131 * | FEAT_PMUV3 | 132 * +----------------------------+ 133 * | FEAT_MTPMU | 134 * +----------------------------+ 135 * | FEAT_FGT2 | 136 * +----------------------------+ 137 * | FEAT_THE | 138 * +----------------------------+ 139 * | FEAT_SCTLR2 | 140 * +----------------------------+ 141 * | FEAT_D128 | 142 * +----------------------------+ 143 * | FEAT_LS64_ACCDATA | 144 * +----------------------------+ 145 * | FEAT_FPMR | 146 * +----------------------------+ 147 * | FEAT_MOPS | 148 * +----------------------------+ 149 * | FEAT_PAUTH_LR | 150 * +----------------------------+ 151 * | FEAT_FGWTE3 | 152 * +----------------------------+ 153 * | FEAT_MPAM_PE_BW_CTRL | 154 * +----------------------------+ 155 * | FEAT_CPA2 | 156 * +----------------------------+ 157 * | FEAT_AIE | 158 * +----------------------------+ 159 * | FEAT_PFAR | 160 * +----------------------------+ 161 * | FEAT_RME_GPC2 | 162 * +----------------------------+ 163 * | FEAT_RME_GDI | 164 * +----------------------------+ 165 */ 166 167 __attribute__((always_inline)) 168 static inline bool is_armv7_gentimer_present(void) 169 { 170 /* The Generic Timer is always present in an ARMv8-A implementation */ 171 return true; 172 } 173 174 /* FEAT_PAN: Privileged access never */ 175 CREATE_FEATURE_FUNCS(feat_pan, id_aa64mmfr1_el1, ID_AA64MMFR1_EL1_PAN_SHIFT, 176 ID_AA64MMFR1_EL1_PAN_MASK, 1U, ENABLE_FEAT_PAN) 177 178 /* FEAT_VHE: Virtualization Host Extensions */ 179 CREATE_FEATURE_FUNCS(feat_vhe, id_aa64mmfr1_el1, ID_AA64MMFR1_EL1_VHE_SHIFT, 180 ID_AA64MMFR1_EL1_VHE_MASK, 1U, ENABLE_FEAT_VHE) 181 182 /* FEAT_TTCNP: Translation table common not private */ 183 CREATE_FEATURE_PRESENT(feat_ttcnp, id_aa64mmfr2_el1, ID_AA64MMFR2_EL1_CNP_SHIFT, 184 ID_AA64MMFR2_EL1_CNP_MASK, 1U) 185 186 /* FEAT_UAO: User access override */ 187 CREATE_FEATURE_PRESENT(feat_uao, id_aa64mmfr2_el1, ID_AA64MMFR2_EL1_UAO_SHIFT, 188 ID_AA64MMFR2_EL1_UAO_MASK, 1U) 189 190 /* If any of the fields is not zero, QARMA3 algorithm is present */ 191 CREATE_FEATURE_PRESENT(feat_pacqarma3, id_aa64isar2_el1, 0, 192 ((ID_AA64ISAR2_GPA3_MASK << ID_AA64ISAR2_GPA3_SHIFT) | 193 (ID_AA64ISAR2_APA3_MASK << ID_AA64ISAR2_APA3_SHIFT)), 1U) 194 195 /* FEAT_PAUTH: Pointer Authentication */ 196 __attribute__((always_inline)) 197 static inline bool is_feat_pauth_present(void) 198 { 199 uint64_t mask_id_aa64isar1 = 200 (ID_AA64ISAR1_GPI_MASK << ID_AA64ISAR1_GPI_SHIFT) | 201 (ID_AA64ISAR1_GPA_MASK << ID_AA64ISAR1_GPA_SHIFT) | 202 (ID_AA64ISAR1_API_MASK << ID_AA64ISAR1_API_SHIFT) | 203 (ID_AA64ISAR1_APA_MASK << ID_AA64ISAR1_APA_SHIFT); 204 205 /* 206 * If any of the fields is not zero or QARMA3 is present, 207 * PAuth is present 208 */ 209 return ((read_id_aa64isar1_el1() & mask_id_aa64isar1) != 0U || 210 is_feat_pacqarma3_present()); 211 } 212 CREATE_FEATURE_SUPPORTED(feat_pauth, is_feat_pauth_present, ENABLE_PAUTH) 213 CREATE_FEATURE_SUPPORTED(ctx_pauth, is_feat_pauth_present, CTX_INCLUDE_PAUTH_REGS) 214 215 /* 216 * FEAT_PAUTH_LR 217 * This feature has a non-standard discovery method so define this function 218 * manually then call use the CREATE_FEATURE_SUPPORTED macro with it. This 219 * feature is enabled with ENABLE_PAUTH when present. 220 */ 221 __attribute__((always_inline)) 222 static inline bool is_feat_pauth_lr_present(void) 223 { 224 /* 225 * FEAT_PAUTH_LR support is indicated by up to 3 fields, if one or more 226 * of these is 0b0110 then the feature is present. 227 * 1) id_aa64isr1_el1.api 228 * 2) id_aa64isr1_el1.apa 229 * 3) id_aa64isr2_el1.apa3 230 */ 231 if (ISOLATE_FIELD(read_id_aa64isar1_el1(), ID_AA64ISAR1_API_SHIFT, ID_AA64ISAR1_API_MASK) == 0b0110) { 232 return true; 233 } 234 if (ISOLATE_FIELD(read_id_aa64isar1_el1(), ID_AA64ISAR1_APA_SHIFT, ID_AA64ISAR1_APA_MASK) == 0b0110) { 235 return true; 236 } 237 if (ISOLATE_FIELD(read_id_aa64isar2_el1(), ID_AA64ISAR2_APA3_SHIFT, ID_AA64ISAR2_APA3_MASK) == 0b0110) { 238 return true; 239 } 240 return false; 241 } 242 CREATE_FEATURE_SUPPORTED(feat_pauth_lr, is_feat_pauth_lr_present, ENABLE_FEAT_PAUTH_LR) 243 244 /* FEAT_TTST: Small translation tables */ 245 CREATE_FEATURE_PRESENT(feat_ttst, id_aa64mmfr2_el1, ID_AA64MMFR2_EL1_ST_SHIFT, 246 ID_AA64MMFR2_EL1_ST_MASK, 1U) 247 248 /* FEAT_BTI: Branch target identification */ 249 CREATE_FEATURE_FUNCS(feat_bti, id_aa64pfr1_el1, ID_AA64PFR1_EL1_BT_SHIFT, 250 ID_AA64PFR1_EL1_BT_MASK, BTI_IMPLEMENTED, ENABLE_BTI) 251 252 /* FEAT_MTE2: Memory tagging extension */ 253 CREATE_FEATURE_FUNCS(feat_mte2, id_aa64pfr1_el1, ID_AA64PFR1_EL1_MTE_SHIFT, 254 ID_AA64PFR1_EL1_MTE_MASK, MTE_IMPLEMENTED_ELX, ENABLE_FEAT_MTE2) 255 256 /* FEAT_SSBS: Speculative store bypass safe */ 257 CREATE_FEATURE_PRESENT(feat_ssbs, id_aa64pfr1_el1, ID_AA64PFR1_EL1_SSBS_SHIFT, 258 ID_AA64PFR1_EL1_SSBS_MASK, 1U) 259 260 /* FEAT_NMI: Non-maskable interrupts */ 261 CREATE_FEATURE_PRESENT(feat_nmi, id_aa64pfr1_el1, ID_AA64PFR1_EL1_NMI_SHIFT, 262 ID_AA64PFR1_EL1_NMI_MASK, NMI_IMPLEMENTED) 263 264 /* FEAT_EBEP */ 265 CREATE_FEATURE_FUNCS(feat_ebep, id_aa64dfr1_el1, ID_AA64DFR1_EBEP_SHIFT, 266 ID_AA64DFR1_EBEP_MASK, 1U, ENABLE_FEAT_EBEP) 267 268 /* FEAT_SEBEP */ 269 CREATE_FEATURE_PRESENT(feat_sebep, id_aa64dfr0_el1, ID_AA64DFR0_SEBEP_SHIFT, 270 ID_AA64DFR0_SEBEP_MASK, SEBEP_IMPLEMENTED) 271 272 /* FEAT_SEL2: Secure EL2 */ 273 CREATE_FEATURE_FUNCS(feat_sel2, id_aa64pfr0_el1, ID_AA64PFR0_SEL2_SHIFT, 274 ID_AA64PFR0_SEL2_MASK, 1U, ENABLE_FEAT_SEL2) 275 276 /* FEAT_TWED: Delayed trapping of WFE */ 277 CREATE_FEATURE_FUNCS(feat_twed, id_aa64mmfr1_el1, ID_AA64MMFR1_EL1_TWED_SHIFT, 278 ID_AA64MMFR1_EL1_TWED_MASK, 1U, ENABLE_FEAT_TWED) 279 280 /* FEAT_FGT: Fine-grained traps */ 281 CREATE_FEATURE_FUNCS(feat_fgt, id_aa64mmfr0_el1, ID_AA64MMFR0_EL1_FGT_SHIFT, 282 ID_AA64MMFR0_EL1_FGT_MASK, 1U, ENABLE_FEAT_FGT) 283 284 /* FEAT_FGT2: Fine-grained traps extended */ 285 CREATE_FEATURE_FUNCS(feat_fgt2, id_aa64mmfr0_el1, ID_AA64MMFR0_EL1_FGT_SHIFT, 286 ID_AA64MMFR0_EL1_FGT_MASK, FGT2_IMPLEMENTED, ENABLE_FEAT_FGT2) 287 288 /* FEAT_FGWTE3: Fine-grained write traps EL3 */ 289 CREATE_FEATURE_FUNCS(feat_fgwte3, id_aa64mmfr4_el1, ID_AA64MMFR4_EL1_FGWTE3_SHIFT, 290 ID_AA64MMFR4_EL1_FGWTE3_MASK, FGWTE3_IMPLEMENTED, 291 ENABLE_FEAT_FGWTE3) 292 293 /* FEAT_ECV: Enhanced Counter Virtualization */ 294 CREATE_FEATURE_FUNCS(feat_ecv, id_aa64mmfr0_el1, ID_AA64MMFR0_EL1_ECV_SHIFT, 295 ID_AA64MMFR0_EL1_ECV_MASK, 1U, ENABLE_FEAT_ECV) 296 CREATE_FEATURE_FUNCS(feat_ecv_v2, id_aa64mmfr0_el1, ID_AA64MMFR0_EL1_ECV_SHIFT, 297 ID_AA64MMFR0_EL1_ECV_MASK, ID_AA64MMFR0_EL1_ECV_SELF_SYNCH, ENABLE_FEAT_ECV) 298 299 /* FEAT_RNG: Random number generator */ 300 CREATE_FEATURE_FUNCS(feat_rng, id_aa64isar0_el1, ID_AA64ISAR0_RNDR_SHIFT, 301 ID_AA64ISAR0_RNDR_MASK, 1U, ENABLE_FEAT_RNG) 302 303 /* FEAT_TCR2: Support TCR2_ELx regs */ 304 CREATE_FEATURE_FUNCS(feat_tcr2, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_TCRX_SHIFT, 305 ID_AA64MMFR3_EL1_TCRX_MASK, 1U, ENABLE_FEAT_TCR2) 306 307 /* FEAT_S2POE */ 308 CREATE_FEATURE_FUNCS(feat_s2poe, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_S2POE_SHIFT, 309 ID_AA64MMFR3_EL1_S2POE_MASK, 1U, ENABLE_FEAT_S2POE) 310 311 /* FEAT_S1POE */ 312 CREATE_FEATURE_FUNCS(feat_s1poe, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_S1POE_SHIFT, 313 ID_AA64MMFR3_EL1_S1POE_MASK, 1U, ENABLE_FEAT_S1POE) 314 315 __attribute__((always_inline)) 316 static inline bool is_feat_sxpoe_supported(void) 317 { 318 return is_feat_s1poe_supported() || is_feat_s2poe_supported(); 319 } 320 321 /* FEAT_S2PIE */ 322 CREATE_FEATURE_FUNCS(feat_s2pie, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_S2PIE_SHIFT, 323 ID_AA64MMFR3_EL1_S2PIE_MASK, 1U, ENABLE_FEAT_S2PIE) 324 325 /* FEAT_S1PIE */ 326 CREATE_FEATURE_FUNCS(feat_s1pie, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_S1PIE_SHIFT, 327 ID_AA64MMFR3_EL1_S1PIE_MASK, 1U, ENABLE_FEAT_S1PIE) 328 329 /* FEAT_THE: Translation Hardening Extension */ 330 CREATE_FEATURE_FUNCS(feat_the, id_aa64pfr1_el1, ID_AA64PFR1_EL1_THE_SHIFT, 331 ID_AA64PFR1_EL1_THE_MASK, THE_IMPLEMENTED, ENABLE_FEAT_THE) 332 333 /* FEAT_SCTLR2 */ 334 CREATE_FEATURE_FUNCS(feat_sctlr2, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_SCTLR2_SHIFT, 335 ID_AA64MMFR3_EL1_SCTLR2_MASK, SCTLR2_IMPLEMENTED, 336 ENABLE_FEAT_SCTLR2) 337 338 /* FEAT_D128 */ 339 CREATE_FEATURE_FUNCS(feat_d128, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_D128_SHIFT, 340 ID_AA64MMFR3_EL1_D128_MASK, D128_IMPLEMENTED, 341 ENABLE_FEAT_D128) 342 343 /* FEAT_RME_GPC2 */ 344 CREATE_FEATURE_PRESENT(feat_rme_gpc2, id_aa64pfr0_el1, 345 ID_AA64PFR0_FEAT_RME_SHIFT, ID_AA64PFR0_FEAT_RME_MASK, 346 RME_GPC2_IMPLEMENTED) 347 348 /* FEAT_RME_GDI */ 349 CREATE_FEATURE_FUNCS(feat_rme_gdi, id_aa64mmfr4_el1, 350 ID_AA64MMFR4_EL1_RME_GDI_SHIFT, 351 ID_AA64MMFR4_EL1_RME_GDI_MASK, RME_GDI_IMPLEMENTED, 352 ENABLE_FEAT_RME_GDI) 353 354 /* FEAT_FPMR */ 355 CREATE_FEATURE_FUNCS(feat_fpmr, id_aa64pfr2_el1, ID_AA64PFR2_EL1_FPMR_SHIFT, 356 ID_AA64PFR2_EL1_FPMR_MASK, FPMR_IMPLEMENTED, 357 ENABLE_FEAT_FPMR) 358 /* FEAT_MOPS */ 359 CREATE_FEATURE_FUNCS(feat_mops, id_aa64isar2_el1, ID_AA64ISAR2_EL1_MOPS_SHIFT, 360 ID_AA64ISAR2_EL1_MOPS_MASK, MOPS_IMPLEMENTED, 361 ENABLE_FEAT_MOPS) 362 363 __attribute__((always_inline)) 364 static inline bool is_feat_sxpie_supported(void) 365 { 366 return is_feat_s1pie_supported() || is_feat_s2pie_supported(); 367 } 368 369 /* FEAT_GCS: Guarded Control Stack */ 370 CREATE_FEATURE_FUNCS(feat_gcs, id_aa64pfr1_el1, ID_AA64PFR1_EL1_GCS_SHIFT, 371 ID_AA64PFR1_EL1_GCS_MASK, 1U, ENABLE_FEAT_GCS) 372 373 /* FEAT_AMU: Activity Monitors Extension */ 374 CREATE_FEATURE_FUNCS(feat_amu, id_aa64pfr0_el1, ID_AA64PFR0_AMU_SHIFT, 375 ID_AA64PFR0_AMU_MASK, 1U, ENABLE_FEAT_AMU) 376 377 /* Auxiliary counters for FEAT_AMU */ 378 CREATE_FEATURE_FUNCS(feat_amu_aux, amcfgr_el0, AMCFGR_EL0_NCG_SHIFT, 379 AMCFGR_EL0_NCG_MASK, 1U, ENABLE_AMU_AUXILIARY_COUNTERS) 380 381 /* FEAT_AMUV1P1: AMU Extension v1.1 */ 382 CREATE_FEATURE_FUNCS(feat_amuv1p1, id_aa64pfr0_el1, ID_AA64PFR0_AMU_SHIFT, 383 ID_AA64PFR0_AMU_MASK, ID_AA64PFR0_AMU_V1P1, ENABLE_FEAT_AMUv1p1) 384 385 /* 386 * Return MPAM version: 387 * 388 * 0x00: None Armv8.0 or later 389 * 0x01: v0.1 Armv8.4 or later 390 * 0x10: v1.0 Armv8.2 or later 391 * 0x11: v1.1 Armv8.4 or later 392 * 393 */ 394 __attribute__((always_inline)) 395 static inline bool is_feat_mpam_present(void) 396 { 397 unsigned int ret = (unsigned int)((((read_id_aa64pfr0_el1() >> 398 ID_AA64PFR0_MPAM_SHIFT) & ID_AA64PFR0_MPAM_MASK) << 4) | 399 ((read_id_aa64pfr1_el1() >> ID_AA64PFR1_MPAM_FRAC_SHIFT) 400 & ID_AA64PFR1_MPAM_FRAC_MASK)); 401 return ret; 402 } 403 404 CREATE_FEATURE_SUPPORTED(feat_mpam, is_feat_mpam_present, ENABLE_FEAT_MPAM) 405 406 407 408 /* FEAT_MPAM_PE_BW_CTRL: MPAM PE-side bandwidth controls */ 409 __attribute__((always_inline)) 410 static inline bool is_feat_mpam_pe_bw_ctrl_present(void) 411 { 412 if (is_feat_mpam_present()) { 413 return ((unsigned long long)(read_mpamidr_el1() & 414 MPAMIDR_HAS_BW_CTRL_BIT) != 0U); 415 } 416 return false; 417 } 418 419 CREATE_FEATURE_SUPPORTED(feat_mpam_pe_bw_ctrl, is_feat_mpam_pe_bw_ctrl_present, 420 ENABLE_FEAT_MPAM_PE_BW_CTRL) 421 422 /* 423 * FEAT_DebugV8P9: Debug extension. This function checks the field 3:0 of 424 * ID_AA64DFR0 Aarch64 Debug Feature Register 0 for the version of 425 * Feat_Debug supported. The value of the field determines feature presence 426 * 427 * 0b0110 - Arm v8.0 debug 428 * 0b0111 - Arm v8.0 debug architecture with Virtualization host extensions 429 * 0x1000 - FEAT_Debugv8p2 is supported 430 * 0x1001 - FEAT_Debugv8p4 is supported 431 * 0x1010 - FEAT_Debugv8p8 is supported 432 * 0x1011 - FEAT_Debugv8p9 is supported 433 * 434 */ 435 CREATE_FEATURE_FUNCS(feat_debugv8p9, id_aa64dfr0_el1, ID_AA64DFR0_DEBUGVER_SHIFT, 436 ID_AA64DFR0_DEBUGVER_MASK, DEBUGVER_V8P9_IMPLEMENTED, 437 ENABLE_FEAT_DEBUGV8P9) 438 439 /* FEAT_HCX: Extended Hypervisor Configuration Register */ 440 CREATE_FEATURE_FUNCS(feat_hcx, id_aa64mmfr1_el1, ID_AA64MMFR1_EL1_HCX_SHIFT, 441 ID_AA64MMFR1_EL1_HCX_MASK, 1U, ENABLE_FEAT_HCX) 442 443 /* FEAT_RNG_TRAP: Trapping support */ 444 CREATE_FEATURE_FUNCS(feat_rng_trap, id_aa64pfr1_el1, ID_AA64PFR1_EL1_RNDR_TRAP_SHIFT, 445 ID_AA64PFR1_EL1_RNDR_TRAP_MASK, RNG_TRAP_IMPLEMENTED, ENABLE_FEAT_RNG_TRAP) 446 447 /* Return the RME version, zero if not supported. */ 448 CREATE_FEATURE_FUNCS(feat_rme, id_aa64pfr0_el1, ID_AA64PFR0_FEAT_RME_SHIFT, 449 ID_AA64PFR0_FEAT_RME_MASK, 1U, ENABLE_RME) 450 451 /* FEAT_SB: Speculation barrier instruction */ 452 CREATE_FEATURE_PRESENT(feat_sb, id_aa64isar1_el1, ID_AA64ISAR1_SB_SHIFT, 453 ID_AA64ISAR1_SB_MASK, 1U) 454 455 /* FEAT_MEC: Memory Encryption Contexts */ 456 CREATE_FEATURE_FUNCS(feat_mec, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_MEC_SHIFT, 457 ID_AA64MMFR3_EL1_MEC_MASK, 1U, ENABLE_FEAT_MEC) 458 459 /* 460 * FEAT_CSV2: Cache Speculation Variant 2. This checks bit fields[56-59] 461 * of id_aa64pfr0_el1 register and can be used to check for below features: 462 * FEAT_CSV2_2: Cache Speculation Variant CSV2_2. 463 * FEAT_CSV2_3: Cache Speculation Variant CSV2_3. 464 * 0b0000 - Feature FEAT_CSV2 is not implemented. 465 * 0b0001 - Feature FEAT_CSV2 is implemented, but FEAT_CSV2_2 and FEAT_CSV2_3 466 * are not implemented. 467 * 0b0010 - Feature FEAT_CSV2_2 is implemented but FEAT_CSV2_3 is not 468 * implemented. 469 * 0b0011 - Feature FEAT_CSV2_3 is implemented. 470 */ 471 472 CREATE_FEATURE_FUNCS(feat_csv2_2, id_aa64pfr0_el1, ID_AA64PFR0_CSV2_SHIFT, 473 ID_AA64PFR0_CSV2_MASK, CSV2_2_IMPLEMENTED, ENABLE_FEAT_CSV2_2) 474 CREATE_FEATURE_FUNCS(feat_csv2_3, id_aa64pfr0_el1, ID_AA64PFR0_CSV2_SHIFT, 475 ID_AA64PFR0_CSV2_MASK, CSV2_3_IMPLEMENTED, ENABLE_FEAT_CSV2_3) 476 477 /* FEAT_SPE: Statistical Profiling Extension */ 478 CREATE_FEATURE_FUNCS(feat_spe, id_aa64dfr0_el1, ID_AA64DFR0_PMS_SHIFT, 479 ID_AA64DFR0_PMS_MASK, 1U, ENABLE_SPE_FOR_NS) 480 481 /* FEAT_SVE: Scalable Vector Extension */ 482 CREATE_FEATURE_FUNCS(feat_sve, id_aa64pfr0_el1, ID_AA64PFR0_SVE_SHIFT, 483 ID_AA64PFR0_SVE_MASK, 1U, ENABLE_SVE_FOR_NS) 484 485 /* FEAT_RAS: Reliability, Accessibility, Serviceability */ 486 CREATE_FEATURE_FUNCS(feat_ras, id_aa64pfr0_el1, ID_AA64PFR0_RAS_SHIFT, 487 ID_AA64PFR0_RAS_MASK, 1U, ENABLE_FEAT_RAS) 488 489 /* FEAT_DIT: Data Independent Timing instructions */ 490 CREATE_FEATURE_FUNCS(feat_dit, id_aa64pfr0_el1, ID_AA64PFR0_DIT_SHIFT, 491 ID_AA64PFR0_DIT_MASK, 1U, ENABLE_FEAT_DIT) 492 493 /* FEAT_SYS_REG_TRACE */ 494 CREATE_FEATURE_FUNCS(feat_sys_reg_trace, id_aa64dfr0_el1, ID_AA64DFR0_TRACEVER_SHIFT, 495 ID_AA64DFR0_TRACEVER_MASK, 1U, ENABLE_SYS_REG_TRACE_FOR_NS) 496 497 /* FEAT_TRF: TraceFilter */ 498 CREATE_FEATURE_FUNCS(feat_trf, id_aa64dfr0_el1, ID_AA64DFR0_TRACEFILT_SHIFT, 499 ID_AA64DFR0_TRACEFILT_MASK, 1U, ENABLE_TRF_FOR_NS) 500 501 /* FEAT_NV2: Enhanced Nested Virtualization */ 502 CREATE_FEATURE_FUNCS(feat_nv2, id_aa64mmfr2_el1, ID_AA64MMFR2_EL1_NV_SHIFT, 503 ID_AA64MMFR2_EL1_NV_MASK, NV2_IMPLEMENTED, CTX_INCLUDE_NEVE_REGS) 504 505 /* FEAT_BRBE: Branch Record Buffer Extension */ 506 CREATE_FEATURE_FUNCS(feat_brbe, id_aa64dfr0_el1, ID_AA64DFR0_BRBE_SHIFT, 507 ID_AA64DFR0_BRBE_MASK, 1U, ENABLE_BRBE_FOR_NS) 508 509 /* FEAT_TRBE: Trace Buffer Extension */ 510 CREATE_FEATURE_FUNCS(feat_trbe, id_aa64dfr0_el1, ID_AA64DFR0_TRACEBUFFER_SHIFT, 511 ID_AA64DFR0_TRACEBUFFER_MASK, 1U, ENABLE_TRBE_FOR_NS) 512 513 /* FEAT_SME_FA64: Full A64 Instruction support in streaming SVE mode */ 514 CREATE_FEATURE_PRESENT(feat_sme_fa64, id_aa64smfr0_el1, ID_AA64SMFR0_EL1_SME_FA64_SHIFT, 515 ID_AA64SMFR0_EL1_SME_FA64_MASK, 1U) 516 517 /* FEAT_SMEx: Scalar Matrix Extension */ 518 CREATE_FEATURE_FUNCS(feat_sme, id_aa64pfr1_el1, ID_AA64PFR1_EL1_SME_SHIFT, 519 ID_AA64PFR1_EL1_SME_MASK, 1U, ENABLE_SME_FOR_NS) 520 521 CREATE_FEATURE_FUNCS(feat_sme2, id_aa64pfr1_el1, ID_AA64PFR1_EL1_SME_SHIFT, 522 ID_AA64PFR1_EL1_SME_MASK, SME2_IMPLEMENTED, ENABLE_SME2_FOR_NS) 523 524 /* FEAT_LS64_ACCDATA: */ 525 CREATE_FEATURE_FUNCS(feat_ls64_accdata, id_aa64isar1_el1, ID_AA64ISAR1_LS64_SHIFT, 526 ID_AA64ISAR1_LS64_MASK, LS64_ACCDATA_IMPLEMENTED, 527 ENABLE_FEAT_LS64_ACCDATA) 528 529 /* FEAT_AIE: */ 530 CREATE_FEATURE_FUNCS(feat_aie, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_AIE_SHIFT, 531 ID_AA64MMFR3_EL1_AIE_MASK, 1U, ENABLE_FEAT_AIE) 532 533 /* FEAT_PFAR: */ 534 CREATE_FEATURE_FUNCS(feat_pfar, id_aa64pfr1_el1, ID_AA64PFR1_EL1_PFAR_SHIFT, 535 ID_AA64PFR1_EL1_PFAR_MASK, 1U, ENABLE_FEAT_PFAR) 536 537 /******************************************************************************* 538 * Function to get hardware granularity support 539 ******************************************************************************/ 540 541 __attribute__((always_inline)) 542 static inline bool is_feat_tgran4K_present(void) 543 { 544 unsigned int tgranx = ISOLATE_FIELD(read_id_aa64mmfr0_el1(), 545 ID_AA64MMFR0_EL1_TGRAN4_SHIFT, ID_REG_FIELD_MASK); 546 return (tgranx < 8U); 547 } 548 549 CREATE_FEATURE_PRESENT(feat_tgran16K, id_aa64mmfr0_el1, ID_AA64MMFR0_EL1_TGRAN16_SHIFT, 550 ID_AA64MMFR0_EL1_TGRAN16_MASK, TGRAN16_IMPLEMENTED) 551 552 __attribute__((always_inline)) 553 static inline bool is_feat_tgran64K_present(void) 554 { 555 unsigned int tgranx = ISOLATE_FIELD(read_id_aa64mmfr0_el1(), 556 ID_AA64MMFR0_EL1_TGRAN64_SHIFT, ID_REG_FIELD_MASK); 557 return (tgranx < 8U); 558 } 559 560 /* FEAT_PMUV3 */ 561 CREATE_FEATURE_PRESENT(feat_pmuv3, id_aa64dfr0_el1, ID_AA64DFR0_PMUVER_SHIFT, 562 ID_AA64DFR0_PMUVER_MASK, 1U) 563 564 /* FEAT_MTPMU */ 565 __attribute__((always_inline)) 566 static inline bool is_feat_mtpmu_present(void) 567 { 568 unsigned int mtpmu = ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_MTPMU_SHIFT, 569 ID_AA64DFR0_MTPMU_MASK); 570 return (mtpmu != 0U) && (mtpmu != MTPMU_NOT_IMPLEMENTED); 571 } 572 573 CREATE_FEATURE_SUPPORTED(feat_mtpmu, is_feat_mtpmu_present, DISABLE_MTPMU) 574 575 /************************************************************************* 576 * Function to identify the presence of FEAT_GCIE (GICv5 CPU interface 577 * extension). 578 ************************************************************************/ 579 CREATE_FEATURE_FUNCS(feat_gcie, id_aa64pfr2_el1, ID_AA64PFR2_EL1_GCIE_SHIFT, 580 ID_AA64PFR2_EL1_GCIE_MASK, 1U, ENABLE_FEAT_GCIE) 581 582 CREATE_FEATURE_FUNCS(feat_cpa2, id_aa64isar3_el1, ID_AA64ISAR3_EL1_CPA_SHIFT, 583 ID_AA64ISAR3_EL1_CPA_MASK, CPA2_IMPLEMENTED, 584 ENABLE_FEAT_CPA2) 585 586 #endif /* ARCH_FEATURES_H */ 587