1 /* 2 * Copyright (c) 2019-2023, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef ARCH_FEATURES_H 8 #define ARCH_FEATURES_H 9 10 #include <stdbool.h> 11 12 #include <arch_helpers.h> 13 #include <common/feat_detect.h> 14 15 #define ISOLATE_FIELD(reg, feat) \ 16 ((unsigned int)(((reg) >> (feat ## _SHIFT)) & (feat ## _MASK))) 17 18 static inline bool is_armv7_gentimer_present(void) 19 { 20 /* The Generic Timer is always present in an ARMv8-A implementation */ 21 return true; 22 } 23 24 static inline bool is_armv8_1_pan_present(void) 25 { 26 return ((read_id_aa64mmfr1_el1() >> ID_AA64MMFR1_EL1_PAN_SHIFT) & 27 ID_AA64MMFR1_EL1_PAN_MASK) != 0U; 28 } 29 30 static inline unsigned int read_feat_vhe_id_field(void) 31 { 32 return ISOLATE_FIELD(read_id_aa64mmfr1_el1(), ID_AA64MMFR1_EL1_VHE); 33 } 34 35 static inline bool is_feat_vhe_supported(void) 36 { 37 if (ENABLE_FEAT_VHE == FEAT_STATE_DISABLED) { 38 return false; 39 } 40 41 if (ENABLE_FEAT_VHE == FEAT_STATE_ALWAYS) { 42 return true; 43 } 44 45 return read_feat_vhe_id_field() != 0U; 46 } 47 48 static inline bool is_armv8_2_ttcnp_present(void) 49 { 50 return ((read_id_aa64mmfr2_el1() >> ID_AA64MMFR2_EL1_CNP_SHIFT) & 51 ID_AA64MMFR2_EL1_CNP_MASK) != 0U; 52 } 53 54 static inline bool is_feat_pacqarma3_present(void) 55 { 56 uint64_t mask_id_aa64isar2 = 57 (ID_AA64ISAR2_GPA3_MASK << ID_AA64ISAR2_GPA3_SHIFT) | 58 (ID_AA64ISAR2_APA3_MASK << ID_AA64ISAR2_APA3_SHIFT); 59 60 /* If any of the fields is not zero, QARMA3 algorithm is present */ 61 return (read_id_aa64isar2_el1() & mask_id_aa64isar2) != 0U; 62 } 63 64 static inline bool is_armv8_3_pauth_present(void) 65 { 66 uint64_t mask_id_aa64isar1 = 67 (ID_AA64ISAR1_GPI_MASK << ID_AA64ISAR1_GPI_SHIFT) | 68 (ID_AA64ISAR1_GPA_MASK << ID_AA64ISAR1_GPA_SHIFT) | 69 (ID_AA64ISAR1_API_MASK << ID_AA64ISAR1_API_SHIFT) | 70 (ID_AA64ISAR1_APA_MASK << ID_AA64ISAR1_APA_SHIFT); 71 72 /* 73 * If any of the fields is not zero or QARMA3 is present, 74 * PAuth is present 75 */ 76 return ((read_id_aa64isar1_el1() & mask_id_aa64isar1) != 0U || 77 is_feat_pacqarma3_present()); 78 } 79 80 static inline bool is_armv8_4_dit_present(void) 81 { 82 return ((read_id_aa64pfr0_el1() >> ID_AA64PFR0_DIT_SHIFT) & 83 ID_AA64PFR0_DIT_MASK) == 1U; 84 } 85 86 static inline bool is_armv8_4_ttst_present(void) 87 { 88 return ((read_id_aa64mmfr2_el1() >> ID_AA64MMFR2_EL1_ST_SHIFT) & 89 ID_AA64MMFR2_EL1_ST_MASK) == 1U; 90 } 91 92 static inline bool is_armv8_5_bti_present(void) 93 { 94 return ((read_id_aa64pfr1_el1() >> ID_AA64PFR1_EL1_BT_SHIFT) & 95 ID_AA64PFR1_EL1_BT_MASK) == BTI_IMPLEMENTED; 96 } 97 98 static inline unsigned int get_armv8_5_mte_support(void) 99 { 100 return ((read_id_aa64pfr1_el1() >> ID_AA64PFR1_EL1_MTE_SHIFT) & 101 ID_AA64PFR1_EL1_MTE_MASK); 102 } 103 104 static inline bool is_armv8_4_sel2_present(void) 105 { 106 return ((read_id_aa64pfr0_el1() >> ID_AA64PFR0_SEL2_SHIFT) & 107 ID_AA64PFR0_SEL2_MASK) == 1ULL; 108 } 109 110 static inline bool is_armv8_6_twed_present(void) 111 { 112 return (((read_id_aa64mmfr1_el1() >> ID_AA64MMFR1_EL1_TWED_SHIFT) & 113 ID_AA64MMFR1_EL1_TWED_MASK) == ID_AA64MMFR1_EL1_TWED_SUPPORTED); 114 } 115 116 static unsigned int read_feat_fgt_id_field(void) 117 { 118 return ISOLATE_FIELD(read_id_aa64mmfr0_el1(), ID_AA64MMFR0_EL1_FGT); 119 } 120 121 static inline bool is_feat_fgt_supported(void) 122 { 123 if (ENABLE_FEAT_FGT == FEAT_STATE_DISABLED) { 124 return false; 125 } 126 127 if (ENABLE_FEAT_FGT == FEAT_STATE_ALWAYS) { 128 return true; 129 } 130 131 return read_feat_fgt_id_field() != 0U; 132 } 133 134 static inline unsigned long int get_armv8_6_ecv_support(void) 135 { 136 return ((read_id_aa64mmfr0_el1() >> ID_AA64MMFR0_EL1_ECV_SHIFT) & 137 ID_AA64MMFR0_EL1_ECV_MASK); 138 } 139 140 static inline bool is_armv8_5_rng_present(void) 141 { 142 return ((read_id_aa64isar0_el1() >> ID_AA64ISAR0_RNDR_SHIFT) & 143 ID_AA64ISAR0_RNDR_MASK); 144 } 145 146 static unsigned int read_feat_tcrx_id_field(void) 147 { 148 return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_TCRX); 149 } 150 151 static inline bool is_feat_tcr2_supported(void) 152 { 153 if (ENABLE_FEAT_TCR2 == FEAT_STATE_DISABLED) { 154 return false; 155 } 156 157 if (ENABLE_FEAT_TCR2 == FEAT_STATE_ALWAYS) { 158 return true; 159 } 160 161 return read_feat_tcrx_id_field() != 0U; 162 } 163 164 /******************************************************************************* 165 * Functions to identify the presence of the Activity Monitors Extension 166 ******************************************************************************/ 167 static unsigned int read_feat_amu_id_field(void) 168 { 169 return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_AMU); 170 } 171 172 static inline bool is_feat_amu_supported(void) 173 { 174 if (ENABLE_FEAT_AMUv1 == FEAT_STATE_DISABLED) { 175 return false; 176 } 177 178 if (ENABLE_FEAT_AMUv1 == FEAT_STATE_ALWAYS) { 179 return true; 180 } 181 182 return read_feat_amu_id_field() >= ID_AA64PFR0_AMU_V1; 183 } 184 185 static inline bool is_armv8_6_feat_amuv1p1_present(void) 186 { 187 return read_feat_amu_id_field() >= ID_AA64PFR0_AMU_V1P1; 188 } 189 190 /* 191 * Return MPAM version: 192 * 193 * 0x00: None Armv8.0 or later 194 * 0x01: v0.1 Armv8.4 or later 195 * 0x10: v1.0 Armv8.2 or later 196 * 0x11: v1.1 Armv8.4 or later 197 * 198 */ 199 static inline unsigned int read_feat_mpam_version(void) 200 { 201 return (unsigned int)((((read_id_aa64pfr0_el1() >> 202 ID_AA64PFR0_MPAM_SHIFT) & ID_AA64PFR0_MPAM_MASK) << 4) | 203 ((read_id_aa64pfr1_el1() >> 204 ID_AA64PFR1_MPAM_FRAC_SHIFT) & ID_AA64PFR1_MPAM_FRAC_MASK)); 205 } 206 207 static inline bool is_feat_mpam_supported(void) 208 { 209 if (ENABLE_MPAM_FOR_LOWER_ELS == FEAT_STATE_DISABLED) { 210 return false; 211 } 212 213 if (ENABLE_MPAM_FOR_LOWER_ELS == FEAT_STATE_ALWAYS) { 214 return true; 215 } 216 217 return read_feat_mpam_version() != 0U; 218 } 219 220 static inline unsigned int read_feat_hcx_id_field(void) 221 { 222 return ISOLATE_FIELD(read_id_aa64mmfr1_el1(), ID_AA64MMFR1_EL1_HCX); 223 } 224 225 static inline bool is_feat_hcx_supported(void) 226 { 227 if (ENABLE_FEAT_HCX == FEAT_STATE_DISABLED) { 228 return false; 229 } 230 231 if (ENABLE_FEAT_HCX == FEAT_STATE_ALWAYS) { 232 return true; 233 } 234 235 return read_feat_hcx_id_field() != 0U; 236 } 237 238 static inline bool is_feat_rng_trap_present(void) 239 { 240 return (((read_id_aa64pfr1_el1() >> ID_AA64PFR1_EL1_RNDR_TRAP_SHIFT) & 241 ID_AA64PFR1_EL1_RNDR_TRAP_MASK) 242 == ID_AA64PFR1_EL1_RNG_TRAP_SUPPORTED); 243 } 244 245 static inline unsigned int get_armv9_2_feat_rme_support(void) 246 { 247 /* 248 * Return the RME version, zero if not supported. This function can be 249 * used as both an integer value for the RME version or compared to zero 250 * to detect RME presence. 251 */ 252 return (unsigned int)(read_id_aa64pfr0_el1() >> 253 ID_AA64PFR0_FEAT_RME_SHIFT) & ID_AA64PFR0_FEAT_RME_MASK; 254 } 255 256 /********************************************************************************* 257 * Function to identify the presence of FEAT_SB (Speculation Barrier Instruction) 258 ********************************************************************************/ 259 static inline unsigned int read_feat_sb_id_field(void) 260 { 261 return ISOLATE_FIELD(read_id_aa64isar1_el1(), ID_AA64ISAR1_SB); 262 } 263 264 /********************************************************************************* 265 * Function to identify the presence of FEAT_CSV2_2 (Cache Speculation Variant 2) 266 ********************************************************************************/ 267 static inline bool is_armv8_0_feat_csv2_2_present(void) 268 { 269 return (((read_id_aa64pfr0_el1() >> ID_AA64PFR0_CSV2_SHIFT) & 270 ID_AA64PFR0_CSV2_MASK) == ID_AA64PFR0_CSV2_2_SUPPORTED); 271 } 272 273 /********************************************************************************** 274 * Function to identify the presence of FEAT_SPE (Statistical Profiling Extension) 275 *********************************************************************************/ 276 static inline unsigned int read_feat_spe_id_field(void) 277 { 278 return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_PMS); 279 } 280 281 static inline bool is_feat_spe_supported(void) 282 { 283 if (ENABLE_SPE_FOR_NS == FEAT_STATE_DISABLED) { 284 return false; 285 } 286 287 if (ENABLE_SPE_FOR_NS == FEAT_STATE_ALWAYS) { 288 return true; 289 } 290 291 return read_feat_spe_id_field() != 0U; 292 } 293 294 /******************************************************************************* 295 * Function to identify the presence of FEAT_SVE (Scalable Vector Extension) 296 ******************************************************************************/ 297 static inline bool is_armv8_2_feat_sve_present(void) 298 { 299 return (((read_id_aa64pfr0_el1() >> ID_AA64PFR0_SVE_SHIFT) & 300 ID_AA64PFR0_SVE_MASK) == ID_AA64PFR0_SVE_SUPPORTED); 301 } 302 303 /******************************************************************************* 304 * Function to identify the presence of FEAT_RAS (Reliability,Availability, 305 * and Serviceability Extension) 306 ******************************************************************************/ 307 static inline bool is_armv8_2_feat_ras_present(void) 308 { 309 return (((read_id_aa64pfr0_el1() >> ID_AA64PFR0_RAS_SHIFT) & 310 ID_AA64PFR0_RAS_MASK) != ID_AA64PFR0_RAS_NOT_SUPPORTED); 311 } 312 313 /************************************************************************** 314 * Function to identify the presence of FEAT_DIT (Data Independent Timing) 315 *************************************************************************/ 316 static inline bool is_armv8_4_feat_dit_present(void) 317 { 318 return (((read_id_aa64pfr0_el1() >> ID_AA64PFR0_DIT_SHIFT) & 319 ID_AA64PFR0_DIT_MASK) == ID_AA64PFR0_DIT_SUPPORTED); 320 } 321 322 static inline unsigned int read_feat_tracever_id_field(void) 323 { 324 return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_TRACEVER); 325 } 326 327 static inline bool is_feat_sys_reg_trace_supported(void) 328 { 329 if (ENABLE_SYS_REG_TRACE_FOR_NS == FEAT_STATE_DISABLED) { 330 return false; 331 } 332 333 if (ENABLE_SYS_REG_TRACE_FOR_NS == FEAT_STATE_ALWAYS) { 334 return true; 335 } 336 337 return read_feat_tracever_id_field() != 0U; 338 } 339 340 /************************************************************************* 341 * Function to identify the presence of FEAT_TRF (TraceLift) 342 ************************************************************************/ 343 static inline unsigned int read_feat_trf_id_field(void) 344 { 345 return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_TRACEFILT); 346 } 347 348 static inline bool is_feat_trf_supported(void) 349 { 350 if (ENABLE_TRF_FOR_NS == FEAT_STATE_DISABLED) { 351 return false; 352 } 353 354 if (ENABLE_TRF_FOR_NS == FEAT_STATE_ALWAYS) { 355 return true; 356 } 357 358 return read_feat_trf_id_field() != 0U; 359 } 360 361 /******************************************************************************** 362 * Function to identify the presence of FEAT_NV2 (Enhanced Nested Virtualization 363 * Support) 364 *******************************************************************************/ 365 static inline unsigned int get_armv8_4_feat_nv_support(void) 366 { 367 return (((read_id_aa64mmfr2_el1() >> ID_AA64MMFR2_EL1_NV_SHIFT) & 368 ID_AA64MMFR2_EL1_NV_MASK)); 369 } 370 371 /******************************************************************************* 372 * Function to identify the presence of FEAT_BRBE (Branch Record Buffer 373 * Extension) 374 ******************************************************************************/ 375 static inline unsigned int read_feat_brbe_id_field(void) 376 { 377 return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_BRBE); 378 } 379 380 static inline bool is_feat_brbe_supported(void) 381 { 382 if (ENABLE_BRBE_FOR_NS == FEAT_STATE_DISABLED) { 383 return false; 384 } 385 386 if (ENABLE_BRBE_FOR_NS == FEAT_STATE_ALWAYS) { 387 return true; 388 } 389 390 return read_feat_brbe_id_field() != 0U; 391 } 392 393 /******************************************************************************* 394 * Function to identify the presence of FEAT_TRBE (Trace Buffer Extension) 395 ******************************************************************************/ 396 static inline unsigned int read_feat_trbe_id_field(void) 397 { 398 return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_TRACEBUFFER); 399 } 400 401 static inline bool is_feat_trbe_supported(void) 402 { 403 if (ENABLE_TRBE_FOR_NS == FEAT_STATE_DISABLED) { 404 return false; 405 } 406 407 if (ENABLE_TRBE_FOR_NS == FEAT_STATE_ALWAYS) { 408 return true; 409 } 410 411 return read_feat_trbe_id_field() != 0U; 412 413 } 414 #endif /* ARCH_FEATURES_H */ 415