1 /* 2 * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2020-2022, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef ARCH_H 9 #define ARCH_H 10 11 #include <lib/utils_def.h> 12 13 /******************************************************************************* 14 * MIDR bit definitions 15 ******************************************************************************/ 16 #define MIDR_IMPL_MASK U(0xff) 17 #define MIDR_IMPL_SHIFT U(0x18) 18 #define MIDR_VAR_SHIFT U(20) 19 #define MIDR_VAR_BITS U(4) 20 #define MIDR_VAR_MASK U(0xf) 21 #define MIDR_REV_SHIFT U(0) 22 #define MIDR_REV_BITS U(4) 23 #define MIDR_REV_MASK U(0xf) 24 #define MIDR_PN_MASK U(0xfff) 25 #define MIDR_PN_SHIFT U(0x4) 26 27 /******************************************************************************* 28 * MPIDR macros 29 ******************************************************************************/ 30 #define MPIDR_MT_MASK (ULL(1) << 24) 31 #define MPIDR_CPU_MASK MPIDR_AFFLVL_MASK 32 #define MPIDR_CLUSTER_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS) 33 #define MPIDR_AFFINITY_BITS U(8) 34 #define MPIDR_AFFLVL_MASK ULL(0xff) 35 #define MPIDR_AFF0_SHIFT U(0) 36 #define MPIDR_AFF1_SHIFT U(8) 37 #define MPIDR_AFF2_SHIFT U(16) 38 #define MPIDR_AFF3_SHIFT U(32) 39 #define MPIDR_AFF_SHIFT(_n) MPIDR_AFF##_n##_SHIFT 40 #define MPIDR_AFFINITY_MASK ULL(0xff00ffffff) 41 #define MPIDR_AFFLVL_SHIFT U(3) 42 #define MPIDR_AFFLVL0 ULL(0x0) 43 #define MPIDR_AFFLVL1 ULL(0x1) 44 #define MPIDR_AFFLVL2 ULL(0x2) 45 #define MPIDR_AFFLVL3 ULL(0x3) 46 #define MPIDR_AFFLVL(_n) MPIDR_AFFLVL##_n 47 #define MPIDR_AFFLVL0_VAL(mpidr) \ 48 (((mpidr) >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK) 49 #define MPIDR_AFFLVL1_VAL(mpidr) \ 50 (((mpidr) >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK) 51 #define MPIDR_AFFLVL2_VAL(mpidr) \ 52 (((mpidr) >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK) 53 #define MPIDR_AFFLVL3_VAL(mpidr) \ 54 (((mpidr) >> MPIDR_AFF3_SHIFT) & MPIDR_AFFLVL_MASK) 55 /* 56 * The MPIDR_MAX_AFFLVL count starts from 0. Take care to 57 * add one while using this macro to define array sizes. 58 * TODO: Support only the first 3 affinity levels for now. 59 */ 60 #define MPIDR_MAX_AFFLVL U(2) 61 62 #define MPID_MASK (MPIDR_MT_MASK | \ 63 (MPIDR_AFFLVL_MASK << MPIDR_AFF3_SHIFT) | \ 64 (MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT) | \ 65 (MPIDR_AFFLVL_MASK << MPIDR_AFF1_SHIFT) | \ 66 (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT)) 67 68 #define MPIDR_AFF_ID(mpid, n) \ 69 (((mpid) >> MPIDR_AFF_SHIFT(n)) & MPIDR_AFFLVL_MASK) 70 71 /* 72 * An invalid MPID. This value can be used by functions that return an MPID to 73 * indicate an error. 74 */ 75 #define INVALID_MPID U(0xFFFFFFFF) 76 77 /******************************************************************************* 78 * Definitions for CPU system register interface to GICv3 79 ******************************************************************************/ 80 #define ICC_IGRPEN1_EL1 S3_0_C12_C12_7 81 #define ICC_SGI1R S3_0_C12_C11_5 82 #define ICC_ASGI1R S3_0_C12_C11_6 83 #define ICC_SRE_EL1 S3_0_C12_C12_5 84 #define ICC_SRE_EL2 S3_4_C12_C9_5 85 #define ICC_SRE_EL3 S3_6_C12_C12_5 86 #define ICC_CTLR_EL1 S3_0_C12_C12_4 87 #define ICC_CTLR_EL3 S3_6_C12_C12_4 88 #define ICC_PMR_EL1 S3_0_C4_C6_0 89 #define ICC_RPR_EL1 S3_0_C12_C11_3 90 #define ICC_IGRPEN1_EL3 S3_6_c12_c12_7 91 #define ICC_IGRPEN0_EL1 S3_0_c12_c12_6 92 #define ICC_HPPIR0_EL1 S3_0_c12_c8_2 93 #define ICC_HPPIR1_EL1 S3_0_c12_c12_2 94 #define ICC_IAR0_EL1 S3_0_c12_c8_0 95 #define ICC_IAR1_EL1 S3_0_c12_c12_0 96 #define ICC_EOIR0_EL1 S3_0_c12_c8_1 97 #define ICC_EOIR1_EL1 S3_0_c12_c12_1 98 #define ICC_SGI0R_EL1 S3_0_c12_c11_7 99 100 /******************************************************************************* 101 * Definitions for EL2 system registers for save/restore routine 102 ******************************************************************************/ 103 #define CNTPOFF_EL2 S3_4_C14_C0_6 104 #define HAFGRTR_EL2 S3_4_C3_C1_6 105 #define HDFGRTR_EL2 S3_4_C3_C1_4 106 #define HDFGWTR_EL2 S3_4_C3_C1_5 107 #define HFGITR_EL2 S3_4_C1_C1_6 108 #define HFGRTR_EL2 S3_4_C1_C1_4 109 #define HFGWTR_EL2 S3_4_C1_C1_5 110 #define ICH_HCR_EL2 S3_4_C12_C11_0 111 #define ICH_VMCR_EL2 S3_4_C12_C11_7 112 #define MPAMVPM0_EL2 S3_4_C10_C6_0 113 #define MPAMVPM1_EL2 S3_4_C10_C6_1 114 #define MPAMVPM2_EL2 S3_4_C10_C6_2 115 #define MPAMVPM3_EL2 S3_4_C10_C6_3 116 #define MPAMVPM4_EL2 S3_4_C10_C6_4 117 #define MPAMVPM5_EL2 S3_4_C10_C6_5 118 #define MPAMVPM6_EL2 S3_4_C10_C6_6 119 #define MPAMVPM7_EL2 S3_4_C10_C6_7 120 #define MPAMVPMV_EL2 S3_4_C10_C4_1 121 #define TRFCR_EL2 S3_4_C1_C2_1 122 #define VNCR_EL2 S3_4_C2_C2_0 123 #define PMSCR_EL2 S3_4_C9_C9_0 124 #define TFSR_EL2 S3_4_C5_C6_0 125 #define CONTEXTIDR_EL2 S3_4_C13_C0_1 126 #define TTBR1_EL2 S3_4_C2_C0_1 127 128 /******************************************************************************* 129 * Generic timer memory mapped registers & offsets 130 ******************************************************************************/ 131 #define CNTCR_OFF U(0x000) 132 #define CNTCV_OFF U(0x008) 133 #define CNTFID_OFF U(0x020) 134 135 #define CNTCR_EN (U(1) << 0) 136 #define CNTCR_HDBG (U(1) << 1) 137 #define CNTCR_FCREQ(x) ((x) << 8) 138 139 /******************************************************************************* 140 * System register bit definitions 141 ******************************************************************************/ 142 /* CLIDR definitions */ 143 #define LOUIS_SHIFT U(21) 144 #define LOC_SHIFT U(24) 145 #define CTYPE_SHIFT(n) U(3 * (n - 1)) 146 #define CLIDR_FIELD_WIDTH U(3) 147 148 /* CSSELR definitions */ 149 #define LEVEL_SHIFT U(1) 150 151 /* Data cache set/way op type defines */ 152 #define DCISW U(0x0) 153 #define DCCISW U(0x1) 154 #if ERRATA_A53_827319 155 #define DCCSW DCCISW 156 #else 157 #define DCCSW U(0x2) 158 #endif 159 160 /* ID_AA64PFR0_EL1 definitions */ 161 #define ID_AA64PFR0_EL0_SHIFT U(0) 162 #define ID_AA64PFR0_EL1_SHIFT U(4) 163 #define ID_AA64PFR0_EL2_SHIFT U(8) 164 #define ID_AA64PFR0_EL3_SHIFT U(12) 165 166 #define ID_AA64PFR0_AMU_SHIFT U(44) 167 #define ID_AA64PFR0_AMU_MASK ULL(0xf) 168 #define ID_AA64PFR0_AMU_NOT_SUPPORTED U(0x0) 169 #define ID_AA64PFR0_AMU_V1 ULL(0x1) 170 #define ID_AA64PFR0_AMU_V1P1 U(0x2) 171 172 #define ID_AA64PFR0_ELX_MASK ULL(0xf) 173 174 #define ID_AA64PFR0_GIC_SHIFT U(24) 175 #define ID_AA64PFR0_GIC_WIDTH U(4) 176 #define ID_AA64PFR0_GIC_MASK ULL(0xf) 177 178 #define ID_AA64PFR0_SVE_SHIFT U(32) 179 #define ID_AA64PFR0_SVE_MASK ULL(0xf) 180 #define ID_AA64PFR0_SVE_SUPPORTED ULL(0x1) 181 #define ID_AA64PFR0_SVE_LENGTH U(4) 182 183 #define ID_AA64PFR0_SEL2_SHIFT U(36) 184 #define ID_AA64PFR0_SEL2_MASK ULL(0xf) 185 186 #define ID_AA64PFR0_MPAM_SHIFT U(40) 187 #define ID_AA64PFR0_MPAM_MASK ULL(0xf) 188 189 #define ID_AA64PFR0_DIT_SHIFT U(48) 190 #define ID_AA64PFR0_DIT_MASK ULL(0xf) 191 #define ID_AA64PFR0_DIT_LENGTH U(4) 192 #define ID_AA64PFR0_DIT_SUPPORTED U(1) 193 194 #define ID_AA64PFR0_CSV2_SHIFT U(56) 195 #define ID_AA64PFR0_CSV2_MASK ULL(0xf) 196 #define ID_AA64PFR0_CSV2_LENGTH U(4) 197 #define ID_AA64PFR0_CSV2_2_SUPPORTED ULL(0x2) 198 199 #define ID_AA64PFR0_FEAT_RME_SHIFT U(52) 200 #define ID_AA64PFR0_FEAT_RME_MASK ULL(0xf) 201 #define ID_AA64PFR0_FEAT_RME_LENGTH U(4) 202 #define ID_AA64PFR0_FEAT_RME_NOT_SUPPORTED U(0) 203 #define ID_AA64PFR0_FEAT_RME_V1 U(1) 204 205 #define ID_AA64PFR0_RAS_SHIFT U(28) 206 #define ID_AA64PFR0_RAS_MASK ULL(0xf) 207 #define ID_AA64PFR0_RAS_NOT_SUPPORTED ULL(0x0) 208 #define ID_AA64PFR0_RAS_LENGTH U(4) 209 210 /* Exception level handling */ 211 #define EL_IMPL_NONE ULL(0) 212 #define EL_IMPL_A64ONLY ULL(1) 213 #define EL_IMPL_A64_A32 ULL(2) 214 215 /* ID_AA64DFR0_EL1.TraceVer definitions */ 216 #define ID_AA64DFR0_TRACEVER_SHIFT U(4) 217 #define ID_AA64DFR0_TRACEVER_MASK ULL(0xf) 218 #define ID_AA64DFR0_TRACEVER_SUPPORTED ULL(1) 219 #define ID_AA64DFR0_TRACEVER_LENGTH U(4) 220 #define ID_AA64DFR0_TRACEFILT_SHIFT U(40) 221 #define ID_AA64DFR0_TRACEFILT_MASK U(0xf) 222 #define ID_AA64DFR0_TRACEFILT_SUPPORTED U(1) 223 #define ID_AA64DFR0_TRACEFILT_LENGTH U(4) 224 225 /* ID_AA64DFR0_EL1.PMS definitions (for ARMv8.2+) */ 226 #define ID_AA64DFR0_PMS_SHIFT U(32) 227 #define ID_AA64DFR0_PMS_MASK ULL(0xf) 228 #define ID_AA64DFR0_SPE_SUPPORTED ULL(0x1) 229 #define ID_AA64DFR0_SPE_NOT_SUPPORTED ULL(0x0) 230 231 /* ID_AA64DFR0_EL1.TraceBuffer definitions */ 232 #define ID_AA64DFR0_TRACEBUFFER_SHIFT U(44) 233 #define ID_AA64DFR0_TRACEBUFFER_MASK ULL(0xf) 234 #define ID_AA64DFR0_TRACEBUFFER_SUPPORTED ULL(1) 235 236 /* ID_AA64DFR0_EL1.MTPMU definitions (for ARMv8.6+) */ 237 #define ID_AA64DFR0_MTPMU_SHIFT U(48) 238 #define ID_AA64DFR0_MTPMU_MASK ULL(0xf) 239 #define ID_AA64DFR0_MTPMU_SUPPORTED ULL(1) 240 241 /* ID_AA64DFR0_EL1.BRBE definitions */ 242 #define ID_AA64DFR0_BRBE_SHIFT U(52) 243 #define ID_AA64DFR0_BRBE_MASK ULL(0xf) 244 #define ID_AA64DFR0_BRBE_SUPPORTED ULL(1) 245 246 /* ID_AA64ISAR0_EL1 definitions */ 247 #define ID_AA64ISAR0_RNDR_SHIFT U(60) 248 #define ID_AA64ISAR0_RNDR_MASK ULL(0xf) 249 250 /* ID_AA64ISAR1_EL1 definitions */ 251 #define ID_AA64ISAR1_EL1 S3_0_C0_C6_1 252 253 #define ID_AA64ISAR1_GPI_SHIFT U(28) 254 #define ID_AA64ISAR1_GPI_MASK ULL(0xf) 255 #define ID_AA64ISAR1_GPA_SHIFT U(24) 256 #define ID_AA64ISAR1_GPA_MASK ULL(0xf) 257 258 #define ID_AA64ISAR1_API_SHIFT U(8) 259 #define ID_AA64ISAR1_API_MASK ULL(0xf) 260 #define ID_AA64ISAR1_APA_SHIFT U(4) 261 #define ID_AA64ISAR1_APA_MASK ULL(0xf) 262 263 #define ID_AA64ISAR1_SB_SHIFT U(36) 264 #define ID_AA64ISAR1_SB_MASK ULL(0xf) 265 #define ID_AA64ISAR1_SB_SUPPORTED ULL(0x1) 266 #define ID_AA64ISAR1_SB_NOT_SUPPORTED ULL(0x0) 267 268 /* ID_AA64ISAR2_EL1 definitions */ 269 #define ID_AA64ISAR2_EL1 S3_0_C0_C6_2 270 271 #define ID_AA64ISAR2_GPA3_SHIFT U(8) 272 #define ID_AA64ISAR2_GPA3_MASK ULL(0xf) 273 274 #define ID_AA64ISAR2_APA3_SHIFT U(12) 275 #define ID_AA64ISAR2_APA3_MASK ULL(0xf) 276 277 /* ID_AA64MMFR0_EL1 definitions */ 278 #define ID_AA64MMFR0_EL1_PARANGE_SHIFT U(0) 279 #define ID_AA64MMFR0_EL1_PARANGE_MASK ULL(0xf) 280 281 #define PARANGE_0000 U(32) 282 #define PARANGE_0001 U(36) 283 #define PARANGE_0010 U(40) 284 #define PARANGE_0011 U(42) 285 #define PARANGE_0100 U(44) 286 #define PARANGE_0101 U(48) 287 #define PARANGE_0110 U(52) 288 289 #define ID_AA64MMFR0_EL1_ECV_SHIFT U(60) 290 #define ID_AA64MMFR0_EL1_ECV_MASK ULL(0xf) 291 #define ID_AA64MMFR0_EL1_ECV_NOT_SUPPORTED ULL(0x0) 292 #define ID_AA64MMFR0_EL1_ECV_SUPPORTED ULL(0x1) 293 #define ID_AA64MMFR0_EL1_ECV_SELF_SYNCH ULL(0x2) 294 295 #define ID_AA64MMFR0_EL1_FGT_SHIFT U(56) 296 #define ID_AA64MMFR0_EL1_FGT_MASK ULL(0xf) 297 #define ID_AA64MMFR0_EL1_FGT_SUPPORTED ULL(0x1) 298 #define ID_AA64MMFR0_EL1_FGT_NOT_SUPPORTED ULL(0x0) 299 300 #define ID_AA64MMFR0_EL1_TGRAN4_SHIFT U(28) 301 #define ID_AA64MMFR0_EL1_TGRAN4_MASK ULL(0xf) 302 #define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED ULL(0x0) 303 #define ID_AA64MMFR0_EL1_TGRAN4_52B_SUPPORTED ULL(0x1) 304 #define ID_AA64MMFR0_EL1_TGRAN4_NOT_SUPPORTED ULL(0xf) 305 306 #define ID_AA64MMFR0_EL1_TGRAN64_SHIFT U(24) 307 #define ID_AA64MMFR0_EL1_TGRAN64_MASK ULL(0xf) 308 #define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED ULL(0x0) 309 #define ID_AA64MMFR0_EL1_TGRAN64_NOT_SUPPORTED ULL(0xf) 310 311 #define ID_AA64MMFR0_EL1_TGRAN16_SHIFT U(20) 312 #define ID_AA64MMFR0_EL1_TGRAN16_MASK ULL(0xf) 313 #define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED ULL(0x1) 314 #define ID_AA64MMFR0_EL1_TGRAN16_NOT_SUPPORTED ULL(0x0) 315 #define ID_AA64MMFR0_EL1_TGRAN16_52B_SUPPORTED ULL(0x2) 316 317 /* ID_AA64MMFR1_EL1 definitions */ 318 #define ID_AA64MMFR1_EL1_TWED_SHIFT U(32) 319 #define ID_AA64MMFR1_EL1_TWED_MASK ULL(0xf) 320 #define ID_AA64MMFR1_EL1_TWED_SUPPORTED ULL(0x1) 321 #define ID_AA64MMFR1_EL1_TWED_NOT_SUPPORTED ULL(0x0) 322 323 #define ID_AA64MMFR1_EL1_PAN_SHIFT U(20) 324 #define ID_AA64MMFR1_EL1_PAN_MASK ULL(0xf) 325 #define ID_AA64MMFR1_EL1_PAN_NOT_SUPPORTED ULL(0x0) 326 #define ID_AA64MMFR1_EL1_PAN_SUPPORTED ULL(0x1) 327 #define ID_AA64MMFR1_EL1_PAN2_SUPPORTED ULL(0x2) 328 #define ID_AA64MMFR1_EL1_PAN3_SUPPORTED ULL(0x3) 329 330 #define ID_AA64MMFR1_EL1_VHE_SHIFT U(8) 331 #define ID_AA64MMFR1_EL1_VHE_MASK ULL(0xf) 332 333 #define ID_AA64MMFR1_EL1_HCX_SHIFT U(40) 334 #define ID_AA64MMFR1_EL1_HCX_MASK ULL(0xf) 335 #define ID_AA64MMFR1_EL1_HCX_SUPPORTED ULL(0x1) 336 #define ID_AA64MMFR1_EL1_HCX_NOT_SUPPORTED ULL(0x0) 337 338 /* ID_AA64MMFR2_EL1 definitions */ 339 #define ID_AA64MMFR2_EL1 S3_0_C0_C7_2 340 341 #define ID_AA64MMFR2_EL1_ST_SHIFT U(28) 342 #define ID_AA64MMFR2_EL1_ST_MASK ULL(0xf) 343 344 #define ID_AA64MMFR2_EL1_CCIDX_SHIFT U(20) 345 #define ID_AA64MMFR2_EL1_CCIDX_MASK ULL(0xf) 346 #define ID_AA64MMFR2_EL1_CCIDX_LENGTH U(4) 347 348 #define ID_AA64MMFR2_EL1_CNP_SHIFT U(0) 349 #define ID_AA64MMFR2_EL1_CNP_MASK ULL(0xf) 350 351 #define ID_AA64MMFR2_EL1_NV_SHIFT U(24) 352 #define ID_AA64MMFR2_EL1_NV_MASK ULL(0xf) 353 #define ID_AA64MMFR2_EL1_NV_NOT_SUPPORTED ULL(0x0) 354 #define ID_AA64MMFR2_EL1_NV_SUPPORTED ULL(0x1) 355 #define ID_AA64MMFR2_EL1_NV2_SUPPORTED ULL(0x2) 356 357 /* ID_AA64MMFR3_EL1 definitions */ 358 #define ID_AA64MMFR3_EL1 S3_0_C0_C7_3 359 360 #define ID_AA64MMFR3_EL1_S2POE_SHIFT U(20) 361 #define ID_AA64MMFR3_EL1_S2POE_MASK ULL(0xf) 362 363 #define ID_AA64MMFR3_EL1_S1POE_SHIFT U(16) 364 #define ID_AA64MMFR3_EL1_S1POE_MASK ULL(0xf) 365 366 #define ID_AA64MMFR3_EL1_S2PIE_SHIFT U(12) 367 #define ID_AA64MMFR3_EL1_S2PIE_MASK ULL(0xf) 368 369 #define ID_AA64MMFR3_EL1_S1PIE_SHIFT U(8) 370 #define ID_AA64MMFR3_EL1_S1PIE_MASK ULL(0xf) 371 372 #define ID_AA64MMFR3_EL1_TCRX_SHIFT U(0) 373 #define ID_AA64MMFR3_EL1_TCRX_MASK ULL(0xf) 374 375 /* ID_AA64PFR1_EL1 definitions */ 376 #define ID_AA64PFR1_EL1_GCS_SHIFT U(44) 377 #define ID_AA64PFR1_EL1_GCS_MASK ULL(0xf) 378 379 #define ID_AA64PFR1_EL1_SSBS_SHIFT U(4) 380 #define ID_AA64PFR1_EL1_SSBS_MASK ULL(0xf) 381 382 #define SSBS_UNAVAILABLE ULL(0) /* No architectural SSBS support */ 383 384 #define ID_AA64PFR1_EL1_BT_SHIFT U(0) 385 #define ID_AA64PFR1_EL1_BT_MASK ULL(0xf) 386 387 #define BTI_IMPLEMENTED ULL(1) /* The BTI mechanism is implemented */ 388 389 #define ID_AA64PFR1_EL1_MTE_SHIFT U(8) 390 #define ID_AA64PFR1_EL1_MTE_MASK ULL(0xf) 391 392 #define ID_AA64PFR1_EL1_RNDR_TRAP_SHIFT U(28) 393 #define ID_AA64PFR1_EL1_RNDR_TRAP_MASK U(0xf) 394 395 #define ID_AA64PFR1_EL1_RNG_TRAP_SUPPORTED ULL(0x1) 396 #define ID_AA64PFR1_EL1_RNG_TRAP_NOT_SUPPORTED ULL(0x0) 397 398 #define VDISR_EL2 S3_4_C12_C1_1 399 #define VSESR_EL2 S3_4_C5_C2_3 400 401 /* Memory Tagging Extension is not implemented */ 402 #define MTE_UNIMPLEMENTED U(0) 403 /* FEAT_MTE: MTE instructions accessible at EL0 are implemented */ 404 #define MTE_IMPLEMENTED_EL0 U(1) 405 /* FEAT_MTE2: Full MTE is implemented */ 406 #define MTE_IMPLEMENTED_ELX U(2) 407 /* 408 * FEAT_MTE3: MTE is implemented with support for 409 * asymmetric Tag Check Fault handling 410 */ 411 #define MTE_IMPLEMENTED_ASY U(3) 412 413 #define ID_AA64PFR1_MPAM_FRAC_SHIFT ULL(16) 414 #define ID_AA64PFR1_MPAM_FRAC_MASK ULL(0xf) 415 416 #define ID_AA64PFR1_EL1_SME_SHIFT U(24) 417 #define ID_AA64PFR1_EL1_SME_MASK ULL(0xf) 418 #define ID_AA64PFR1_EL1_SME_NOT_SUPPORTED ULL(0x0) 419 #define ID_AA64PFR1_EL1_SME_SUPPORTED ULL(0x1) 420 #define ID_AA64PFR1_EL1_SME2_SUPPORTED ULL(0x2) 421 422 /* ID_PFR1_EL1 definitions */ 423 #define ID_PFR1_VIRTEXT_SHIFT U(12) 424 #define ID_PFR1_VIRTEXT_MASK U(0xf) 425 #define GET_VIRT_EXT(id) (((id) >> ID_PFR1_VIRTEXT_SHIFT) \ 426 & ID_PFR1_VIRTEXT_MASK) 427 428 /* SCTLR definitions */ 429 #define SCTLR_EL2_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ 430 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \ 431 (U(1) << 11) | (U(1) << 5) | (U(1) << 4)) 432 433 #define SCTLR_EL1_RES1 ((UL(1) << 29) | (UL(1) << 28) | (UL(1) << 23) | \ 434 (UL(1) << 22) | (UL(1) << 20) | (UL(1) << 11)) 435 436 #define SCTLR_AARCH32_EL1_RES1 \ 437 ((U(1) << 23) | (U(1) << 22) | (U(1) << 11) | \ 438 (U(1) << 4) | (U(1) << 3)) 439 440 #define SCTLR_EL3_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ 441 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \ 442 (U(1) << 11) | (U(1) << 5) | (U(1) << 4)) 443 444 #define SCTLR_M_BIT (ULL(1) << 0) 445 #define SCTLR_A_BIT (ULL(1) << 1) 446 #define SCTLR_C_BIT (ULL(1) << 2) 447 #define SCTLR_SA_BIT (ULL(1) << 3) 448 #define SCTLR_SA0_BIT (ULL(1) << 4) 449 #define SCTLR_CP15BEN_BIT (ULL(1) << 5) 450 #define SCTLR_nAA_BIT (ULL(1) << 6) 451 #define SCTLR_ITD_BIT (ULL(1) << 7) 452 #define SCTLR_SED_BIT (ULL(1) << 8) 453 #define SCTLR_UMA_BIT (ULL(1) << 9) 454 #define SCTLR_EnRCTX_BIT (ULL(1) << 10) 455 #define SCTLR_EOS_BIT (ULL(1) << 11) 456 #define SCTLR_I_BIT (ULL(1) << 12) 457 #define SCTLR_EnDB_BIT (ULL(1) << 13) 458 #define SCTLR_DZE_BIT (ULL(1) << 14) 459 #define SCTLR_UCT_BIT (ULL(1) << 15) 460 #define SCTLR_NTWI_BIT (ULL(1) << 16) 461 #define SCTLR_NTWE_BIT (ULL(1) << 18) 462 #define SCTLR_WXN_BIT (ULL(1) << 19) 463 #define SCTLR_TSCXT_BIT (ULL(1) << 20) 464 #define SCTLR_IESB_BIT (ULL(1) << 21) 465 #define SCTLR_EIS_BIT (ULL(1) << 22) 466 #define SCTLR_SPAN_BIT (ULL(1) << 23) 467 #define SCTLR_E0E_BIT (ULL(1) << 24) 468 #define SCTLR_EE_BIT (ULL(1) << 25) 469 #define SCTLR_UCI_BIT (ULL(1) << 26) 470 #define SCTLR_EnDA_BIT (ULL(1) << 27) 471 #define SCTLR_nTLSMD_BIT (ULL(1) << 28) 472 #define SCTLR_LSMAOE_BIT (ULL(1) << 29) 473 #define SCTLR_EnIB_BIT (ULL(1) << 30) 474 #define SCTLR_EnIA_BIT (ULL(1) << 31) 475 #define SCTLR_BT0_BIT (ULL(1) << 35) 476 #define SCTLR_BT1_BIT (ULL(1) << 36) 477 #define SCTLR_BT_BIT (ULL(1) << 36) 478 #define SCTLR_ITFSB_BIT (ULL(1) << 37) 479 #define SCTLR_TCF0_SHIFT U(38) 480 #define SCTLR_TCF0_MASK ULL(3) 481 #define SCTLR_ENTP2_BIT (ULL(1) << 60) 482 483 /* Tag Check Faults in EL0 have no effect on the PE */ 484 #define SCTLR_TCF0_NO_EFFECT U(0) 485 /* Tag Check Faults in EL0 cause a synchronous exception */ 486 #define SCTLR_TCF0_SYNC U(1) 487 /* Tag Check Faults in EL0 are asynchronously accumulated */ 488 #define SCTLR_TCF0_ASYNC U(2) 489 /* 490 * Tag Check Faults in EL0 cause a synchronous exception on reads, 491 * and are asynchronously accumulated on writes 492 */ 493 #define SCTLR_TCF0_SYNCR_ASYNCW U(3) 494 495 #define SCTLR_TCF_SHIFT U(40) 496 #define SCTLR_TCF_MASK ULL(3) 497 498 /* Tag Check Faults in EL1 have no effect on the PE */ 499 #define SCTLR_TCF_NO_EFFECT U(0) 500 /* Tag Check Faults in EL1 cause a synchronous exception */ 501 #define SCTLR_TCF_SYNC U(1) 502 /* Tag Check Faults in EL1 are asynchronously accumulated */ 503 #define SCTLR_TCF_ASYNC U(2) 504 /* 505 * Tag Check Faults in EL1 cause a synchronous exception on reads, 506 * and are asynchronously accumulated on writes 507 */ 508 #define SCTLR_TCF_SYNCR_ASYNCW U(3) 509 510 #define SCTLR_ATA0_BIT (ULL(1) << 42) 511 #define SCTLR_ATA_BIT (ULL(1) << 43) 512 #define SCTLR_DSSBS_SHIFT U(44) 513 #define SCTLR_DSSBS_BIT (ULL(1) << SCTLR_DSSBS_SHIFT) 514 #define SCTLR_TWEDEn_BIT (ULL(1) << 45) 515 #define SCTLR_TWEDEL_SHIFT U(46) 516 #define SCTLR_TWEDEL_MASK ULL(0xf) 517 #define SCTLR_EnASR_BIT (ULL(1) << 54) 518 #define SCTLR_EnAS0_BIT (ULL(1) << 55) 519 #define SCTLR_EnALS_BIT (ULL(1) << 56) 520 #define SCTLR_EPAN_BIT (ULL(1) << 57) 521 #define SCTLR_RESET_VAL SCTLR_EL3_RES1 522 523 /* CPACR_EL1 definitions */ 524 #define CPACR_EL1_FPEN(x) ((x) << 20) 525 #define CPACR_EL1_FP_TRAP_EL0 UL(0x1) 526 #define CPACR_EL1_FP_TRAP_ALL UL(0x2) 527 #define CPACR_EL1_FP_TRAP_NONE UL(0x3) 528 #define CPACR_EL1_SMEN_SHIFT U(24) 529 #define CPACR_EL1_SMEN_MASK ULL(0x3) 530 531 /* SCR definitions */ 532 #define SCR_RES1_BITS ((U(1) << 4) | (U(1) << 5)) 533 #define SCR_NSE_SHIFT U(62) 534 #define SCR_NSE_BIT (ULL(1) << SCR_NSE_SHIFT) 535 #define SCR_GPF_BIT (UL(1) << 48) 536 #define SCR_TWEDEL_SHIFT U(30) 537 #define SCR_TWEDEL_MASK ULL(0xf) 538 #define SCR_PIEN_BIT (UL(1) << 45) 539 #define SCR_TCR2EN_BIT (UL(1) << 43) 540 #define SCR_TRNDR_BIT (UL(1) << 40) 541 #define SCR_GCSEn_BIT (UL(1) << 39) 542 #define SCR_HXEn_BIT (UL(1) << 38) 543 #define SCR_ENTP2_SHIFT U(41) 544 #define SCR_ENTP2_BIT (UL(1) << SCR_ENTP2_SHIFT) 545 #define SCR_AMVOFFEN_SHIFT U(35) 546 #define SCR_AMVOFFEN_BIT (UL(1) << SCR_AMVOFFEN_SHIFT) 547 #define SCR_TWEDEn_BIT (UL(1) << 29) 548 #define SCR_ECVEN_BIT (UL(1) << 28) 549 #define SCR_FGTEN_BIT (UL(1) << 27) 550 #define SCR_ATA_BIT (UL(1) << 26) 551 #define SCR_EnSCXT_BIT (UL(1) << 25) 552 #define SCR_FIEN_BIT (UL(1) << 21) 553 #define SCR_EEL2_BIT (UL(1) << 18) 554 #define SCR_API_BIT (UL(1) << 17) 555 #define SCR_APK_BIT (UL(1) << 16) 556 #define SCR_TERR_BIT (UL(1) << 15) 557 #define SCR_TWE_BIT (UL(1) << 13) 558 #define SCR_TWI_BIT (UL(1) << 12) 559 #define SCR_ST_BIT (UL(1) << 11) 560 #define SCR_RW_BIT (UL(1) << 10) 561 #define SCR_SIF_BIT (UL(1) << 9) 562 #define SCR_HCE_BIT (UL(1) << 8) 563 #define SCR_SMD_BIT (UL(1) << 7) 564 #define SCR_EA_BIT (UL(1) << 3) 565 #define SCR_FIQ_BIT (UL(1) << 2) 566 #define SCR_IRQ_BIT (UL(1) << 1) 567 #define SCR_NS_BIT (UL(1) << 0) 568 #define SCR_VALID_BIT_MASK U(0x24000002F8F) 569 #define SCR_RESET_VAL SCR_RES1_BITS 570 571 /* MDCR_EL3 definitions */ 572 #define MDCR_EnPMSN_BIT (ULL(1) << 36) 573 #define MDCR_MPMX_BIT (ULL(1) << 35) 574 #define MDCR_MCCD_BIT (ULL(1) << 34) 575 #define MDCR_SBRBE_SHIFT U(32) 576 #define MDCR_SBRBE_MASK ULL(0x3) 577 #define MDCR_NSTB(x) ((x) << 24) 578 #define MDCR_NSTB_EL1 ULL(0x3) 579 #define MDCR_NSTBE (ULL(1) << 26) 580 #define MDCR_MTPME_BIT (ULL(1) << 28) 581 #define MDCR_TDCC_BIT (ULL(1) << 27) 582 #define MDCR_SCCD_BIT (ULL(1) << 23) 583 #define MDCR_EPMAD_BIT (ULL(1) << 21) 584 #define MDCR_EDAD_BIT (ULL(1) << 20) 585 #define MDCR_TTRF_BIT (ULL(1) << 19) 586 #define MDCR_STE_BIT (ULL(1) << 18) 587 #define MDCR_SPME_BIT (ULL(1) << 17) 588 #define MDCR_SDD_BIT (ULL(1) << 16) 589 #define MDCR_SPD32(x) ((x) << 14) 590 #define MDCR_SPD32_LEGACY ULL(0x0) 591 #define MDCR_SPD32_DISABLE ULL(0x2) 592 #define MDCR_SPD32_ENABLE ULL(0x3) 593 #define MDCR_NSPB(x) ((x) << 12) 594 #define MDCR_NSPB_EL1 ULL(0x3) 595 #define MDCR_TDOSA_BIT (ULL(1) << 10) 596 #define MDCR_TDA_BIT (ULL(1) << 9) 597 #define MDCR_TPM_BIT (ULL(1) << 6) 598 #define MDCR_EL3_RESET_VAL ULL(0x0) 599 600 /* MDCR_EL2 definitions */ 601 #define MDCR_EL2_MTPME (U(1) << 28) 602 #define MDCR_EL2_HLP (U(1) << 26) 603 #define MDCR_EL2_E2TB(x) ((x) << 24) 604 #define MDCR_EL2_E2TB_EL1 U(0x3) 605 #define MDCR_EL2_HCCD (U(1) << 23) 606 #define MDCR_EL2_TTRF (U(1) << 19) 607 #define MDCR_EL2_HPMD (U(1) << 17) 608 #define MDCR_EL2_TPMS (U(1) << 14) 609 #define MDCR_EL2_E2PB(x) ((x) << 12) 610 #define MDCR_EL2_E2PB_EL1 U(0x3) 611 #define MDCR_EL2_TDRA_BIT (U(1) << 11) 612 #define MDCR_EL2_TDOSA_BIT (U(1) << 10) 613 #define MDCR_EL2_TDA_BIT (U(1) << 9) 614 #define MDCR_EL2_TDE_BIT (U(1) << 8) 615 #define MDCR_EL2_HPME_BIT (U(1) << 7) 616 #define MDCR_EL2_TPM_BIT (U(1) << 6) 617 #define MDCR_EL2_TPMCR_BIT (U(1) << 5) 618 #define MDCR_EL2_RESET_VAL U(0x0) 619 620 /* HSTR_EL2 definitions */ 621 #define HSTR_EL2_RESET_VAL U(0x0) 622 #define HSTR_EL2_T_MASK U(0xff) 623 624 /* CNTHP_CTL_EL2 definitions */ 625 #define CNTHP_CTL_ENABLE_BIT (U(1) << 0) 626 #define CNTHP_CTL_RESET_VAL U(0x0) 627 628 /* VTTBR_EL2 definitions */ 629 #define VTTBR_RESET_VAL ULL(0x0) 630 #define VTTBR_VMID_MASK ULL(0xff) 631 #define VTTBR_VMID_SHIFT U(48) 632 #define VTTBR_BADDR_MASK ULL(0xffffffffffff) 633 #define VTTBR_BADDR_SHIFT U(0) 634 635 /* HCR definitions */ 636 #define HCR_RESET_VAL ULL(0x0) 637 #define HCR_AMVOFFEN_SHIFT U(51) 638 #define HCR_AMVOFFEN_BIT (ULL(1) << HCR_AMVOFFEN_SHIFT) 639 #define HCR_TEA_BIT (ULL(1) << 47) 640 #define HCR_API_BIT (ULL(1) << 41) 641 #define HCR_APK_BIT (ULL(1) << 40) 642 #define HCR_E2H_BIT (ULL(1) << 34) 643 #define HCR_HCD_BIT (ULL(1) << 29) 644 #define HCR_TGE_BIT (ULL(1) << 27) 645 #define HCR_RW_SHIFT U(31) 646 #define HCR_RW_BIT (ULL(1) << HCR_RW_SHIFT) 647 #define HCR_TWE_BIT (ULL(1) << 14) 648 #define HCR_TWI_BIT (ULL(1) << 13) 649 #define HCR_AMO_BIT (ULL(1) << 5) 650 #define HCR_IMO_BIT (ULL(1) << 4) 651 #define HCR_FMO_BIT (ULL(1) << 3) 652 653 /* ISR definitions */ 654 #define ISR_A_SHIFT U(8) 655 #define ISR_I_SHIFT U(7) 656 #define ISR_F_SHIFT U(6) 657 658 /* CNTHCTL_EL2 definitions */ 659 #define CNTHCTL_RESET_VAL U(0x0) 660 #define EVNTEN_BIT (U(1) << 2) 661 #define EL1PCEN_BIT (U(1) << 1) 662 #define EL1PCTEN_BIT (U(1) << 0) 663 664 /* CNTKCTL_EL1 definitions */ 665 #define EL0PTEN_BIT (U(1) << 9) 666 #define EL0VTEN_BIT (U(1) << 8) 667 #define EL0PCTEN_BIT (U(1) << 0) 668 #define EL0VCTEN_BIT (U(1) << 1) 669 #define EVNTEN_BIT (U(1) << 2) 670 #define EVNTDIR_BIT (U(1) << 3) 671 #define EVNTI_SHIFT U(4) 672 #define EVNTI_MASK U(0xf) 673 674 /* CPTR_EL3 definitions */ 675 #define TCPAC_BIT (U(1) << 31) 676 #define TAM_SHIFT U(30) 677 #define TAM_BIT (U(1) << TAM_SHIFT) 678 #define TTA_BIT (U(1) << 20) 679 #define ESM_BIT (U(1) << 12) 680 #define TFP_BIT (U(1) << 10) 681 #define CPTR_EZ_BIT (U(1) << 8) 682 #define CPTR_EL3_RESET_VAL ((TCPAC_BIT | TAM_BIT | TTA_BIT | TFP_BIT) & \ 683 ~(CPTR_EZ_BIT | ESM_BIT)) 684 685 /* CPTR_EL2 definitions */ 686 #define CPTR_EL2_RES1 ((U(1) << 13) | (U(1) << 12) | (U(0x3ff))) 687 #define CPTR_EL2_TCPAC_BIT (U(1) << 31) 688 #define CPTR_EL2_TAM_SHIFT U(30) 689 #define CPTR_EL2_TAM_BIT (U(1) << CPTR_EL2_TAM_SHIFT) 690 #define CPTR_EL2_SMEN_MASK ULL(0x3) 691 #define CPTR_EL2_SMEN_SHIFT U(24) 692 #define CPTR_EL2_TTA_BIT (U(1) << 20) 693 #define CPTR_EL2_TSM_BIT (U(1) << 12) 694 #define CPTR_EL2_TFP_BIT (U(1) << 10) 695 #define CPTR_EL2_TZ_BIT (U(1) << 8) 696 #define CPTR_EL2_RESET_VAL CPTR_EL2_RES1 697 698 /* VTCR_EL2 definitions */ 699 #define VTCR_RESET_VAL U(0x0) 700 #define VTCR_EL2_MSA (U(1) << 31) 701 702 /* CPSR/SPSR definitions */ 703 #define DAIF_FIQ_BIT (U(1) << 0) 704 #define DAIF_IRQ_BIT (U(1) << 1) 705 #define DAIF_ABT_BIT (U(1) << 2) 706 #define DAIF_DBG_BIT (U(1) << 3) 707 #define SPSR_DAIF_SHIFT U(6) 708 #define SPSR_DAIF_MASK U(0xf) 709 710 #define SPSR_AIF_SHIFT U(6) 711 #define SPSR_AIF_MASK U(0x7) 712 713 #define SPSR_E_SHIFT U(9) 714 #define SPSR_E_MASK U(0x1) 715 #define SPSR_E_LITTLE U(0x0) 716 #define SPSR_E_BIG U(0x1) 717 718 #define SPSR_T_SHIFT U(5) 719 #define SPSR_T_MASK U(0x1) 720 #define SPSR_T_ARM U(0x0) 721 #define SPSR_T_THUMB U(0x1) 722 723 #define SPSR_M_SHIFT U(4) 724 #define SPSR_M_MASK U(0x1) 725 #define SPSR_M_AARCH64 U(0x0) 726 #define SPSR_M_AARCH32 U(0x1) 727 #define SPSR_M_EL2H U(0x9) 728 729 #define SPSR_EL_SHIFT U(2) 730 #define SPSR_EL_WIDTH U(2) 731 732 #define SPSR_SSBS_SHIFT_AARCH64 U(12) 733 #define SPSR_SSBS_BIT_AARCH64 (ULL(1) << SPSR_SSBS_SHIFT_AARCH64) 734 #define SPSR_SSBS_SHIFT_AARCH32 U(23) 735 #define SPSR_SSBS_BIT_AARCH32 (ULL(1) << SPSR_SSBS_SHIFT_AARCH32) 736 737 #define SPSR_PAN_BIT BIT_64(22) 738 739 #define SPSR_DIT_BIT BIT(24) 740 741 #define SPSR_TCO_BIT_AARCH64 BIT_64(25) 742 743 #define DISABLE_ALL_EXCEPTIONS \ 744 (DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT | DAIF_DBG_BIT) 745 746 #define DISABLE_INTERRUPTS (DAIF_FIQ_BIT | DAIF_IRQ_BIT) 747 748 /* 749 * RMR_EL3 definitions 750 */ 751 #define RMR_EL3_RR_BIT (U(1) << 1) 752 #define RMR_EL3_AA64_BIT (U(1) << 0) 753 754 /* 755 * HI-VECTOR address for AArch32 state 756 */ 757 #define HI_VECTOR_BASE U(0xFFFF0000) 758 759 /* 760 * TCR definitions 761 */ 762 #define TCR_EL3_RES1 ((ULL(1) << 31) | (ULL(1) << 23)) 763 #define TCR_EL2_RES1 ((ULL(1) << 31) | (ULL(1) << 23)) 764 #define TCR_EL1_IPS_SHIFT U(32) 765 #define TCR_EL2_PS_SHIFT U(16) 766 #define TCR_EL3_PS_SHIFT U(16) 767 768 #define TCR_TxSZ_MIN ULL(16) 769 #define TCR_TxSZ_MAX ULL(39) 770 #define TCR_TxSZ_MAX_TTST ULL(48) 771 772 #define TCR_T0SZ_SHIFT U(0) 773 #define TCR_T1SZ_SHIFT U(16) 774 775 /* (internal) physical address size bits in EL3/EL1 */ 776 #define TCR_PS_BITS_4GB ULL(0x0) 777 #define TCR_PS_BITS_64GB ULL(0x1) 778 #define TCR_PS_BITS_1TB ULL(0x2) 779 #define TCR_PS_BITS_4TB ULL(0x3) 780 #define TCR_PS_BITS_16TB ULL(0x4) 781 #define TCR_PS_BITS_256TB ULL(0x5) 782 783 #define ADDR_MASK_48_TO_63 ULL(0xFFFF000000000000) 784 #define ADDR_MASK_44_TO_47 ULL(0x0000F00000000000) 785 #define ADDR_MASK_42_TO_43 ULL(0x00000C0000000000) 786 #define ADDR_MASK_40_TO_41 ULL(0x0000030000000000) 787 #define ADDR_MASK_36_TO_39 ULL(0x000000F000000000) 788 #define ADDR_MASK_32_TO_35 ULL(0x0000000F00000000) 789 790 #define TCR_RGN_INNER_NC (ULL(0x0) << 8) 791 #define TCR_RGN_INNER_WBA (ULL(0x1) << 8) 792 #define TCR_RGN_INNER_WT (ULL(0x2) << 8) 793 #define TCR_RGN_INNER_WBNA (ULL(0x3) << 8) 794 795 #define TCR_RGN_OUTER_NC (ULL(0x0) << 10) 796 #define TCR_RGN_OUTER_WBA (ULL(0x1) << 10) 797 #define TCR_RGN_OUTER_WT (ULL(0x2) << 10) 798 #define TCR_RGN_OUTER_WBNA (ULL(0x3) << 10) 799 800 #define TCR_SH_NON_SHAREABLE (ULL(0x0) << 12) 801 #define TCR_SH_OUTER_SHAREABLE (ULL(0x2) << 12) 802 #define TCR_SH_INNER_SHAREABLE (ULL(0x3) << 12) 803 804 #define TCR_RGN1_INNER_NC (ULL(0x0) << 24) 805 #define TCR_RGN1_INNER_WBA (ULL(0x1) << 24) 806 #define TCR_RGN1_INNER_WT (ULL(0x2) << 24) 807 #define TCR_RGN1_INNER_WBNA (ULL(0x3) << 24) 808 809 #define TCR_RGN1_OUTER_NC (ULL(0x0) << 26) 810 #define TCR_RGN1_OUTER_WBA (ULL(0x1) << 26) 811 #define TCR_RGN1_OUTER_WT (ULL(0x2) << 26) 812 #define TCR_RGN1_OUTER_WBNA (ULL(0x3) << 26) 813 814 #define TCR_SH1_NON_SHAREABLE (ULL(0x0) << 28) 815 #define TCR_SH1_OUTER_SHAREABLE (ULL(0x2) << 28) 816 #define TCR_SH1_INNER_SHAREABLE (ULL(0x3) << 28) 817 818 #define TCR_TG0_SHIFT U(14) 819 #define TCR_TG0_MASK ULL(3) 820 #define TCR_TG0_4K (ULL(0) << TCR_TG0_SHIFT) 821 #define TCR_TG0_64K (ULL(1) << TCR_TG0_SHIFT) 822 #define TCR_TG0_16K (ULL(2) << TCR_TG0_SHIFT) 823 824 #define TCR_TG1_SHIFT U(30) 825 #define TCR_TG1_MASK ULL(3) 826 #define TCR_TG1_16K (ULL(1) << TCR_TG1_SHIFT) 827 #define TCR_TG1_4K (ULL(2) << TCR_TG1_SHIFT) 828 #define TCR_TG1_64K (ULL(3) << TCR_TG1_SHIFT) 829 830 #define TCR_EPD0_BIT (ULL(1) << 7) 831 #define TCR_EPD1_BIT (ULL(1) << 23) 832 833 #define MODE_SP_SHIFT U(0x0) 834 #define MODE_SP_MASK U(0x1) 835 #define MODE_SP_EL0 U(0x0) 836 #define MODE_SP_ELX U(0x1) 837 838 #define MODE_RW_SHIFT U(0x4) 839 #define MODE_RW_MASK U(0x1) 840 #define MODE_RW_64 U(0x0) 841 #define MODE_RW_32 U(0x1) 842 843 #define MODE_EL_SHIFT U(0x2) 844 #define MODE_EL_MASK U(0x3) 845 #define MODE_EL_WIDTH U(0x2) 846 #define MODE_EL3 U(0x3) 847 #define MODE_EL2 U(0x2) 848 #define MODE_EL1 U(0x1) 849 #define MODE_EL0 U(0x0) 850 851 #define MODE32_SHIFT U(0) 852 #define MODE32_MASK U(0xf) 853 #define MODE32_usr U(0x0) 854 #define MODE32_fiq U(0x1) 855 #define MODE32_irq U(0x2) 856 #define MODE32_svc U(0x3) 857 #define MODE32_mon U(0x6) 858 #define MODE32_abt U(0x7) 859 #define MODE32_hyp U(0xa) 860 #define MODE32_und U(0xb) 861 #define MODE32_sys U(0xf) 862 863 #define GET_RW(mode) (((mode) >> MODE_RW_SHIFT) & MODE_RW_MASK) 864 #define GET_EL(mode) (((mode) >> MODE_EL_SHIFT) & MODE_EL_MASK) 865 #define GET_SP(mode) (((mode) >> MODE_SP_SHIFT) & MODE_SP_MASK) 866 #define GET_M32(mode) (((mode) >> MODE32_SHIFT) & MODE32_MASK) 867 868 #define SPSR_64(el, sp, daif) \ 869 (((MODE_RW_64 << MODE_RW_SHIFT) | \ 870 (((el) & MODE_EL_MASK) << MODE_EL_SHIFT) | \ 871 (((sp) & MODE_SP_MASK) << MODE_SP_SHIFT) | \ 872 (((daif) & SPSR_DAIF_MASK) << SPSR_DAIF_SHIFT)) & \ 873 (~(SPSR_SSBS_BIT_AARCH64))) 874 875 #define SPSR_MODE32(mode, isa, endian, aif) \ 876 (((MODE_RW_32 << MODE_RW_SHIFT) | \ 877 (((mode) & MODE32_MASK) << MODE32_SHIFT) | \ 878 (((isa) & SPSR_T_MASK) << SPSR_T_SHIFT) | \ 879 (((endian) & SPSR_E_MASK) << SPSR_E_SHIFT) | \ 880 (((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT)) & \ 881 (~(SPSR_SSBS_BIT_AARCH32))) 882 883 /* 884 * TTBR Definitions 885 */ 886 #define TTBR_CNP_BIT ULL(0x1) 887 888 /* 889 * CTR_EL0 definitions 890 */ 891 #define CTR_CWG_SHIFT U(24) 892 #define CTR_CWG_MASK U(0xf) 893 #define CTR_ERG_SHIFT U(20) 894 #define CTR_ERG_MASK U(0xf) 895 #define CTR_DMINLINE_SHIFT U(16) 896 #define CTR_DMINLINE_MASK U(0xf) 897 #define CTR_L1IP_SHIFT U(14) 898 #define CTR_L1IP_MASK U(0x3) 899 #define CTR_IMINLINE_SHIFT U(0) 900 #define CTR_IMINLINE_MASK U(0xf) 901 902 #define MAX_CACHE_LINE_SIZE U(0x800) /* 2KB */ 903 904 /* Physical timer control register bit fields shifts and masks */ 905 #define CNTP_CTL_ENABLE_SHIFT U(0) 906 #define CNTP_CTL_IMASK_SHIFT U(1) 907 #define CNTP_CTL_ISTATUS_SHIFT U(2) 908 909 #define CNTP_CTL_ENABLE_MASK U(1) 910 #define CNTP_CTL_IMASK_MASK U(1) 911 #define CNTP_CTL_ISTATUS_MASK U(1) 912 913 /* Physical timer control macros */ 914 #define CNTP_CTL_ENABLE_BIT (U(1) << CNTP_CTL_ENABLE_SHIFT) 915 #define CNTP_CTL_IMASK_BIT (U(1) << CNTP_CTL_IMASK_SHIFT) 916 917 /* Exception Syndrome register bits and bobs */ 918 #define ESR_EC_SHIFT U(26) 919 #define ESR_EC_MASK U(0x3f) 920 #define ESR_EC_LENGTH U(6) 921 #define ESR_ISS_SHIFT U(0) 922 #define ESR_ISS_LENGTH U(25) 923 #define EC_UNKNOWN U(0x0) 924 #define EC_WFE_WFI U(0x1) 925 #define EC_AARCH32_CP15_MRC_MCR U(0x3) 926 #define EC_AARCH32_CP15_MRRC_MCRR U(0x4) 927 #define EC_AARCH32_CP14_MRC_MCR U(0x5) 928 #define EC_AARCH32_CP14_LDC_STC U(0x6) 929 #define EC_FP_SIMD U(0x7) 930 #define EC_AARCH32_CP10_MRC U(0x8) 931 #define EC_AARCH32_CP14_MRRC_MCRR U(0xc) 932 #define EC_ILLEGAL U(0xe) 933 #define EC_AARCH32_SVC U(0x11) 934 #define EC_AARCH32_HVC U(0x12) 935 #define EC_AARCH32_SMC U(0x13) 936 #define EC_AARCH64_SVC U(0x15) 937 #define EC_AARCH64_HVC U(0x16) 938 #define EC_AARCH64_SMC U(0x17) 939 #define EC_AARCH64_SYS U(0x18) 940 #define EC_IABORT_LOWER_EL U(0x20) 941 #define EC_IABORT_CUR_EL U(0x21) 942 #define EC_PC_ALIGN U(0x22) 943 #define EC_DABORT_LOWER_EL U(0x24) 944 #define EC_DABORT_CUR_EL U(0x25) 945 #define EC_SP_ALIGN U(0x26) 946 #define EC_AARCH32_FP U(0x28) 947 #define EC_AARCH64_FP U(0x2c) 948 #define EC_SERROR U(0x2f) 949 #define EC_BRK U(0x3c) 950 951 /* 952 * External Abort bit in Instruction and Data Aborts synchronous exception 953 * syndromes. 954 */ 955 #define ESR_ISS_EABORT_EA_BIT U(9) 956 957 #define EC_BITS(x) (((x) >> ESR_EC_SHIFT) & ESR_EC_MASK) 958 959 /* Reset bit inside the Reset management register for EL3 (RMR_EL3) */ 960 #define RMR_RESET_REQUEST_SHIFT U(0x1) 961 #define RMR_WARM_RESET_CPU (U(1) << RMR_RESET_REQUEST_SHIFT) 962 963 /******************************************************************************* 964 * Definitions of register offsets, fields and macros for CPU system 965 * instructions. 966 ******************************************************************************/ 967 968 #define TLBI_ADDR_SHIFT U(12) 969 #define TLBI_ADDR_MASK ULL(0x00000FFFFFFFFFFF) 970 #define TLBI_ADDR(x) (((x) >> TLBI_ADDR_SHIFT) & TLBI_ADDR_MASK) 971 972 /******************************************************************************* 973 * Definitions of register offsets and fields in the CNTCTLBase Frame of the 974 * system level implementation of the Generic Timer. 975 ******************************************************************************/ 976 #define CNTCTLBASE_CNTFRQ U(0x0) 977 #define CNTNSAR U(0x4) 978 #define CNTNSAR_NS_SHIFT(x) (x) 979 980 #define CNTACR_BASE(x) (U(0x40) + ((x) << 2)) 981 #define CNTACR_RPCT_SHIFT U(0x0) 982 #define CNTACR_RVCT_SHIFT U(0x1) 983 #define CNTACR_RFRQ_SHIFT U(0x2) 984 #define CNTACR_RVOFF_SHIFT U(0x3) 985 #define CNTACR_RWVT_SHIFT U(0x4) 986 #define CNTACR_RWPT_SHIFT U(0x5) 987 988 /******************************************************************************* 989 * Definitions of register offsets and fields in the CNTBaseN Frame of the 990 * system level implementation of the Generic Timer. 991 ******************************************************************************/ 992 /* Physical Count register. */ 993 #define CNTPCT_LO U(0x0) 994 /* Counter Frequency register. */ 995 #define CNTBASEN_CNTFRQ U(0x10) 996 /* Physical Timer CompareValue register. */ 997 #define CNTP_CVAL_LO U(0x20) 998 /* Physical Timer Control register. */ 999 #define CNTP_CTL U(0x2c) 1000 1001 /* PMCR_EL0 definitions */ 1002 #define PMCR_EL0_RESET_VAL U(0x0) 1003 #define PMCR_EL0_N_SHIFT U(11) 1004 #define PMCR_EL0_N_MASK U(0x1f) 1005 #define PMCR_EL0_N_BITS (PMCR_EL0_N_MASK << PMCR_EL0_N_SHIFT) 1006 #define PMCR_EL0_LP_BIT (U(1) << 7) 1007 #define PMCR_EL0_LC_BIT (U(1) << 6) 1008 #define PMCR_EL0_DP_BIT (U(1) << 5) 1009 #define PMCR_EL0_X_BIT (U(1) << 4) 1010 #define PMCR_EL0_D_BIT (U(1) << 3) 1011 #define PMCR_EL0_C_BIT (U(1) << 2) 1012 #define PMCR_EL0_P_BIT (U(1) << 1) 1013 #define PMCR_EL0_E_BIT (U(1) << 0) 1014 1015 /******************************************************************************* 1016 * Definitions for system register interface to SVE 1017 ******************************************************************************/ 1018 #define ZCR_EL3 S3_6_C1_C2_0 1019 #define ZCR_EL2 S3_4_C1_C2_0 1020 1021 /* ZCR_EL3 definitions */ 1022 #define ZCR_EL3_LEN_MASK U(0xf) 1023 1024 /* ZCR_EL2 definitions */ 1025 #define ZCR_EL2_LEN_MASK U(0xf) 1026 1027 /******************************************************************************* 1028 * Definitions for system register interface to SME as needed in EL3 1029 ******************************************************************************/ 1030 #define ID_AA64SMFR0_EL1 S3_0_C0_C4_5 1031 #define SMCR_EL3 S3_6_C1_C2_6 1032 1033 /* ID_AA64SMFR0_EL1 definitions */ 1034 #define ID_AA64SMFR0_EL1_SME_FA64_SHIFT U(63) 1035 #define ID_AA64SMFR0_EL1_SME_FA64_MASK U(0x1) 1036 #define ID_AA64SMFR0_EL1_SME_FA64_SUPPORTED U(0x1) 1037 #define ID_AA64SMFR0_EL1_SME_VER_SHIFT U(55) 1038 #define ID_AA64SMFR0_EL1_SME_VER_MASK ULL(0xf) 1039 #define ID_AA64SMFR0_EL1_SME_INST_SUPPORTED ULL(0x0) 1040 #define ID_AA64SMFR0_EL1_SME2_INST_SUPPORTED ULL(0x1) 1041 1042 /* SMCR_ELx definitions */ 1043 #define SMCR_ELX_LEN_SHIFT U(0) 1044 #define SMCR_ELX_LEN_MAX U(0x1ff) 1045 #define SMCR_ELX_FA64_BIT (U(1) << 31) 1046 #define SMCR_ELX_EZT0_BIT (U(1) << 30) 1047 1048 /******************************************************************************* 1049 * Definitions of MAIR encodings for device and normal memory 1050 ******************************************************************************/ 1051 /* 1052 * MAIR encodings for device memory attributes. 1053 */ 1054 #define MAIR_DEV_nGnRnE ULL(0x0) 1055 #define MAIR_DEV_nGnRE ULL(0x4) 1056 #define MAIR_DEV_nGRE ULL(0x8) 1057 #define MAIR_DEV_GRE ULL(0xc) 1058 1059 /* 1060 * MAIR encodings for normal memory attributes. 1061 * 1062 * Cache Policy 1063 * WT: Write Through 1064 * WB: Write Back 1065 * NC: Non-Cacheable 1066 * 1067 * Transient Hint 1068 * NTR: Non-Transient 1069 * TR: Transient 1070 * 1071 * Allocation Policy 1072 * RA: Read Allocate 1073 * WA: Write Allocate 1074 * RWA: Read and Write Allocate 1075 * NA: No Allocation 1076 */ 1077 #define MAIR_NORM_WT_TR_WA ULL(0x1) 1078 #define MAIR_NORM_WT_TR_RA ULL(0x2) 1079 #define MAIR_NORM_WT_TR_RWA ULL(0x3) 1080 #define MAIR_NORM_NC ULL(0x4) 1081 #define MAIR_NORM_WB_TR_WA ULL(0x5) 1082 #define MAIR_NORM_WB_TR_RA ULL(0x6) 1083 #define MAIR_NORM_WB_TR_RWA ULL(0x7) 1084 #define MAIR_NORM_WT_NTR_NA ULL(0x8) 1085 #define MAIR_NORM_WT_NTR_WA ULL(0x9) 1086 #define MAIR_NORM_WT_NTR_RA ULL(0xa) 1087 #define MAIR_NORM_WT_NTR_RWA ULL(0xb) 1088 #define MAIR_NORM_WB_NTR_NA ULL(0xc) 1089 #define MAIR_NORM_WB_NTR_WA ULL(0xd) 1090 #define MAIR_NORM_WB_NTR_RA ULL(0xe) 1091 #define MAIR_NORM_WB_NTR_RWA ULL(0xf) 1092 1093 #define MAIR_NORM_OUTER_SHIFT U(4) 1094 1095 #define MAKE_MAIR_NORMAL_MEMORY(inner, outer) \ 1096 ((inner) | ((outer) << MAIR_NORM_OUTER_SHIFT)) 1097 1098 /* PAR_EL1 fields */ 1099 #define PAR_F_SHIFT U(0) 1100 #define PAR_F_MASK ULL(0x1) 1101 #define PAR_ADDR_SHIFT U(12) 1102 #define PAR_ADDR_MASK (BIT(40) - ULL(1)) /* 40-bits-wide page address */ 1103 1104 /******************************************************************************* 1105 * Definitions for system register interface to SPE 1106 ******************************************************************************/ 1107 #define PMBLIMITR_EL1 S3_0_C9_C10_0 1108 1109 /******************************************************************************* 1110 * Definitions for system register interface, shifts and masks for MPAM 1111 ******************************************************************************/ 1112 #define MPAMIDR_EL1 S3_0_C10_C4_4 1113 #define MPAM2_EL2 S3_4_C10_C5_0 1114 #define MPAMHCR_EL2 S3_4_C10_C4_0 1115 #define MPAM3_EL3 S3_6_C10_C5_0 1116 1117 #define MPAMIDR_EL1_VPMR_MAX_SHIFT ULL(18) 1118 #define MPAMIDR_EL1_VPMR_MAX_MASK ULL(0x7) 1119 /******************************************************************************* 1120 * Definitions for system register interface to AMU for FEAT_AMUv1 1121 ******************************************************************************/ 1122 #define AMCR_EL0 S3_3_C13_C2_0 1123 #define AMCFGR_EL0 S3_3_C13_C2_1 1124 #define AMCGCR_EL0 S3_3_C13_C2_2 1125 #define AMUSERENR_EL0 S3_3_C13_C2_3 1126 #define AMCNTENCLR0_EL0 S3_3_C13_C2_4 1127 #define AMCNTENSET0_EL0 S3_3_C13_C2_5 1128 #define AMCNTENCLR1_EL0 S3_3_C13_C3_0 1129 #define AMCNTENSET1_EL0 S3_3_C13_C3_1 1130 1131 /* Activity Monitor Group 0 Event Counter Registers */ 1132 #define AMEVCNTR00_EL0 S3_3_C13_C4_0 1133 #define AMEVCNTR01_EL0 S3_3_C13_C4_1 1134 #define AMEVCNTR02_EL0 S3_3_C13_C4_2 1135 #define AMEVCNTR03_EL0 S3_3_C13_C4_3 1136 1137 /* Activity Monitor Group 0 Event Type Registers */ 1138 #define AMEVTYPER00_EL0 S3_3_C13_C6_0 1139 #define AMEVTYPER01_EL0 S3_3_C13_C6_1 1140 #define AMEVTYPER02_EL0 S3_3_C13_C6_2 1141 #define AMEVTYPER03_EL0 S3_3_C13_C6_3 1142 1143 /* Activity Monitor Group 1 Event Counter Registers */ 1144 #define AMEVCNTR10_EL0 S3_3_C13_C12_0 1145 #define AMEVCNTR11_EL0 S3_3_C13_C12_1 1146 #define AMEVCNTR12_EL0 S3_3_C13_C12_2 1147 #define AMEVCNTR13_EL0 S3_3_C13_C12_3 1148 #define AMEVCNTR14_EL0 S3_3_C13_C12_4 1149 #define AMEVCNTR15_EL0 S3_3_C13_C12_5 1150 #define AMEVCNTR16_EL0 S3_3_C13_C12_6 1151 #define AMEVCNTR17_EL0 S3_3_C13_C12_7 1152 #define AMEVCNTR18_EL0 S3_3_C13_C13_0 1153 #define AMEVCNTR19_EL0 S3_3_C13_C13_1 1154 #define AMEVCNTR1A_EL0 S3_3_C13_C13_2 1155 #define AMEVCNTR1B_EL0 S3_3_C13_C13_3 1156 #define AMEVCNTR1C_EL0 S3_3_C13_C13_4 1157 #define AMEVCNTR1D_EL0 S3_3_C13_C13_5 1158 #define AMEVCNTR1E_EL0 S3_3_C13_C13_6 1159 #define AMEVCNTR1F_EL0 S3_3_C13_C13_7 1160 1161 /* Activity Monitor Group 1 Event Type Registers */ 1162 #define AMEVTYPER10_EL0 S3_3_C13_C14_0 1163 #define AMEVTYPER11_EL0 S3_3_C13_C14_1 1164 #define AMEVTYPER12_EL0 S3_3_C13_C14_2 1165 #define AMEVTYPER13_EL0 S3_3_C13_C14_3 1166 #define AMEVTYPER14_EL0 S3_3_C13_C14_4 1167 #define AMEVTYPER15_EL0 S3_3_C13_C14_5 1168 #define AMEVTYPER16_EL0 S3_3_C13_C14_6 1169 #define AMEVTYPER17_EL0 S3_3_C13_C14_7 1170 #define AMEVTYPER18_EL0 S3_3_C13_C15_0 1171 #define AMEVTYPER19_EL0 S3_3_C13_C15_1 1172 #define AMEVTYPER1A_EL0 S3_3_C13_C15_2 1173 #define AMEVTYPER1B_EL0 S3_3_C13_C15_3 1174 #define AMEVTYPER1C_EL0 S3_3_C13_C15_4 1175 #define AMEVTYPER1D_EL0 S3_3_C13_C15_5 1176 #define AMEVTYPER1E_EL0 S3_3_C13_C15_6 1177 #define AMEVTYPER1F_EL0 S3_3_C13_C15_7 1178 1179 /* AMCNTENSET0_EL0 definitions */ 1180 #define AMCNTENSET0_EL0_Pn_SHIFT U(0) 1181 #define AMCNTENSET0_EL0_Pn_MASK ULL(0xffff) 1182 1183 /* AMCNTENSET1_EL0 definitions */ 1184 #define AMCNTENSET1_EL0_Pn_SHIFT U(0) 1185 #define AMCNTENSET1_EL0_Pn_MASK ULL(0xffff) 1186 1187 /* AMCNTENCLR0_EL0 definitions */ 1188 #define AMCNTENCLR0_EL0_Pn_SHIFT U(0) 1189 #define AMCNTENCLR0_EL0_Pn_MASK ULL(0xffff) 1190 1191 /* AMCNTENCLR1_EL0 definitions */ 1192 #define AMCNTENCLR1_EL0_Pn_SHIFT U(0) 1193 #define AMCNTENCLR1_EL0_Pn_MASK ULL(0xffff) 1194 1195 /* AMCFGR_EL0 definitions */ 1196 #define AMCFGR_EL0_NCG_SHIFT U(28) 1197 #define AMCFGR_EL0_NCG_MASK U(0xf) 1198 #define AMCFGR_EL0_N_SHIFT U(0) 1199 #define AMCFGR_EL0_N_MASK U(0xff) 1200 1201 /* AMCGCR_EL0 definitions */ 1202 #define AMCGCR_EL0_CG0NC_SHIFT U(0) 1203 #define AMCGCR_EL0_CG0NC_MASK U(0xff) 1204 #define AMCGCR_EL0_CG1NC_SHIFT U(8) 1205 #define AMCGCR_EL0_CG1NC_MASK U(0xff) 1206 1207 /* MPAM register definitions */ 1208 #define MPAM3_EL3_MPAMEN_BIT (ULL(1) << 63) 1209 #define MPAMHCR_EL2_TRAP_MPAMIDR_EL1 (ULL(1) << 31) 1210 1211 #define MPAM2_EL2_TRAPMPAM0EL1 (ULL(1) << 49) 1212 #define MPAM2_EL2_TRAPMPAM1EL1 (ULL(1) << 48) 1213 1214 #define MPAMIDR_HAS_HCR_BIT (ULL(1) << 17) 1215 1216 /******************************************************************************* 1217 * Definitions for system register interface to AMU for FEAT_AMUv1p1 1218 ******************************************************************************/ 1219 1220 /* Definition for register defining which virtual offsets are implemented. */ 1221 #define AMCG1IDR_EL0 S3_3_C13_C2_6 1222 #define AMCG1IDR_CTR_MASK ULL(0xffff) 1223 #define AMCG1IDR_CTR_SHIFT U(0) 1224 #define AMCG1IDR_VOFF_MASK ULL(0xffff) 1225 #define AMCG1IDR_VOFF_SHIFT U(16) 1226 1227 /* New bit added to AMCR_EL0 */ 1228 #define AMCR_CG1RZ_SHIFT U(17) 1229 #define AMCR_CG1RZ_BIT (ULL(0x1) << AMCR_CG1RZ_SHIFT) 1230 1231 /* 1232 * Definitions for virtual offset registers for architected activity monitor 1233 * event counters. 1234 * AMEVCNTVOFF01_EL2 intentionally left undefined, as it does not exist. 1235 */ 1236 #define AMEVCNTVOFF00_EL2 S3_4_C13_C8_0 1237 #define AMEVCNTVOFF02_EL2 S3_4_C13_C8_2 1238 #define AMEVCNTVOFF03_EL2 S3_4_C13_C8_3 1239 1240 /* 1241 * Definitions for virtual offset registers for auxiliary activity monitor event 1242 * counters. 1243 */ 1244 #define AMEVCNTVOFF10_EL2 S3_4_C13_C10_0 1245 #define AMEVCNTVOFF11_EL2 S3_4_C13_C10_1 1246 #define AMEVCNTVOFF12_EL2 S3_4_C13_C10_2 1247 #define AMEVCNTVOFF13_EL2 S3_4_C13_C10_3 1248 #define AMEVCNTVOFF14_EL2 S3_4_C13_C10_4 1249 #define AMEVCNTVOFF15_EL2 S3_4_C13_C10_5 1250 #define AMEVCNTVOFF16_EL2 S3_4_C13_C10_6 1251 #define AMEVCNTVOFF17_EL2 S3_4_C13_C10_7 1252 #define AMEVCNTVOFF18_EL2 S3_4_C13_C11_0 1253 #define AMEVCNTVOFF19_EL2 S3_4_C13_C11_1 1254 #define AMEVCNTVOFF1A_EL2 S3_4_C13_C11_2 1255 #define AMEVCNTVOFF1B_EL2 S3_4_C13_C11_3 1256 #define AMEVCNTVOFF1C_EL2 S3_4_C13_C11_4 1257 #define AMEVCNTVOFF1D_EL2 S3_4_C13_C11_5 1258 #define AMEVCNTVOFF1E_EL2 S3_4_C13_C11_6 1259 #define AMEVCNTVOFF1F_EL2 S3_4_C13_C11_7 1260 1261 /******************************************************************************* 1262 * Realm management extension register definitions 1263 ******************************************************************************/ 1264 #define GPCCR_EL3 S3_6_C2_C1_6 1265 #define GPTBR_EL3 S3_6_C2_C1_4 1266 1267 #define SCXTNUM_EL2 S3_4_C13_C0_7 1268 1269 /******************************************************************************* 1270 * RAS system registers 1271 ******************************************************************************/ 1272 #define DISR_EL1 S3_0_C12_C1_1 1273 #define DISR_A_BIT U(31) 1274 1275 #define ERRIDR_EL1 S3_0_C5_C3_0 1276 #define ERRIDR_MASK U(0xffff) 1277 1278 #define ERRSELR_EL1 S3_0_C5_C3_1 1279 1280 /* System register access to Standard Error Record registers */ 1281 #define ERXFR_EL1 S3_0_C5_C4_0 1282 #define ERXCTLR_EL1 S3_0_C5_C4_1 1283 #define ERXSTATUS_EL1 S3_0_C5_C4_2 1284 #define ERXADDR_EL1 S3_0_C5_C4_3 1285 #define ERXPFGF_EL1 S3_0_C5_C4_4 1286 #define ERXPFGCTL_EL1 S3_0_C5_C4_5 1287 #define ERXPFGCDN_EL1 S3_0_C5_C4_6 1288 #define ERXMISC0_EL1 S3_0_C5_C5_0 1289 #define ERXMISC1_EL1 S3_0_C5_C5_1 1290 1291 #define ERXCTLR_ED_SHIFT U(0) 1292 #define ERXCTLR_ED_BIT (U(1) << ERXCTLR_ED_SHIFT) 1293 #define ERXCTLR_UE_BIT (U(1) << 4) 1294 1295 #define ERXPFGCTL_UC_BIT (U(1) << 1) 1296 #define ERXPFGCTL_UEU_BIT (U(1) << 2) 1297 #define ERXPFGCTL_CDEN_BIT (U(1) << 31) 1298 1299 /******************************************************************************* 1300 * Armv8.3 Pointer Authentication Registers 1301 ******************************************************************************/ 1302 #define APIAKeyLo_EL1 S3_0_C2_C1_0 1303 #define APIAKeyHi_EL1 S3_0_C2_C1_1 1304 #define APIBKeyLo_EL1 S3_0_C2_C1_2 1305 #define APIBKeyHi_EL1 S3_0_C2_C1_3 1306 #define APDAKeyLo_EL1 S3_0_C2_C2_0 1307 #define APDAKeyHi_EL1 S3_0_C2_C2_1 1308 #define APDBKeyLo_EL1 S3_0_C2_C2_2 1309 #define APDBKeyHi_EL1 S3_0_C2_C2_3 1310 #define APGAKeyLo_EL1 S3_0_C2_C3_0 1311 #define APGAKeyHi_EL1 S3_0_C2_C3_1 1312 1313 /******************************************************************************* 1314 * Armv8.4 Data Independent Timing Registers 1315 ******************************************************************************/ 1316 #define DIT S3_3_C4_C2_5 1317 #define DIT_BIT BIT(24) 1318 1319 /******************************************************************************* 1320 * Armv8.5 - new MSR encoding to directly access PSTATE.SSBS field 1321 ******************************************************************************/ 1322 #define SSBS S3_3_C4_C2_6 1323 1324 /******************************************************************************* 1325 * Armv8.5 - Memory Tagging Extension Registers 1326 ******************************************************************************/ 1327 #define TFSRE0_EL1 S3_0_C5_C6_1 1328 #define TFSR_EL1 S3_0_C5_C6_0 1329 #define RGSR_EL1 S3_0_C1_C0_5 1330 #define GCR_EL1 S3_0_C1_C0_6 1331 1332 /******************************************************************************* 1333 * Armv8.5 - Random Number Generator Registers 1334 ******************************************************************************/ 1335 #define RNDR S3_3_C2_C4_0 1336 #define RNDRRS S3_3_C2_C4_1 1337 1338 /******************************************************************************* 1339 * FEAT_HCX - Extended Hypervisor Configuration Register 1340 ******************************************************************************/ 1341 #define HCRX_EL2 S3_4_C1_C2_2 1342 #define HCRX_EL2_MSCEn_BIT (UL(1) << 11) 1343 #define HCRX_EL2_MCE2_BIT (UL(1) << 10) 1344 #define HCRX_EL2_CMOW_BIT (UL(1) << 9) 1345 #define HCRX_EL2_VFNMI_BIT (UL(1) << 8) 1346 #define HCRX_EL2_VINMI_BIT (UL(1) << 7) 1347 #define HCRX_EL2_TALLINT_BIT (UL(1) << 6) 1348 #define HCRX_EL2_SMPME_BIT (UL(1) << 5) 1349 #define HCRX_EL2_FGTnXS_BIT (UL(1) << 4) 1350 #define HCRX_EL2_FnXS_BIT (UL(1) << 3) 1351 #define HCRX_EL2_EnASR_BIT (UL(1) << 2) 1352 #define HCRX_EL2_EnALS_BIT (UL(1) << 1) 1353 #define HCRX_EL2_EnAS0_BIT (UL(1) << 0) 1354 #define HCRX_EL2_INIT_VAL ULL(0x0) 1355 1356 /******************************************************************************* 1357 * FEAT_TCR2 - Extended Translation Control Register 1358 ******************************************************************************/ 1359 #define TCR2_EL2 S3_4_C2_C0_3 1360 1361 /******************************************************************************* 1362 * Permission indirection and overlay 1363 ******************************************************************************/ 1364 1365 #define PIRE0_EL2 S3_4_C10_C2_2 1366 #define PIR_EL2 S3_4_C10_C2_3 1367 #define POR_EL2 S3_4_C10_C2_4 1368 #define S2PIR_EL2 S3_4_C10_C2_5 1369 1370 /******************************************************************************* 1371 * FEAT_GCS - Guarded Control Stack Registers 1372 ******************************************************************************/ 1373 #define GCSCR_EL2 S3_4_C2_C5_0 1374 #define GCSPR_EL2 S3_4_C2_C5_1 1375 1376 /******************************************************************************* 1377 * Definitions for DynamicIQ Shared Unit registers 1378 ******************************************************************************/ 1379 #define CLUSTERPWRDN_EL1 S3_0_c15_c3_6 1380 1381 /* CLUSTERPWRDN_EL1 register definitions */ 1382 #define DSU_CLUSTER_PWR_OFF 0 1383 #define DSU_CLUSTER_PWR_ON 1 1384 #define DSU_CLUSTER_PWR_MASK U(1) 1385 1386 /******************************************************************************* 1387 * Definitions for CPU Power/Performance Management registers 1388 ******************************************************************************/ 1389 1390 #define CPUPPMCR_EL3 S3_6_C15_C2_0 1391 #define CPUPPMCR_EL3_MPMMPINCTL_SHIFT UINT64_C(0) 1392 #define CPUPPMCR_EL3_MPMMPINCTL_MASK UINT64_C(0x1) 1393 1394 #define CPUMPMMCR_EL3 S3_6_C15_C2_1 1395 #define CPUMPMMCR_EL3_MPMM_EN_SHIFT UINT64_C(0) 1396 #define CPUMPMMCR_EL3_MPMM_EN_MASK UINT64_C(0x1) 1397 1398 /* alternative system register encoding for the "sb" speculation barrier */ 1399 #define SYSREG_SB S0_3_C3_C0_7 1400 1401 #endif /* ARCH_H */ 1402