1 /* 2 * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef ARCH_H 9 #define ARCH_H 10 11 #include <lib/utils_def.h> 12 13 /******************************************************************************* 14 * MIDR bit definitions 15 ******************************************************************************/ 16 #define MIDR_IMPL_MASK U(0xff) 17 #define MIDR_IMPL_SHIFT U(0x18) 18 #define MIDR_VAR_SHIFT U(20) 19 #define MIDR_VAR_BITS U(4) 20 #define MIDR_VAR_MASK U(0xf) 21 #define MIDR_REV_SHIFT U(0) 22 #define MIDR_REV_BITS U(4) 23 #define MIDR_REV_MASK U(0xf) 24 #define MIDR_PN_MASK U(0xfff) 25 #define MIDR_PN_SHIFT U(0x4) 26 27 /******************************************************************************* 28 * MPIDR macros 29 ******************************************************************************/ 30 #define MPIDR_MT_MASK (ULL(1) << 24) 31 #define MPIDR_CPU_MASK MPIDR_AFFLVL_MASK 32 #define MPIDR_CLUSTER_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS) 33 #define MPIDR_AFFINITY_BITS U(8) 34 #define MPIDR_AFFLVL_MASK ULL(0xff) 35 #define MPIDR_AFF0_SHIFT U(0) 36 #define MPIDR_AFF1_SHIFT U(8) 37 #define MPIDR_AFF2_SHIFT U(16) 38 #define MPIDR_AFF3_SHIFT U(32) 39 #define MPIDR_AFF_SHIFT(_n) MPIDR_AFF##_n##_SHIFT 40 #define MPIDR_AFFINITY_MASK ULL(0xff00ffffff) 41 #define MPIDR_AFFLVL_SHIFT U(3) 42 #define MPIDR_AFFLVL0 ULL(0x0) 43 #define MPIDR_AFFLVL1 ULL(0x1) 44 #define MPIDR_AFFLVL2 ULL(0x2) 45 #define MPIDR_AFFLVL3 ULL(0x3) 46 #define MPIDR_AFFLVL(_n) MPIDR_AFFLVL##_n 47 #define MPIDR_AFFLVL0_VAL(mpidr) \ 48 (((mpidr) >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK) 49 #define MPIDR_AFFLVL1_VAL(mpidr) \ 50 (((mpidr) >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK) 51 #define MPIDR_AFFLVL2_VAL(mpidr) \ 52 (((mpidr) >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK) 53 #define MPIDR_AFFLVL3_VAL(mpidr) \ 54 (((mpidr) >> MPIDR_AFF3_SHIFT) & MPIDR_AFFLVL_MASK) 55 /* 56 * The MPIDR_MAX_AFFLVL count starts from 0. Take care to 57 * add one while using this macro to define array sizes. 58 * TODO: Support only the first 3 affinity levels for now. 59 */ 60 #define MPIDR_MAX_AFFLVL U(2) 61 62 #define MPID_MASK (MPIDR_MT_MASK | \ 63 (MPIDR_AFFLVL_MASK << MPIDR_AFF3_SHIFT) | \ 64 (MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT) | \ 65 (MPIDR_AFFLVL_MASK << MPIDR_AFF1_SHIFT) | \ 66 (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT)) 67 68 #define MPIDR_AFF_ID(mpid, n) \ 69 (((mpid) >> MPIDR_AFF_SHIFT(n)) & MPIDR_AFFLVL_MASK) 70 71 /* 72 * An invalid MPID. This value can be used by functions that return an MPID to 73 * indicate an error. 74 */ 75 #define INVALID_MPID U(0xFFFFFFFF) 76 77 /******************************************************************************* 78 * Definitions for CPU system register interface to GICv3 79 ******************************************************************************/ 80 #define ICC_IGRPEN1_EL1 S3_0_C12_C12_7 81 #define ICC_SGI1R S3_0_C12_C11_5 82 #define ICC_SRE_EL1 S3_0_C12_C12_5 83 #define ICC_SRE_EL2 S3_4_C12_C9_5 84 #define ICC_SRE_EL3 S3_6_C12_C12_5 85 #define ICC_CTLR_EL1 S3_0_C12_C12_4 86 #define ICC_CTLR_EL3 S3_6_C12_C12_4 87 #define ICC_PMR_EL1 S3_0_C4_C6_0 88 #define ICC_RPR_EL1 S3_0_C12_C11_3 89 #define ICC_IGRPEN1_EL3 S3_6_c12_c12_7 90 #define ICC_IGRPEN0_EL1 S3_0_c12_c12_6 91 #define ICC_HPPIR0_EL1 S3_0_c12_c8_2 92 #define ICC_HPPIR1_EL1 S3_0_c12_c12_2 93 #define ICC_IAR0_EL1 S3_0_c12_c8_0 94 #define ICC_IAR1_EL1 S3_0_c12_c12_0 95 #define ICC_EOIR0_EL1 S3_0_c12_c8_1 96 #define ICC_EOIR1_EL1 S3_0_c12_c12_1 97 #define ICC_SGI0R_EL1 S3_0_c12_c11_7 98 99 /******************************************************************************* 100 * Definitions for EL2 system registers for save/restore routine 101 ******************************************************************************/ 102 103 #define CNTPOFF_EL2 S3_4_C14_C0_6 104 #define HAFGRTR_EL2 S3_4_C3_C1_6 105 #define HDFGRTR_EL2 S3_4_C3_C1_4 106 #define HDFGWTR_EL2 S3_4_C3_C1_5 107 #define HFGITR_EL2 S3_4_C1_C1_6 108 #define HFGRTR_EL2 S3_4_C1_C1_4 109 #define HFGWTR_EL2 S3_4_C1_C1_5 110 #define ICH_HCR_EL2 S3_4_C12_C11_0 111 #define ICH_VMCR_EL2 S3_4_C12_C11_7 112 #define MPAMVPM0_EL2 S3_4_C10_C5_0 113 #define MPAMVPM1_EL2 S3_4_C10_C5_1 114 #define MPAMVPM2_EL2 S3_4_C10_C5_2 115 #define MPAMVPM3_EL2 S3_4_C10_C5_3 116 #define MPAMVPM4_EL2 S3_4_C10_C5_4 117 #define MPAMVPM5_EL2 S3_4_C10_C5_5 118 #define MPAMVPM6_EL2 S3_4_C10_C5_6 119 #define MPAMVPM7_EL2 S3_4_C10_C5_7 120 #define MPAMVPMV_EL2 S3_4_C10_C4_1 121 #define TRFCR_EL2 S3_4_C1_C2_1 122 #define PMSCR_EL2 S3_4_C9_C9_0 123 #define TFSR_EL2 S3_4_C5_C6_0 124 125 /******************************************************************************* 126 * Generic timer memory mapped registers & offsets 127 ******************************************************************************/ 128 #define CNTCR_OFF U(0x000) 129 #define CNTCV_OFF U(0x008) 130 #define CNTFID_OFF U(0x020) 131 132 #define CNTCR_EN (U(1) << 0) 133 #define CNTCR_HDBG (U(1) << 1) 134 #define CNTCR_FCREQ(x) ((x) << 8) 135 136 /******************************************************************************* 137 * System register bit definitions 138 ******************************************************************************/ 139 /* CLIDR definitions */ 140 #define LOUIS_SHIFT U(21) 141 #define LOC_SHIFT U(24) 142 #define CTYPE_SHIFT(n) U(3 * (n - 1)) 143 #define CLIDR_FIELD_WIDTH U(3) 144 145 /* CSSELR definitions */ 146 #define LEVEL_SHIFT U(1) 147 148 /* Data cache set/way op type defines */ 149 #define DCISW U(0x0) 150 #define DCCISW U(0x1) 151 #if ERRATA_A53_827319 152 #define DCCSW DCCISW 153 #else 154 #define DCCSW U(0x2) 155 #endif 156 157 /* ID_AA64PFR0_EL1 definitions */ 158 #define ID_AA64PFR0_EL0_SHIFT U(0) 159 #define ID_AA64PFR0_EL1_SHIFT U(4) 160 #define ID_AA64PFR0_EL2_SHIFT U(8) 161 #define ID_AA64PFR0_EL3_SHIFT U(12) 162 #define ID_AA64PFR0_AMU_SHIFT U(44) 163 #define ID_AA64PFR0_AMU_MASK ULL(0xf) 164 #define ID_AA64PFR0_AMU_NOT_SUPPORTED U(0x0) 165 #define ID_AA64PFR0_AMU_V1 U(0x1) 166 #define ID_AA64PFR0_AMU_V1P1 U(0x2) 167 #define ID_AA64PFR0_ELX_MASK ULL(0xf) 168 #define ID_AA64PFR0_GIC_SHIFT U(24) 169 #define ID_AA64PFR0_GIC_WIDTH U(4) 170 #define ID_AA64PFR0_GIC_MASK ULL(0xf) 171 #define ID_AA64PFR0_SVE_SHIFT U(32) 172 #define ID_AA64PFR0_SVE_MASK ULL(0xf) 173 #define ID_AA64PFR0_SVE_LENGTH U(4) 174 #define ID_AA64PFR0_SEL2_SHIFT U(36) 175 #define ID_AA64PFR0_SEL2_MASK ULL(0xf) 176 #define ID_AA64PFR0_MPAM_SHIFT U(40) 177 #define ID_AA64PFR0_MPAM_MASK ULL(0xf) 178 #define ID_AA64PFR0_DIT_SHIFT U(48) 179 #define ID_AA64PFR0_DIT_MASK ULL(0xf) 180 #define ID_AA64PFR0_DIT_LENGTH U(4) 181 #define ID_AA64PFR0_DIT_SUPPORTED U(1) 182 #define ID_AA64PFR0_CSV2_SHIFT U(56) 183 #define ID_AA64PFR0_CSV2_MASK ULL(0xf) 184 #define ID_AA64PFR0_CSV2_LENGTH U(4) 185 186 /* Exception level handling */ 187 #define EL_IMPL_NONE ULL(0) 188 #define EL_IMPL_A64ONLY ULL(1) 189 #define EL_IMPL_A64_A32 ULL(2) 190 191 /* ID_AA64DFR0_EL1.PMS definitions (for ARMv8.2+) */ 192 #define ID_AA64DFR0_PMS_SHIFT U(32) 193 #define ID_AA64DFR0_PMS_MASK ULL(0xf) 194 195 /* ID_AA64DFR0_EL1.MTPMU definitions (for ARMv8.6+) */ 196 #define ID_AA64DFR0_MTPMU_SHIFT U(48) 197 #define ID_AA64DFR0_MTPMU_MASK ULL(0xf) 198 #define ID_AA64DFR0_MTPMU_SUPPORTED ULL(1) 199 200 /* ID_AA64ISAR0_EL1 definitions */ 201 #define ID_AA64ISAR0_RNDR_SHIFT U(60) 202 #define ID_AA64ISAR0_RNDR_MASK ULL(0xf) 203 204 /* ID_AA64ISAR1_EL1 definitions */ 205 #define ID_AA64ISAR1_EL1 S3_0_C0_C6_1 206 #define ID_AA64ISAR1_GPI_SHIFT U(28) 207 #define ID_AA64ISAR1_GPI_MASK ULL(0xf) 208 #define ID_AA64ISAR1_GPA_SHIFT U(24) 209 #define ID_AA64ISAR1_GPA_MASK ULL(0xf) 210 #define ID_AA64ISAR1_API_SHIFT U(8) 211 #define ID_AA64ISAR1_API_MASK ULL(0xf) 212 #define ID_AA64ISAR1_APA_SHIFT U(4) 213 #define ID_AA64ISAR1_APA_MASK ULL(0xf) 214 215 /* ID_AA64MMFR0_EL1 definitions */ 216 #define ID_AA64MMFR0_EL1_PARANGE_SHIFT U(0) 217 #define ID_AA64MMFR0_EL1_PARANGE_MASK ULL(0xf) 218 219 #define PARANGE_0000 U(32) 220 #define PARANGE_0001 U(36) 221 #define PARANGE_0010 U(40) 222 #define PARANGE_0011 U(42) 223 #define PARANGE_0100 U(44) 224 #define PARANGE_0101 U(48) 225 #define PARANGE_0110 U(52) 226 227 #define ID_AA64MMFR0_EL1_ECV_SHIFT U(60) 228 #define ID_AA64MMFR0_EL1_ECV_MASK ULL(0xf) 229 #define ID_AA64MMFR0_EL1_ECV_NOT_SUPPORTED ULL(0x0) 230 #define ID_AA64MMFR0_EL1_ECV_SUPPORTED ULL(0x1) 231 #define ID_AA64MMFR0_EL1_ECV_SELF_SYNCH ULL(0x2) 232 233 #define ID_AA64MMFR0_EL1_FGT_SHIFT U(56) 234 #define ID_AA64MMFR0_EL1_FGT_MASK ULL(0xf) 235 #define ID_AA64MMFR0_EL1_FGT_SUPPORTED ULL(0x1) 236 #define ID_AA64MMFR0_EL1_FGT_NOT_SUPPORTED ULL(0x0) 237 238 #define ID_AA64MMFR0_EL1_TGRAN4_SHIFT U(28) 239 #define ID_AA64MMFR0_EL1_TGRAN4_MASK ULL(0xf) 240 #define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED ULL(0x0) 241 #define ID_AA64MMFR0_EL1_TGRAN4_NOT_SUPPORTED ULL(0xf) 242 243 #define ID_AA64MMFR0_EL1_TGRAN64_SHIFT U(24) 244 #define ID_AA64MMFR0_EL1_TGRAN64_MASK ULL(0xf) 245 #define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED ULL(0x0) 246 #define ID_AA64MMFR0_EL1_TGRAN64_NOT_SUPPORTED ULL(0xf) 247 248 #define ID_AA64MMFR0_EL1_TGRAN16_SHIFT U(20) 249 #define ID_AA64MMFR0_EL1_TGRAN16_MASK ULL(0xf) 250 #define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED ULL(0x1) 251 #define ID_AA64MMFR0_EL1_TGRAN16_NOT_SUPPORTED ULL(0x0) 252 253 /* ID_AA64MMFR1_EL1 definitions */ 254 #define ID_AA64MMFR1_EL1_TWED_SHIFT U(32) 255 #define ID_AA64MMFR1_EL1_TWED_MASK ULL(0xf) 256 #define ID_AA64MMFR1_EL1_TWED_SUPPORTED ULL(0x1) 257 #define ID_AA64MMFR1_EL1_TWED_NOT_SUPPORTED ULL(0x0) 258 259 #define ID_AA64MMFR1_EL1_PAN_SHIFT U(20) 260 #define ID_AA64MMFR1_EL1_PAN_MASK ULL(0xf) 261 #define ID_AA64MMFR1_EL1_PAN_NOT_SUPPORTED ULL(0x0) 262 #define ID_AA64MMFR1_EL1_PAN_SUPPORTED ULL(0x1) 263 #define ID_AA64MMFR1_EL1_PAN2_SUPPORTED ULL(0x2) 264 #define ID_AA64MMFR1_EL1_PAN3_SUPPORTED ULL(0x3) 265 266 /* ID_AA64MMFR2_EL1 definitions */ 267 #define ID_AA64MMFR2_EL1 S3_0_C0_C7_2 268 269 #define ID_AA64MMFR2_EL1_ST_SHIFT U(28) 270 #define ID_AA64MMFR2_EL1_ST_MASK ULL(0xf) 271 272 #define ID_AA64MMFR2_EL1_CNP_SHIFT U(0) 273 #define ID_AA64MMFR2_EL1_CNP_MASK ULL(0xf) 274 275 /* ID_AA64PFR1_EL1 definitions */ 276 #define ID_AA64PFR1_EL1_SSBS_SHIFT U(4) 277 #define ID_AA64PFR1_EL1_SSBS_MASK ULL(0xf) 278 279 #define SSBS_UNAVAILABLE ULL(0) /* No architectural SSBS support */ 280 281 #define ID_AA64PFR1_EL1_BT_SHIFT U(0) 282 #define ID_AA64PFR1_EL1_BT_MASK ULL(0xf) 283 284 #define BTI_IMPLEMENTED ULL(1) /* The BTI mechanism is implemented */ 285 286 #define ID_AA64PFR1_EL1_MTE_SHIFT U(8) 287 #define ID_AA64PFR1_EL1_MTE_MASK ULL(0xf) 288 289 /* Memory Tagging Extension is not implemented */ 290 #define MTE_UNIMPLEMENTED U(0) 291 /* FEAT_MTE: MTE instructions accessible at EL0 are implemented */ 292 #define MTE_IMPLEMENTED_EL0 U(1) 293 /* FEAT_MTE2: Full MTE is implemented */ 294 #define MTE_IMPLEMENTED_ELX U(2) 295 /* 296 * FEAT_MTE3: MTE is implemented with support for 297 * asymmetric Tag Check Fault handling 298 */ 299 #define MTE_IMPLEMENTED_ASY U(3) 300 301 #define ID_AA64PFR1_MPAM_FRAC_SHIFT ULL(16) 302 #define ID_AA64PFR1_MPAM_FRAC_MASK ULL(0xf) 303 304 /* ID_PFR1_EL1 definitions */ 305 #define ID_PFR1_VIRTEXT_SHIFT U(12) 306 #define ID_PFR1_VIRTEXT_MASK U(0xf) 307 #define GET_VIRT_EXT(id) (((id) >> ID_PFR1_VIRTEXT_SHIFT) \ 308 & ID_PFR1_VIRTEXT_MASK) 309 310 /* SCTLR definitions */ 311 #define SCTLR_EL2_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ 312 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \ 313 (U(1) << 11) | (U(1) << 5) | (U(1) << 4)) 314 315 #define SCTLR_EL1_RES1 ((UL(1) << 29) | (UL(1) << 28) | (UL(1) << 23) | \ 316 (UL(1) << 22) | (UL(1) << 20) | (UL(1) << 11)) 317 318 #define SCTLR_AARCH32_EL1_RES1 \ 319 ((U(1) << 23) | (U(1) << 22) | (U(1) << 11) | \ 320 (U(1) << 4) | (U(1) << 3)) 321 322 #define SCTLR_EL3_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ 323 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \ 324 (U(1) << 11) | (U(1) << 5) | (U(1) << 4)) 325 326 #define SCTLR_M_BIT (ULL(1) << 0) 327 #define SCTLR_A_BIT (ULL(1) << 1) 328 #define SCTLR_C_BIT (ULL(1) << 2) 329 #define SCTLR_SA_BIT (ULL(1) << 3) 330 #define SCTLR_SA0_BIT (ULL(1) << 4) 331 #define SCTLR_CP15BEN_BIT (ULL(1) << 5) 332 #define SCTLR_nAA_BIT (ULL(1) << 6) 333 #define SCTLR_ITD_BIT (ULL(1) << 7) 334 #define SCTLR_SED_BIT (ULL(1) << 8) 335 #define SCTLR_UMA_BIT (ULL(1) << 9) 336 #define SCTLR_EnRCTX_BIT (ULL(1) << 10) 337 #define SCTLR_EOS_BIT (ULL(1) << 11) 338 #define SCTLR_I_BIT (ULL(1) << 12) 339 #define SCTLR_EnDB_BIT (ULL(1) << 13) 340 #define SCTLR_DZE_BIT (ULL(1) << 14) 341 #define SCTLR_UCT_BIT (ULL(1) << 15) 342 #define SCTLR_NTWI_BIT (ULL(1) << 16) 343 #define SCTLR_NTWE_BIT (ULL(1) << 18) 344 #define SCTLR_WXN_BIT (ULL(1) << 19) 345 #define SCTLR_TSCXT_BIT (ULL(1) << 20) 346 #define SCTLR_IESB_BIT (ULL(1) << 21) 347 #define SCTLR_EIS_BIT (ULL(1) << 22) 348 #define SCTLR_SPAN_BIT (ULL(1) << 23) 349 #define SCTLR_E0E_BIT (ULL(1) << 24) 350 #define SCTLR_EE_BIT (ULL(1) << 25) 351 #define SCTLR_UCI_BIT (ULL(1) << 26) 352 #define SCTLR_EnDA_BIT (ULL(1) << 27) 353 #define SCTLR_nTLSMD_BIT (ULL(1) << 28) 354 #define SCTLR_LSMAOE_BIT (ULL(1) << 29) 355 #define SCTLR_EnIB_BIT (ULL(1) << 30) 356 #define SCTLR_EnIA_BIT (ULL(1) << 31) 357 #define SCTLR_BT0_BIT (ULL(1) << 35) 358 #define SCTLR_BT1_BIT (ULL(1) << 36) 359 #define SCTLR_BT_BIT (ULL(1) << 36) 360 #define SCTLR_ITFSB_BIT (ULL(1) << 37) 361 #define SCTLR_TCF0_SHIFT U(38) 362 #define SCTLR_TCF0_MASK ULL(3) 363 364 /* Tag Check Faults in EL0 have no effect on the PE */ 365 #define SCTLR_TCF0_NO_EFFECT U(0) 366 /* Tag Check Faults in EL0 cause a synchronous exception */ 367 #define SCTLR_TCF0_SYNC U(1) 368 /* Tag Check Faults in EL0 are asynchronously accumulated */ 369 #define SCTLR_TCF0_ASYNC U(2) 370 /* 371 * Tag Check Faults in EL0 cause a synchronous exception on reads, 372 * and are asynchronously accumulated on writes 373 */ 374 #define SCTLR_TCF0_SYNCR_ASYNCW U(3) 375 376 #define SCTLR_TCF_SHIFT U(40) 377 #define SCTLR_TCF_MASK ULL(3) 378 379 /* Tag Check Faults in EL1 have no effect on the PE */ 380 #define SCTLR_TCF_NO_EFFECT U(0) 381 /* Tag Check Faults in EL1 cause a synchronous exception */ 382 #define SCTLR_TCF_SYNC U(1) 383 /* Tag Check Faults in EL1 are asynchronously accumulated */ 384 #define SCTLR_TCF_ASYNC U(2) 385 /* 386 * Tag Check Faults in EL1 cause a synchronous exception on reads, 387 * and are asynchronously accumulated on writes 388 */ 389 #define SCTLR_TCF_SYNCR_ASYNCW U(3) 390 391 #define SCTLR_ATA0_BIT (ULL(1) << 42) 392 #define SCTLR_ATA_BIT (ULL(1) << 43) 393 #define SCTLR_DSSBS_BIT (ULL(1) << 44) 394 #define SCTLR_TWEDEn_BIT (ULL(1) << 45) 395 #define SCTLR_TWEDEL_SHIFT U(46) 396 #define SCTLR_TWEDEL_MASK ULL(0xf) 397 #define SCTLR_EnASR_BIT (ULL(1) << 54) 398 #define SCTLR_EnAS0_BIT (ULL(1) << 55) 399 #define SCTLR_EnALS_BIT (ULL(1) << 56) 400 #define SCTLR_EPAN_BIT (ULL(1) << 57) 401 #define SCTLR_RESET_VAL SCTLR_EL3_RES1 402 403 /* CPACR_EL1 definitions */ 404 #define CPACR_EL1_FPEN(x) ((x) << 20) 405 #define CPACR_EL1_FP_TRAP_EL0 UL(0x1) 406 #define CPACR_EL1_FP_TRAP_ALL UL(0x2) 407 #define CPACR_EL1_FP_TRAP_NONE UL(0x3) 408 409 /* SCR definitions */ 410 #define SCR_RES1_BITS ((U(1) << 4) | (U(1) << 5)) 411 #define SCR_TWEDEL_SHIFT U(30) 412 #define SCR_TWEDEL_MASK ULL(0xf) 413 #define SCR_AMVOFFEN_BIT (UL(1) << 35) 414 #define SCR_TWEDEn_BIT (UL(1) << 29) 415 #define SCR_ECVEN_BIT (UL(1) << 28) 416 #define SCR_FGTEN_BIT (UL(1) << 27) 417 #define SCR_ATA_BIT (UL(1) << 26) 418 #define SCR_FIEN_BIT (UL(1) << 21) 419 #define SCR_EEL2_BIT (UL(1) << 18) 420 #define SCR_API_BIT (UL(1) << 17) 421 #define SCR_APK_BIT (UL(1) << 16) 422 #define SCR_TERR_BIT (UL(1) << 15) 423 #define SCR_TWE_BIT (UL(1) << 13) 424 #define SCR_TWI_BIT (UL(1) << 12) 425 #define SCR_ST_BIT (UL(1) << 11) 426 #define SCR_RW_BIT (UL(1) << 10) 427 #define SCR_SIF_BIT (UL(1) << 9) 428 #define SCR_HCE_BIT (UL(1) << 8) 429 #define SCR_SMD_BIT (UL(1) << 7) 430 #define SCR_EA_BIT (UL(1) << 3) 431 #define SCR_FIQ_BIT (UL(1) << 2) 432 #define SCR_IRQ_BIT (UL(1) << 1) 433 #define SCR_NS_BIT (UL(1) << 0) 434 #define SCR_VALID_BIT_MASK U(0x2f8f) 435 #define SCR_RESET_VAL SCR_RES1_BITS 436 437 /* MDCR_EL3 definitions */ 438 #define MDCR_EnPMSN_BIT (ULL(1) << 36) 439 #define MDCR_MPMX_BIT (ULL(1) << 35) 440 #define MDCR_MCCD_BIT (ULL(1) << 34) 441 #define MDCR_MTPME_BIT (ULL(1) << 28) 442 #define MDCR_TDCC_BIT (ULL(1) << 27) 443 #define MDCR_SCCD_BIT (ULL(1) << 23) 444 #define MDCR_EPMAD_BIT (ULL(1) << 21) 445 #define MDCR_EDAD_BIT (ULL(1) << 20) 446 #define MDCR_TTRF_BIT (ULL(1) << 19) 447 #define MDCR_STE_BIT (ULL(1) << 18) 448 #define MDCR_SPME_BIT (ULL(1) << 17) 449 #define MDCR_SDD_BIT (ULL(1) << 16) 450 #define MDCR_SPD32(x) ((x) << 14) 451 #define MDCR_SPD32_LEGACY ULL(0x0) 452 #define MDCR_SPD32_DISABLE ULL(0x2) 453 #define MDCR_SPD32_ENABLE ULL(0x3) 454 #define MDCR_NSPB(x) ((x) << 12) 455 #define MDCR_NSPB_EL1 ULL(0x3) 456 #define MDCR_TDOSA_BIT (ULL(1) << 10) 457 #define MDCR_TDA_BIT (ULL(1) << 9) 458 #define MDCR_TPM_BIT (ULL(1) << 6) 459 #define MDCR_EL3_RESET_VAL ULL(0x0) 460 461 /* MDCR_EL2 definitions */ 462 #define MDCR_EL2_MTPME (U(1) << 28) 463 #define MDCR_EL2_HLP (U(1) << 26) 464 #define MDCR_EL2_HCCD (U(1) << 23) 465 #define MDCR_EL2_TTRF (U(1) << 19) 466 #define MDCR_EL2_HPMD (U(1) << 17) 467 #define MDCR_EL2_TPMS (U(1) << 14) 468 #define MDCR_EL2_E2PB(x) ((x) << 12) 469 #define MDCR_EL2_E2PB_EL1 U(0x3) 470 #define MDCR_EL2_TDRA_BIT (U(1) << 11) 471 #define MDCR_EL2_TDOSA_BIT (U(1) << 10) 472 #define MDCR_EL2_TDA_BIT (U(1) << 9) 473 #define MDCR_EL2_TDE_BIT (U(1) << 8) 474 #define MDCR_EL2_HPME_BIT (U(1) << 7) 475 #define MDCR_EL2_TPM_BIT (U(1) << 6) 476 #define MDCR_EL2_TPMCR_BIT (U(1) << 5) 477 #define MDCR_EL2_RESET_VAL U(0x0) 478 479 /* HSTR_EL2 definitions */ 480 #define HSTR_EL2_RESET_VAL U(0x0) 481 #define HSTR_EL2_T_MASK U(0xff) 482 483 /* CNTHP_CTL_EL2 definitions */ 484 #define CNTHP_CTL_ENABLE_BIT (U(1) << 0) 485 #define CNTHP_CTL_RESET_VAL U(0x0) 486 487 /* VTTBR_EL2 definitions */ 488 #define VTTBR_RESET_VAL ULL(0x0) 489 #define VTTBR_VMID_MASK ULL(0xff) 490 #define VTTBR_VMID_SHIFT U(48) 491 #define VTTBR_BADDR_MASK ULL(0xffffffffffff) 492 #define VTTBR_BADDR_SHIFT U(0) 493 494 /* HCR definitions */ 495 #define HCR_AMVOFFEN_BIT (ULL(1) << 51) 496 #define HCR_API_BIT (ULL(1) << 41) 497 #define HCR_APK_BIT (ULL(1) << 40) 498 #define HCR_E2H_BIT (ULL(1) << 34) 499 #define HCR_TGE_BIT (ULL(1) << 27) 500 #define HCR_RW_SHIFT U(31) 501 #define HCR_RW_BIT (ULL(1) << HCR_RW_SHIFT) 502 #define HCR_AMO_BIT (ULL(1) << 5) 503 #define HCR_IMO_BIT (ULL(1) << 4) 504 #define HCR_FMO_BIT (ULL(1) << 3) 505 506 /* ISR definitions */ 507 #define ISR_A_SHIFT U(8) 508 #define ISR_I_SHIFT U(7) 509 #define ISR_F_SHIFT U(6) 510 511 /* CNTHCTL_EL2 definitions */ 512 #define CNTHCTL_RESET_VAL U(0x0) 513 #define EVNTEN_BIT (U(1) << 2) 514 #define EL1PCEN_BIT (U(1) << 1) 515 #define EL1PCTEN_BIT (U(1) << 0) 516 517 /* CNTKCTL_EL1 definitions */ 518 #define EL0PTEN_BIT (U(1) << 9) 519 #define EL0VTEN_BIT (U(1) << 8) 520 #define EL0PCTEN_BIT (U(1) << 0) 521 #define EL0VCTEN_BIT (U(1) << 1) 522 #define EVNTEN_BIT (U(1) << 2) 523 #define EVNTDIR_BIT (U(1) << 3) 524 #define EVNTI_SHIFT U(4) 525 #define EVNTI_MASK U(0xf) 526 527 /* CPTR_EL3 definitions */ 528 #define TCPAC_BIT (U(1) << 31) 529 #define TAM_BIT (U(1) << 30) 530 #define TTA_BIT (U(1) << 20) 531 #define TFP_BIT (U(1) << 10) 532 #define CPTR_EZ_BIT (U(1) << 8) 533 #define CPTR_EL3_RESET_VAL (TCPAC_BIT | TAM_BIT | TTA_BIT | TFP_BIT & ~(CPTR_EZ_BIT)) 534 535 /* CPTR_EL2 definitions */ 536 #define CPTR_EL2_RES1 ((U(1) << 13) | (U(1) << 12) | (U(0x3ff))) 537 #define CPTR_EL2_TCPAC_BIT (U(1) << 31) 538 #define CPTR_EL2_TAM_BIT (U(1) << 30) 539 #define CPTR_EL2_TTA_BIT (U(1) << 20) 540 #define CPTR_EL2_TFP_BIT (U(1) << 10) 541 #define CPTR_EL2_TZ_BIT (U(1) << 8) 542 #define CPTR_EL2_RESET_VAL CPTR_EL2_RES1 543 544 /* CPSR/SPSR definitions */ 545 #define DAIF_FIQ_BIT (U(1) << 0) 546 #define DAIF_IRQ_BIT (U(1) << 1) 547 #define DAIF_ABT_BIT (U(1) << 2) 548 #define DAIF_DBG_BIT (U(1) << 3) 549 #define SPSR_DAIF_SHIFT U(6) 550 #define SPSR_DAIF_MASK U(0xf) 551 552 #define SPSR_AIF_SHIFT U(6) 553 #define SPSR_AIF_MASK U(0x7) 554 555 #define SPSR_E_SHIFT U(9) 556 #define SPSR_E_MASK U(0x1) 557 #define SPSR_E_LITTLE U(0x0) 558 #define SPSR_E_BIG U(0x1) 559 560 #define SPSR_T_SHIFT U(5) 561 #define SPSR_T_MASK U(0x1) 562 #define SPSR_T_ARM U(0x0) 563 #define SPSR_T_THUMB U(0x1) 564 565 #define SPSR_M_SHIFT U(4) 566 #define SPSR_M_MASK U(0x1) 567 #define SPSR_M_AARCH64 U(0x0) 568 #define SPSR_M_AARCH32 U(0x1) 569 570 #define SPSR_EL_SHIFT U(2) 571 #define SPSR_EL_WIDTH U(2) 572 573 #define SPSR_SSBS_BIT_AARCH64 BIT_64(12) 574 #define SPSR_SSBS_BIT_AARCH32 BIT_64(23) 575 576 #define DISABLE_ALL_EXCEPTIONS \ 577 (DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT | DAIF_DBG_BIT) 578 579 #define DISABLE_INTERRUPTS (DAIF_FIQ_BIT | DAIF_IRQ_BIT) 580 581 /* 582 * RMR_EL3 definitions 583 */ 584 #define RMR_EL3_RR_BIT (U(1) << 1) 585 #define RMR_EL3_AA64_BIT (U(1) << 0) 586 587 /* 588 * HI-VECTOR address for AArch32 state 589 */ 590 #define HI_VECTOR_BASE U(0xFFFF0000) 591 592 /* 593 * TCR defintions 594 */ 595 #define TCR_EL3_RES1 ((ULL(1) << 31) | (ULL(1) << 23)) 596 #define TCR_EL2_RES1 ((ULL(1) << 31) | (ULL(1) << 23)) 597 #define TCR_EL1_IPS_SHIFT U(32) 598 #define TCR_EL2_PS_SHIFT U(16) 599 #define TCR_EL3_PS_SHIFT U(16) 600 601 #define TCR_TxSZ_MIN ULL(16) 602 #define TCR_TxSZ_MAX ULL(39) 603 #define TCR_TxSZ_MAX_TTST ULL(48) 604 605 #define TCR_T0SZ_SHIFT U(0) 606 #define TCR_T1SZ_SHIFT U(16) 607 608 /* (internal) physical address size bits in EL3/EL1 */ 609 #define TCR_PS_BITS_4GB ULL(0x0) 610 #define TCR_PS_BITS_64GB ULL(0x1) 611 #define TCR_PS_BITS_1TB ULL(0x2) 612 #define TCR_PS_BITS_4TB ULL(0x3) 613 #define TCR_PS_BITS_16TB ULL(0x4) 614 #define TCR_PS_BITS_256TB ULL(0x5) 615 616 #define ADDR_MASK_48_TO_63 ULL(0xFFFF000000000000) 617 #define ADDR_MASK_44_TO_47 ULL(0x0000F00000000000) 618 #define ADDR_MASK_42_TO_43 ULL(0x00000C0000000000) 619 #define ADDR_MASK_40_TO_41 ULL(0x0000030000000000) 620 #define ADDR_MASK_36_TO_39 ULL(0x000000F000000000) 621 #define ADDR_MASK_32_TO_35 ULL(0x0000000F00000000) 622 623 #define TCR_RGN_INNER_NC (ULL(0x0) << 8) 624 #define TCR_RGN_INNER_WBA (ULL(0x1) << 8) 625 #define TCR_RGN_INNER_WT (ULL(0x2) << 8) 626 #define TCR_RGN_INNER_WBNA (ULL(0x3) << 8) 627 628 #define TCR_RGN_OUTER_NC (ULL(0x0) << 10) 629 #define TCR_RGN_OUTER_WBA (ULL(0x1) << 10) 630 #define TCR_RGN_OUTER_WT (ULL(0x2) << 10) 631 #define TCR_RGN_OUTER_WBNA (ULL(0x3) << 10) 632 633 #define TCR_SH_NON_SHAREABLE (ULL(0x0) << 12) 634 #define TCR_SH_OUTER_SHAREABLE (ULL(0x2) << 12) 635 #define TCR_SH_INNER_SHAREABLE (ULL(0x3) << 12) 636 637 #define TCR_RGN1_INNER_NC (ULL(0x0) << 24) 638 #define TCR_RGN1_INNER_WBA (ULL(0x1) << 24) 639 #define TCR_RGN1_INNER_WT (ULL(0x2) << 24) 640 #define TCR_RGN1_INNER_WBNA (ULL(0x3) << 24) 641 642 #define TCR_RGN1_OUTER_NC (ULL(0x0) << 26) 643 #define TCR_RGN1_OUTER_WBA (ULL(0x1) << 26) 644 #define TCR_RGN1_OUTER_WT (ULL(0x2) << 26) 645 #define TCR_RGN1_OUTER_WBNA (ULL(0x3) << 26) 646 647 #define TCR_SH1_NON_SHAREABLE (ULL(0x0) << 28) 648 #define TCR_SH1_OUTER_SHAREABLE (ULL(0x2) << 28) 649 #define TCR_SH1_INNER_SHAREABLE (ULL(0x3) << 28) 650 651 #define TCR_TG0_SHIFT U(14) 652 #define TCR_TG0_MASK ULL(3) 653 #define TCR_TG0_4K (ULL(0) << TCR_TG0_SHIFT) 654 #define TCR_TG0_64K (ULL(1) << TCR_TG0_SHIFT) 655 #define TCR_TG0_16K (ULL(2) << TCR_TG0_SHIFT) 656 657 #define TCR_TG1_SHIFT U(30) 658 #define TCR_TG1_MASK ULL(3) 659 #define TCR_TG1_16K (ULL(1) << TCR_TG1_SHIFT) 660 #define TCR_TG1_4K (ULL(2) << TCR_TG1_SHIFT) 661 #define TCR_TG1_64K (ULL(3) << TCR_TG1_SHIFT) 662 663 #define TCR_EPD0_BIT (ULL(1) << 7) 664 #define TCR_EPD1_BIT (ULL(1) << 23) 665 666 #define MODE_SP_SHIFT U(0x0) 667 #define MODE_SP_MASK U(0x1) 668 #define MODE_SP_EL0 U(0x0) 669 #define MODE_SP_ELX U(0x1) 670 671 #define MODE_RW_SHIFT U(0x4) 672 #define MODE_RW_MASK U(0x1) 673 #define MODE_RW_64 U(0x0) 674 #define MODE_RW_32 U(0x1) 675 676 #define MODE_EL_SHIFT U(0x2) 677 #define MODE_EL_MASK U(0x3) 678 #define MODE_EL_WIDTH U(0x2) 679 #define MODE_EL3 U(0x3) 680 #define MODE_EL2 U(0x2) 681 #define MODE_EL1 U(0x1) 682 #define MODE_EL0 U(0x0) 683 684 #define MODE32_SHIFT U(0) 685 #define MODE32_MASK U(0xf) 686 #define MODE32_usr U(0x0) 687 #define MODE32_fiq U(0x1) 688 #define MODE32_irq U(0x2) 689 #define MODE32_svc U(0x3) 690 #define MODE32_mon U(0x6) 691 #define MODE32_abt U(0x7) 692 #define MODE32_hyp U(0xa) 693 #define MODE32_und U(0xb) 694 #define MODE32_sys U(0xf) 695 696 #define GET_RW(mode) (((mode) >> MODE_RW_SHIFT) & MODE_RW_MASK) 697 #define GET_EL(mode) (((mode) >> MODE_EL_SHIFT) & MODE_EL_MASK) 698 #define GET_SP(mode) (((mode) >> MODE_SP_SHIFT) & MODE_SP_MASK) 699 #define GET_M32(mode) (((mode) >> MODE32_SHIFT) & MODE32_MASK) 700 701 #define SPSR_64(el, sp, daif) \ 702 (((MODE_RW_64 << MODE_RW_SHIFT) | \ 703 (((el) & MODE_EL_MASK) << MODE_EL_SHIFT) | \ 704 (((sp) & MODE_SP_MASK) << MODE_SP_SHIFT) | \ 705 (((daif) & SPSR_DAIF_MASK) << SPSR_DAIF_SHIFT)) & \ 706 (~(SPSR_SSBS_BIT_AARCH64))) 707 708 #define SPSR_MODE32(mode, isa, endian, aif) \ 709 (((MODE_RW_32 << MODE_RW_SHIFT) | \ 710 (((mode) & MODE32_MASK) << MODE32_SHIFT) | \ 711 (((isa) & SPSR_T_MASK) << SPSR_T_SHIFT) | \ 712 (((endian) & SPSR_E_MASK) << SPSR_E_SHIFT) | \ 713 (((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT)) & \ 714 (~(SPSR_SSBS_BIT_AARCH32))) 715 716 /* 717 * TTBR Definitions 718 */ 719 #define TTBR_CNP_BIT ULL(0x1) 720 721 /* 722 * CTR_EL0 definitions 723 */ 724 #define CTR_CWG_SHIFT U(24) 725 #define CTR_CWG_MASK U(0xf) 726 #define CTR_ERG_SHIFT U(20) 727 #define CTR_ERG_MASK U(0xf) 728 #define CTR_DMINLINE_SHIFT U(16) 729 #define CTR_DMINLINE_MASK U(0xf) 730 #define CTR_L1IP_SHIFT U(14) 731 #define CTR_L1IP_MASK U(0x3) 732 #define CTR_IMINLINE_SHIFT U(0) 733 #define CTR_IMINLINE_MASK U(0xf) 734 735 #define MAX_CACHE_LINE_SIZE U(0x800) /* 2KB */ 736 737 /* Physical timer control register bit fields shifts and masks */ 738 #define CNTP_CTL_ENABLE_SHIFT U(0) 739 #define CNTP_CTL_IMASK_SHIFT U(1) 740 #define CNTP_CTL_ISTATUS_SHIFT U(2) 741 742 #define CNTP_CTL_ENABLE_MASK U(1) 743 #define CNTP_CTL_IMASK_MASK U(1) 744 #define CNTP_CTL_ISTATUS_MASK U(1) 745 746 /* Physical timer control macros */ 747 #define CNTP_CTL_ENABLE_BIT (U(1) << CNTP_CTL_ENABLE_SHIFT) 748 #define CNTP_CTL_IMASK_BIT (U(1) << CNTP_CTL_IMASK_SHIFT) 749 750 /* Exception Syndrome register bits and bobs */ 751 #define ESR_EC_SHIFT U(26) 752 #define ESR_EC_MASK U(0x3f) 753 #define ESR_EC_LENGTH U(6) 754 #define ESR_ISS_SHIFT U(0) 755 #define ESR_ISS_LENGTH U(25) 756 #define EC_UNKNOWN U(0x0) 757 #define EC_WFE_WFI U(0x1) 758 #define EC_AARCH32_CP15_MRC_MCR U(0x3) 759 #define EC_AARCH32_CP15_MRRC_MCRR U(0x4) 760 #define EC_AARCH32_CP14_MRC_MCR U(0x5) 761 #define EC_AARCH32_CP14_LDC_STC U(0x6) 762 #define EC_FP_SIMD U(0x7) 763 #define EC_AARCH32_CP10_MRC U(0x8) 764 #define EC_AARCH32_CP14_MRRC_MCRR U(0xc) 765 #define EC_ILLEGAL U(0xe) 766 #define EC_AARCH32_SVC U(0x11) 767 #define EC_AARCH32_HVC U(0x12) 768 #define EC_AARCH32_SMC U(0x13) 769 #define EC_AARCH64_SVC U(0x15) 770 #define EC_AARCH64_HVC U(0x16) 771 #define EC_AARCH64_SMC U(0x17) 772 #define EC_AARCH64_SYS U(0x18) 773 #define EC_IABORT_LOWER_EL U(0x20) 774 #define EC_IABORT_CUR_EL U(0x21) 775 #define EC_PC_ALIGN U(0x22) 776 #define EC_DABORT_LOWER_EL U(0x24) 777 #define EC_DABORT_CUR_EL U(0x25) 778 #define EC_SP_ALIGN U(0x26) 779 #define EC_AARCH32_FP U(0x28) 780 #define EC_AARCH64_FP U(0x2c) 781 #define EC_SERROR U(0x2f) 782 #define EC_BRK U(0x3c) 783 784 /* 785 * External Abort bit in Instruction and Data Aborts synchronous exception 786 * syndromes. 787 */ 788 #define ESR_ISS_EABORT_EA_BIT U(9) 789 790 #define EC_BITS(x) (((x) >> ESR_EC_SHIFT) & ESR_EC_MASK) 791 792 /* Reset bit inside the Reset management register for EL3 (RMR_EL3) */ 793 #define RMR_RESET_REQUEST_SHIFT U(0x1) 794 #define RMR_WARM_RESET_CPU (U(1) << RMR_RESET_REQUEST_SHIFT) 795 796 /******************************************************************************* 797 * Definitions of register offsets, fields and macros for CPU system 798 * instructions. 799 ******************************************************************************/ 800 801 #define TLBI_ADDR_SHIFT U(12) 802 #define TLBI_ADDR_MASK ULL(0x00000FFFFFFFFFFF) 803 #define TLBI_ADDR(x) (((x) >> TLBI_ADDR_SHIFT) & TLBI_ADDR_MASK) 804 805 /******************************************************************************* 806 * Definitions of register offsets and fields in the CNTCTLBase Frame of the 807 * system level implementation of the Generic Timer. 808 ******************************************************************************/ 809 #define CNTCTLBASE_CNTFRQ U(0x0) 810 #define CNTNSAR U(0x4) 811 #define CNTNSAR_NS_SHIFT(x) (x) 812 813 #define CNTACR_BASE(x) (U(0x40) + ((x) << 2)) 814 #define CNTACR_RPCT_SHIFT U(0x0) 815 #define CNTACR_RVCT_SHIFT U(0x1) 816 #define CNTACR_RFRQ_SHIFT U(0x2) 817 #define CNTACR_RVOFF_SHIFT U(0x3) 818 #define CNTACR_RWVT_SHIFT U(0x4) 819 #define CNTACR_RWPT_SHIFT U(0x5) 820 821 /******************************************************************************* 822 * Definitions of register offsets and fields in the CNTBaseN Frame of the 823 * system level implementation of the Generic Timer. 824 ******************************************************************************/ 825 /* Physical Count register. */ 826 #define CNTPCT_LO U(0x0) 827 /* Counter Frequency register. */ 828 #define CNTBASEN_CNTFRQ U(0x10) 829 /* Physical Timer CompareValue register. */ 830 #define CNTP_CVAL_LO U(0x20) 831 /* Physical Timer Control register. */ 832 #define CNTP_CTL U(0x2c) 833 834 /* PMCR_EL0 definitions */ 835 #define PMCR_EL0_RESET_VAL U(0x0) 836 #define PMCR_EL0_N_SHIFT U(11) 837 #define PMCR_EL0_N_MASK U(0x1f) 838 #define PMCR_EL0_N_BITS (PMCR_EL0_N_MASK << PMCR_EL0_N_SHIFT) 839 #define PMCR_EL0_LP_BIT (U(1) << 7) 840 #define PMCR_EL0_LC_BIT (U(1) << 6) 841 #define PMCR_EL0_DP_BIT (U(1) << 5) 842 #define PMCR_EL0_X_BIT (U(1) << 4) 843 #define PMCR_EL0_D_BIT (U(1) << 3) 844 #define PMCR_EL0_C_BIT (U(1) << 2) 845 #define PMCR_EL0_P_BIT (U(1) << 1) 846 #define PMCR_EL0_E_BIT (U(1) << 0) 847 848 /******************************************************************************* 849 * Definitions for system register interface to SVE 850 ******************************************************************************/ 851 #define ZCR_EL3 S3_6_C1_C2_0 852 #define ZCR_EL2 S3_4_C1_C2_0 853 854 /* ZCR_EL3 definitions */ 855 #define ZCR_EL3_LEN_MASK U(0xf) 856 857 /* ZCR_EL2 definitions */ 858 #define ZCR_EL2_LEN_MASK U(0xf) 859 860 /******************************************************************************* 861 * Definitions of MAIR encodings for device and normal memory 862 ******************************************************************************/ 863 /* 864 * MAIR encodings for device memory attributes. 865 */ 866 #define MAIR_DEV_nGnRnE ULL(0x0) 867 #define MAIR_DEV_nGnRE ULL(0x4) 868 #define MAIR_DEV_nGRE ULL(0x8) 869 #define MAIR_DEV_GRE ULL(0xc) 870 871 /* 872 * MAIR encodings for normal memory attributes. 873 * 874 * Cache Policy 875 * WT: Write Through 876 * WB: Write Back 877 * NC: Non-Cacheable 878 * 879 * Transient Hint 880 * NTR: Non-Transient 881 * TR: Transient 882 * 883 * Allocation Policy 884 * RA: Read Allocate 885 * WA: Write Allocate 886 * RWA: Read and Write Allocate 887 * NA: No Allocation 888 */ 889 #define MAIR_NORM_WT_TR_WA ULL(0x1) 890 #define MAIR_NORM_WT_TR_RA ULL(0x2) 891 #define MAIR_NORM_WT_TR_RWA ULL(0x3) 892 #define MAIR_NORM_NC ULL(0x4) 893 #define MAIR_NORM_WB_TR_WA ULL(0x5) 894 #define MAIR_NORM_WB_TR_RA ULL(0x6) 895 #define MAIR_NORM_WB_TR_RWA ULL(0x7) 896 #define MAIR_NORM_WT_NTR_NA ULL(0x8) 897 #define MAIR_NORM_WT_NTR_WA ULL(0x9) 898 #define MAIR_NORM_WT_NTR_RA ULL(0xa) 899 #define MAIR_NORM_WT_NTR_RWA ULL(0xb) 900 #define MAIR_NORM_WB_NTR_NA ULL(0xc) 901 #define MAIR_NORM_WB_NTR_WA ULL(0xd) 902 #define MAIR_NORM_WB_NTR_RA ULL(0xe) 903 #define MAIR_NORM_WB_NTR_RWA ULL(0xf) 904 905 #define MAIR_NORM_OUTER_SHIFT U(4) 906 907 #define MAKE_MAIR_NORMAL_MEMORY(inner, outer) \ 908 ((inner) | ((outer) << MAIR_NORM_OUTER_SHIFT)) 909 910 /* PAR_EL1 fields */ 911 #define PAR_F_SHIFT U(0) 912 #define PAR_F_MASK ULL(0x1) 913 #define PAR_ADDR_SHIFT U(12) 914 #define PAR_ADDR_MASK (BIT(40) - ULL(1)) /* 40-bits-wide page address */ 915 916 /******************************************************************************* 917 * Definitions for system register interface to SPE 918 ******************************************************************************/ 919 #define PMBLIMITR_EL1 S3_0_C9_C10_0 920 921 /******************************************************************************* 922 * Definitions for system register interface to MPAM 923 ******************************************************************************/ 924 #define MPAMIDR_EL1 S3_0_C10_C4_4 925 #define MPAM2_EL2 S3_4_C10_C5_0 926 #define MPAMHCR_EL2 S3_4_C10_C4_0 927 #define MPAM3_EL3 S3_6_C10_C5_0 928 929 /******************************************************************************* 930 * Definitions for system register interface to AMU for FEAT_AMUv1 931 ******************************************************************************/ 932 #define AMCR_EL0 S3_3_C13_C2_0 933 #define AMCFGR_EL0 S3_3_C13_C2_1 934 #define AMCGCR_EL0 S3_3_C13_C2_2 935 #define AMUSERENR_EL0 S3_3_C13_C2_3 936 #define AMCNTENCLR0_EL0 S3_3_C13_C2_4 937 #define AMCNTENSET0_EL0 S3_3_C13_C2_5 938 #define AMCNTENCLR1_EL0 S3_3_C13_C3_0 939 #define AMCNTENSET1_EL0 S3_3_C13_C3_1 940 941 /* Activity Monitor Group 0 Event Counter Registers */ 942 #define AMEVCNTR00_EL0 S3_3_C13_C4_0 943 #define AMEVCNTR01_EL0 S3_3_C13_C4_1 944 #define AMEVCNTR02_EL0 S3_3_C13_C4_2 945 #define AMEVCNTR03_EL0 S3_3_C13_C4_3 946 947 /* Activity Monitor Group 0 Event Type Registers */ 948 #define AMEVTYPER00_EL0 S3_3_C13_C6_0 949 #define AMEVTYPER01_EL0 S3_3_C13_C6_1 950 #define AMEVTYPER02_EL0 S3_3_C13_C6_2 951 #define AMEVTYPER03_EL0 S3_3_C13_C6_3 952 953 /* Activity Monitor Group 1 Event Counter Registers */ 954 #define AMEVCNTR10_EL0 S3_3_C13_C12_0 955 #define AMEVCNTR11_EL0 S3_3_C13_C12_1 956 #define AMEVCNTR12_EL0 S3_3_C13_C12_2 957 #define AMEVCNTR13_EL0 S3_3_C13_C12_3 958 #define AMEVCNTR14_EL0 S3_3_C13_C12_4 959 #define AMEVCNTR15_EL0 S3_3_C13_C12_5 960 #define AMEVCNTR16_EL0 S3_3_C13_C12_6 961 #define AMEVCNTR17_EL0 S3_3_C13_C12_7 962 #define AMEVCNTR18_EL0 S3_3_C13_C13_0 963 #define AMEVCNTR19_EL0 S3_3_C13_C13_1 964 #define AMEVCNTR1A_EL0 S3_3_C13_C13_2 965 #define AMEVCNTR1B_EL0 S3_3_C13_C13_3 966 #define AMEVCNTR1C_EL0 S3_3_C13_C13_4 967 #define AMEVCNTR1D_EL0 S3_3_C13_C13_5 968 #define AMEVCNTR1E_EL0 S3_3_C13_C13_6 969 #define AMEVCNTR1F_EL0 S3_3_C13_C13_7 970 971 /* Activity Monitor Group 1 Event Type Registers */ 972 #define AMEVTYPER10_EL0 S3_3_C13_C14_0 973 #define AMEVTYPER11_EL0 S3_3_C13_C14_1 974 #define AMEVTYPER12_EL0 S3_3_C13_C14_2 975 #define AMEVTYPER13_EL0 S3_3_C13_C14_3 976 #define AMEVTYPER14_EL0 S3_3_C13_C14_4 977 #define AMEVTYPER15_EL0 S3_3_C13_C14_5 978 #define AMEVTYPER16_EL0 S3_3_C13_C14_6 979 #define AMEVTYPER17_EL0 S3_3_C13_C14_7 980 #define AMEVTYPER18_EL0 S3_3_C13_C15_0 981 #define AMEVTYPER19_EL0 S3_3_C13_C15_1 982 #define AMEVTYPER1A_EL0 S3_3_C13_C15_2 983 #define AMEVTYPER1B_EL0 S3_3_C13_C15_3 984 #define AMEVTYPER1C_EL0 S3_3_C13_C15_4 985 #define AMEVTYPER1D_EL0 S3_3_C13_C15_5 986 #define AMEVTYPER1E_EL0 S3_3_C13_C15_6 987 #define AMEVTYPER1F_EL0 S3_3_C13_C15_7 988 989 /* AMCFGR_EL0 definitions */ 990 #define AMCFGR_EL0_NCG_SHIFT U(28) 991 #define AMCFGR_EL0_NCG_MASK U(0xf) 992 #define AMCFGR_EL0_N_SHIFT U(0) 993 #define AMCFGR_EL0_N_MASK U(0xff) 994 995 /* AMCGCR_EL0 definitions */ 996 #define AMCGCR_EL0_CG1NC_SHIFT U(8) 997 #define AMCGCR_EL0_CG1NC_MASK U(0xff) 998 999 /* MPAM register definitions */ 1000 #define MPAM3_EL3_MPAMEN_BIT (ULL(1) << 63) 1001 #define MPAMHCR_EL2_TRAP_MPAMIDR_EL1 (ULL(1) << 31) 1002 1003 #define MPAM2_EL2_TRAPMPAM0EL1 (ULL(1) << 49) 1004 #define MPAM2_EL2_TRAPMPAM1EL1 (ULL(1) << 48) 1005 1006 #define MPAMIDR_HAS_HCR_BIT (ULL(1) << 17) 1007 1008 /******************************************************************************* 1009 * Definitions for system register interface to AMU for FEAT_AMUv1p1 1010 ******************************************************************************/ 1011 1012 /* Definition for register defining which virtual offsets are implemented. */ 1013 #define AMCG1IDR_EL0 S3_3_C13_C2_6 1014 #define AMCG1IDR_CTR_MASK ULL(0xffff) 1015 #define AMCG1IDR_CTR_SHIFT U(0) 1016 #define AMCG1IDR_VOFF_MASK ULL(0xffff) 1017 #define AMCG1IDR_VOFF_SHIFT U(16) 1018 1019 /* New bit added to AMCR_EL0 */ 1020 #define AMCR_CG1RZ_BIT (ULL(0x1) << 17) 1021 1022 /* 1023 * Definitions for virtual offset registers for architected activity monitor 1024 * event counters. 1025 * AMEVCNTVOFF01_EL2 intentionally left undefined, as it does not exist. 1026 */ 1027 #define AMEVCNTVOFF00_EL2 S3_4_C13_C8_0 1028 #define AMEVCNTVOFF02_EL2 S3_4_C13_C8_2 1029 #define AMEVCNTVOFF03_EL2 S3_4_C13_C8_3 1030 1031 /* 1032 * Definitions for virtual offset registers for auxiliary activity monitor event 1033 * counters. 1034 */ 1035 #define AMEVCNTVOFF10_EL2 S3_4_C13_C10_0 1036 #define AMEVCNTVOFF11_EL2 S3_4_C13_C10_1 1037 #define AMEVCNTVOFF12_EL2 S3_4_C13_C10_2 1038 #define AMEVCNTVOFF13_EL2 S3_4_C13_C10_3 1039 #define AMEVCNTVOFF14_EL2 S3_4_C13_C10_4 1040 #define AMEVCNTVOFF15_EL2 S3_4_C13_C10_5 1041 #define AMEVCNTVOFF16_EL2 S3_4_C13_C10_6 1042 #define AMEVCNTVOFF17_EL2 S3_4_C13_C10_7 1043 #define AMEVCNTVOFF18_EL2 S3_4_C13_C11_0 1044 #define AMEVCNTVOFF19_EL2 S3_4_C13_C11_1 1045 #define AMEVCNTVOFF1A_EL2 S3_4_C13_C11_2 1046 #define AMEVCNTVOFF1B_EL2 S3_4_C13_C11_3 1047 #define AMEVCNTVOFF1C_EL2 S3_4_C13_C11_4 1048 #define AMEVCNTVOFF1D_EL2 S3_4_C13_C11_5 1049 #define AMEVCNTVOFF1E_EL2 S3_4_C13_C11_6 1050 #define AMEVCNTVOFF1F_EL2 S3_4_C13_C11_7 1051 1052 /******************************************************************************* 1053 * RAS system registers 1054 ******************************************************************************/ 1055 #define DISR_EL1 S3_0_C12_C1_1 1056 #define DISR_A_BIT U(31) 1057 1058 #define ERRIDR_EL1 S3_0_C5_C3_0 1059 #define ERRIDR_MASK U(0xffff) 1060 1061 #define ERRSELR_EL1 S3_0_C5_C3_1 1062 1063 /* System register access to Standard Error Record registers */ 1064 #define ERXFR_EL1 S3_0_C5_C4_0 1065 #define ERXCTLR_EL1 S3_0_C5_C4_1 1066 #define ERXSTATUS_EL1 S3_0_C5_C4_2 1067 #define ERXADDR_EL1 S3_0_C5_C4_3 1068 #define ERXPFGF_EL1 S3_0_C5_C4_4 1069 #define ERXPFGCTL_EL1 S3_0_C5_C4_5 1070 #define ERXPFGCDN_EL1 S3_0_C5_C4_6 1071 #define ERXMISC0_EL1 S3_0_C5_C5_0 1072 #define ERXMISC1_EL1 S3_0_C5_C5_1 1073 1074 #define ERXCTLR_ED_BIT (U(1) << 0) 1075 #define ERXCTLR_UE_BIT (U(1) << 4) 1076 1077 #define ERXPFGCTL_UC_BIT (U(1) << 1) 1078 #define ERXPFGCTL_UEU_BIT (U(1) << 2) 1079 #define ERXPFGCTL_CDEN_BIT (U(1) << 31) 1080 1081 /******************************************************************************* 1082 * Armv8.3 Pointer Authentication Registers 1083 ******************************************************************************/ 1084 #define APIAKeyLo_EL1 S3_0_C2_C1_0 1085 #define APIAKeyHi_EL1 S3_0_C2_C1_1 1086 #define APIBKeyLo_EL1 S3_0_C2_C1_2 1087 #define APIBKeyHi_EL1 S3_0_C2_C1_3 1088 #define APDAKeyLo_EL1 S3_0_C2_C2_0 1089 #define APDAKeyHi_EL1 S3_0_C2_C2_1 1090 #define APDBKeyLo_EL1 S3_0_C2_C2_2 1091 #define APDBKeyHi_EL1 S3_0_C2_C2_3 1092 #define APGAKeyLo_EL1 S3_0_C2_C3_0 1093 #define APGAKeyHi_EL1 S3_0_C2_C3_1 1094 1095 /******************************************************************************* 1096 * Armv8.4 Data Independent Timing Registers 1097 ******************************************************************************/ 1098 #define DIT S3_3_C4_C2_5 1099 #define DIT_BIT BIT(24) 1100 1101 /******************************************************************************* 1102 * Armv8.5 - new MSR encoding to directly access PSTATE.SSBS field 1103 ******************************************************************************/ 1104 #define SSBS S3_3_C4_C2_6 1105 1106 /******************************************************************************* 1107 * Armv8.5 - Memory Tagging Extension Registers 1108 ******************************************************************************/ 1109 #define TFSRE0_EL1 S3_0_C5_C6_1 1110 #define TFSR_EL1 S3_0_C5_C6_0 1111 #define RGSR_EL1 S3_0_C1_C0_5 1112 #define GCR_EL1 S3_0_C1_C0_6 1113 1114 /******************************************************************************* 1115 * Definitions for DynamicIQ Shared Unit registers 1116 ******************************************************************************/ 1117 #define CLUSTERPWRDN_EL1 S3_0_c15_c3_6 1118 1119 /* CLUSTERPWRDN_EL1 register definitions */ 1120 #define DSU_CLUSTER_PWR_OFF 0 1121 #define DSU_CLUSTER_PWR_ON 1 1122 #define DSU_CLUSTER_PWR_MASK U(1) 1123 1124 #endif /* ARCH_H */ 1125