1 /* 2 * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef ARCH_H 9 #define ARCH_H 10 11 #include <lib/utils_def.h> 12 13 /******************************************************************************* 14 * MIDR bit definitions 15 ******************************************************************************/ 16 #define MIDR_IMPL_MASK U(0xff) 17 #define MIDR_IMPL_SHIFT U(0x18) 18 #define MIDR_VAR_SHIFT U(20) 19 #define MIDR_VAR_BITS U(4) 20 #define MIDR_VAR_MASK U(0xf) 21 #define MIDR_REV_SHIFT U(0) 22 #define MIDR_REV_BITS U(4) 23 #define MIDR_REV_MASK U(0xf) 24 #define MIDR_PN_MASK U(0xfff) 25 #define MIDR_PN_SHIFT U(0x4) 26 27 /******************************************************************************* 28 * MPIDR macros 29 ******************************************************************************/ 30 #define MPIDR_MT_MASK (ULL(1) << 24) 31 #define MPIDR_CPU_MASK MPIDR_AFFLVL_MASK 32 #define MPIDR_CLUSTER_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS) 33 #define MPIDR_AFFINITY_BITS U(8) 34 #define MPIDR_AFFLVL_MASK ULL(0xff) 35 #define MPIDR_AFF0_SHIFT U(0) 36 #define MPIDR_AFF1_SHIFT U(8) 37 #define MPIDR_AFF2_SHIFT U(16) 38 #define MPIDR_AFF3_SHIFT U(32) 39 #define MPIDR_AFF_SHIFT(_n) MPIDR_AFF##_n##_SHIFT 40 #define MPIDR_AFFINITY_MASK ULL(0xff00ffffff) 41 #define MPIDR_AFFLVL_SHIFT U(3) 42 #define MPIDR_AFFLVL0 ULL(0x0) 43 #define MPIDR_AFFLVL1 ULL(0x1) 44 #define MPIDR_AFFLVL2 ULL(0x2) 45 #define MPIDR_AFFLVL3 ULL(0x3) 46 #define MPIDR_AFFLVL(_n) MPIDR_AFFLVL##_n 47 #define MPIDR_AFFLVL0_VAL(mpidr) \ 48 (((mpidr) >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK) 49 #define MPIDR_AFFLVL1_VAL(mpidr) \ 50 (((mpidr) >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK) 51 #define MPIDR_AFFLVL2_VAL(mpidr) \ 52 (((mpidr) >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK) 53 #define MPIDR_AFFLVL3_VAL(mpidr) \ 54 (((mpidr) >> MPIDR_AFF3_SHIFT) & MPIDR_AFFLVL_MASK) 55 /* 56 * The MPIDR_MAX_AFFLVL count starts from 0. Take care to 57 * add one while using this macro to define array sizes. 58 * TODO: Support only the first 3 affinity levels for now. 59 */ 60 #define MPIDR_MAX_AFFLVL U(2) 61 62 #define MPID_MASK (MPIDR_MT_MASK | \ 63 (MPIDR_AFFLVL_MASK << MPIDR_AFF3_SHIFT) | \ 64 (MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT) | \ 65 (MPIDR_AFFLVL_MASK << MPIDR_AFF1_SHIFT) | \ 66 (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT)) 67 68 #define MPIDR_AFF_ID(mpid, n) \ 69 (((mpid) >> MPIDR_AFF_SHIFT(n)) & MPIDR_AFFLVL_MASK) 70 71 /* 72 * An invalid MPID. This value can be used by functions that return an MPID to 73 * indicate an error. 74 */ 75 #define INVALID_MPID U(0xFFFFFFFF) 76 77 /******************************************************************************* 78 * Definitions for CPU system register interface to GICv3 79 ******************************************************************************/ 80 #define ICC_IGRPEN1_EL1 S3_0_C12_C12_7 81 #define ICC_SGI1R S3_0_C12_C11_5 82 #define ICC_SRE_EL1 S3_0_C12_C12_5 83 #define ICC_SRE_EL2 S3_4_C12_C9_5 84 #define ICC_SRE_EL3 S3_6_C12_C12_5 85 #define ICC_CTLR_EL1 S3_0_C12_C12_4 86 #define ICC_CTLR_EL3 S3_6_C12_C12_4 87 #define ICC_PMR_EL1 S3_0_C4_C6_0 88 #define ICC_RPR_EL1 S3_0_C12_C11_3 89 #define ICC_IGRPEN1_EL3 S3_6_c12_c12_7 90 #define ICC_IGRPEN0_EL1 S3_0_c12_c12_6 91 #define ICC_HPPIR0_EL1 S3_0_c12_c8_2 92 #define ICC_HPPIR1_EL1 S3_0_c12_c12_2 93 #define ICC_IAR0_EL1 S3_0_c12_c8_0 94 #define ICC_IAR1_EL1 S3_0_c12_c12_0 95 #define ICC_EOIR0_EL1 S3_0_c12_c8_1 96 #define ICC_EOIR1_EL1 S3_0_c12_c12_1 97 #define ICC_SGI0R_EL1 S3_0_c12_c11_7 98 99 /******************************************************************************* 100 * Generic timer memory mapped registers & offsets 101 ******************************************************************************/ 102 #define CNTCR_OFF U(0x000) 103 #define CNTCV_OFF U(0x008) 104 #define CNTFID_OFF U(0x020) 105 106 #define CNTCR_EN (U(1) << 0) 107 #define CNTCR_HDBG (U(1) << 1) 108 #define CNTCR_FCREQ(x) ((x) << 8) 109 110 /******************************************************************************* 111 * System register bit definitions 112 ******************************************************************************/ 113 /* CLIDR definitions */ 114 #define LOUIS_SHIFT U(21) 115 #define LOC_SHIFT U(24) 116 #define CTYPE_SHIFT(n) U(3 * (n - 1)) 117 #define CLIDR_FIELD_WIDTH U(3) 118 119 /* CSSELR definitions */ 120 #define LEVEL_SHIFT U(1) 121 122 /* Data cache set/way op type defines */ 123 #define DCISW U(0x0) 124 #define DCCISW U(0x1) 125 #if ERRATA_A53_827319 126 #define DCCSW DCCISW 127 #else 128 #define DCCSW U(0x2) 129 #endif 130 131 /* ID_AA64PFR0_EL1 definitions */ 132 #define ID_AA64PFR0_EL0_SHIFT U(0) 133 #define ID_AA64PFR0_EL1_SHIFT U(4) 134 #define ID_AA64PFR0_EL2_SHIFT U(8) 135 #define ID_AA64PFR0_EL3_SHIFT U(12) 136 #define ID_AA64PFR0_AMU_SHIFT U(44) 137 #define ID_AA64PFR0_AMU_MASK ULL(0xf) 138 #define ID_AA64PFR0_ELX_MASK ULL(0xf) 139 #define ID_AA64PFR0_GIC_SHIFT U(24) 140 #define ID_AA64PFR0_GIC_WIDTH U(4) 141 #define ID_AA64PFR0_GIC_MASK ULL(0xf) 142 #define ID_AA64PFR0_SVE_SHIFT U(32) 143 #define ID_AA64PFR0_SVE_MASK ULL(0xf) 144 #define ID_AA64PFR0_SEL2_SHIFT U(36) 145 #define ID_AA64PFR0_SEL2_MASK ULL(0xf) 146 #define ID_AA64PFR0_MPAM_SHIFT U(40) 147 #define ID_AA64PFR0_MPAM_MASK ULL(0xf) 148 #define ID_AA64PFR0_DIT_SHIFT U(48) 149 #define ID_AA64PFR0_DIT_MASK ULL(0xf) 150 #define ID_AA64PFR0_DIT_LENGTH U(4) 151 #define ID_AA64PFR0_DIT_SUPPORTED U(1) 152 #define ID_AA64PFR0_CSV2_SHIFT U(56) 153 #define ID_AA64PFR0_CSV2_MASK ULL(0xf) 154 #define ID_AA64PFR0_CSV2_LENGTH U(4) 155 156 /* Exception level handling */ 157 #define EL_IMPL_NONE ULL(0) 158 #define EL_IMPL_A64ONLY ULL(1) 159 #define EL_IMPL_A64_A32 ULL(2) 160 161 /* ID_AA64DFR0_EL1.PMS definitions (for ARMv8.2+) */ 162 #define ID_AA64DFR0_PMS_SHIFT U(32) 163 #define ID_AA64DFR0_PMS_MASK ULL(0xf) 164 165 /* ID_AA64ISAR1_EL1 definitions */ 166 #define ID_AA64ISAR1_EL1 S3_0_C0_C6_1 167 #define ID_AA64ISAR1_GPI_SHIFT U(28) 168 #define ID_AA64ISAR1_GPI_MASK ULL(0xf) 169 #define ID_AA64ISAR1_GPA_SHIFT U(24) 170 #define ID_AA64ISAR1_GPA_MASK ULL(0xf) 171 #define ID_AA64ISAR1_API_SHIFT U(8) 172 #define ID_AA64ISAR1_API_MASK ULL(0xf) 173 #define ID_AA64ISAR1_APA_SHIFT U(4) 174 #define ID_AA64ISAR1_APA_MASK ULL(0xf) 175 176 /* ID_AA64MMFR0_EL1 definitions */ 177 #define ID_AA64MMFR0_EL1_PARANGE_SHIFT U(0) 178 #define ID_AA64MMFR0_EL1_PARANGE_MASK ULL(0xf) 179 180 #define PARANGE_0000 U(32) 181 #define PARANGE_0001 U(36) 182 #define PARANGE_0010 U(40) 183 #define PARANGE_0011 U(42) 184 #define PARANGE_0100 U(44) 185 #define PARANGE_0101 U(48) 186 #define PARANGE_0110 U(52) 187 188 #define ID_AA64MMFR0_EL1_TGRAN4_SHIFT U(28) 189 #define ID_AA64MMFR0_EL1_TGRAN4_MASK ULL(0xf) 190 #define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED ULL(0x0) 191 #define ID_AA64MMFR0_EL1_TGRAN4_NOT_SUPPORTED ULL(0xf) 192 193 #define ID_AA64MMFR0_EL1_TGRAN64_SHIFT U(24) 194 #define ID_AA64MMFR0_EL1_TGRAN64_MASK ULL(0xf) 195 #define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED ULL(0x0) 196 #define ID_AA64MMFR0_EL1_TGRAN64_NOT_SUPPORTED ULL(0xf) 197 198 #define ID_AA64MMFR0_EL1_TGRAN16_SHIFT U(20) 199 #define ID_AA64MMFR0_EL1_TGRAN16_MASK ULL(0xf) 200 #define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED ULL(0x1) 201 #define ID_AA64MMFR0_EL1_TGRAN16_NOT_SUPPORTED ULL(0x0) 202 203 /* ID_AA64MMFR2_EL1 definitions */ 204 #define ID_AA64MMFR2_EL1 S3_0_C0_C7_2 205 206 #define ID_AA64MMFR2_EL1_ST_SHIFT U(28) 207 #define ID_AA64MMFR2_EL1_ST_MASK ULL(0xf) 208 209 #define ID_AA64MMFR2_EL1_CNP_SHIFT U(0) 210 #define ID_AA64MMFR2_EL1_CNP_MASK ULL(0xf) 211 212 /* ID_AA64PFR1_EL1 definitions */ 213 #define ID_AA64PFR1_EL1_SSBS_SHIFT U(4) 214 #define ID_AA64PFR1_EL1_SSBS_MASK ULL(0xf) 215 216 #define SSBS_UNAVAILABLE ULL(0) /* No architectural SSBS support */ 217 218 #define ID_AA64PFR1_EL1_BT_SHIFT U(0) 219 #define ID_AA64PFR1_EL1_BT_MASK ULL(0xf) 220 221 #define BTI_IMPLEMENTED ULL(1) /* The BTI mechanism is implemented */ 222 223 #define ID_AA64PFR1_EL1_MTE_SHIFT U(8) 224 #define ID_AA64PFR1_EL1_MTE_MASK ULL(0xf) 225 226 #define MTE_UNIMPLEMENTED ULL(0) 227 #define MTE_IMPLEMENTED_EL0 ULL(1) /* MTE is only implemented at EL0 */ 228 #define MTE_IMPLEMENTED_ELX ULL(2) /* MTE is implemented at all ELs */ 229 230 /* ID_PFR1_EL1 definitions */ 231 #define ID_PFR1_VIRTEXT_SHIFT U(12) 232 #define ID_PFR1_VIRTEXT_MASK U(0xf) 233 #define GET_VIRT_EXT(id) (((id) >> ID_PFR1_VIRTEXT_SHIFT) \ 234 & ID_PFR1_VIRTEXT_MASK) 235 236 /* SCTLR definitions */ 237 #define SCTLR_EL2_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ 238 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \ 239 (U(1) << 11) | (U(1) << 5) | (U(1) << 4)) 240 241 #define SCTLR_EL1_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ 242 (U(1) << 22) | (U(1) << 20) | (U(1) << 11)) 243 #define SCTLR_AARCH32_EL1_RES1 \ 244 ((U(1) << 23) | (U(1) << 22) | (U(1) << 11) | \ 245 (U(1) << 4) | (U(1) << 3)) 246 247 #define SCTLR_EL3_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ 248 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \ 249 (U(1) << 11) | (U(1) << 5) | (U(1) << 4)) 250 251 #define SCTLR_M_BIT (ULL(1) << 0) 252 #define SCTLR_A_BIT (ULL(1) << 1) 253 #define SCTLR_C_BIT (ULL(1) << 2) 254 #define SCTLR_SA_BIT (ULL(1) << 3) 255 #define SCTLR_SA0_BIT (ULL(1) << 4) 256 #define SCTLR_CP15BEN_BIT (ULL(1) << 5) 257 #define SCTLR_ITD_BIT (ULL(1) << 7) 258 #define SCTLR_SED_BIT (ULL(1) << 8) 259 #define SCTLR_UMA_BIT (ULL(1) << 9) 260 #define SCTLR_I_BIT (ULL(1) << 12) 261 #define SCTLR_EnDB_BIT (ULL(1) << 13) 262 #define SCTLR_DZE_BIT (ULL(1) << 14) 263 #define SCTLR_UCT_BIT (ULL(1) << 15) 264 #define SCTLR_NTWI_BIT (ULL(1) << 16) 265 #define SCTLR_NTWE_BIT (ULL(1) << 18) 266 #define SCTLR_WXN_BIT (ULL(1) << 19) 267 #define SCTLR_UWXN_BIT (ULL(1) << 20) 268 #define SCTLR_IESB_BIT (ULL(1) << 21) 269 #define SCTLR_E0E_BIT (ULL(1) << 24) 270 #define SCTLR_EE_BIT (ULL(1) << 25) 271 #define SCTLR_UCI_BIT (ULL(1) << 26) 272 #define SCTLR_EnDA_BIT (ULL(1) << 27) 273 #define SCTLR_EnIB_BIT (ULL(1) << 30) 274 #define SCTLR_EnIA_BIT (ULL(1) << 31) 275 #define SCTLR_BT0_BIT (ULL(1) << 35) 276 #define SCTLR_BT1_BIT (ULL(1) << 36) 277 #define SCTLR_BT_BIT (ULL(1) << 36) 278 #define SCTLR_DSSBS_BIT (ULL(1) << 44) 279 #define SCTLR_RESET_VAL SCTLR_EL3_RES1 280 281 /* CPACR_El1 definitions */ 282 #define CPACR_EL1_FPEN(x) ((x) << 20) 283 #define CPACR_EL1_FP_TRAP_EL0 U(0x1) 284 #define CPACR_EL1_FP_TRAP_ALL U(0x2) 285 #define CPACR_EL1_FP_TRAP_NONE U(0x3) 286 287 /* SCR definitions */ 288 #define SCR_RES1_BITS ((U(1) << 4) | (U(1) << 5)) 289 #define SCR_ATA_BIT (U(1) << 26) 290 #define SCR_FIEN_BIT (U(1) << 21) 291 #define SCR_EEL2_BIT (U(1) << 18) 292 #define SCR_API_BIT (U(1) << 17) 293 #define SCR_APK_BIT (U(1) << 16) 294 #define SCR_TWE_BIT (U(1) << 13) 295 #define SCR_TWI_BIT (U(1) << 12) 296 #define SCR_ST_BIT (U(1) << 11) 297 #define SCR_RW_BIT (U(1) << 10) 298 #define SCR_SIF_BIT (U(1) << 9) 299 #define SCR_HCE_BIT (U(1) << 8) 300 #define SCR_SMD_BIT (U(1) << 7) 301 #define SCR_EA_BIT (U(1) << 3) 302 #define SCR_FIQ_BIT (U(1) << 2) 303 #define SCR_IRQ_BIT (U(1) << 1) 304 #define SCR_NS_BIT (U(1) << 0) 305 #define SCR_VALID_BIT_MASK U(0x2f8f) 306 #define SCR_RESET_VAL SCR_RES1_BITS 307 308 /* MDCR_EL3 definitions */ 309 #define MDCR_SCCD_BIT (ULL(1) << 23) 310 #define MDCR_SPME_BIT (ULL(1) << 17) 311 #define MDCR_SDD_BIT (ULL(1) << 16) 312 #define MDCR_SPD32(x) ((x) << 14) 313 #define MDCR_SPD32_LEGACY ULL(0x0) 314 #define MDCR_SPD32_DISABLE ULL(0x2) 315 #define MDCR_SPD32_ENABLE ULL(0x3) 316 #define MDCR_NSPB(x) ((x) << 12) 317 #define MDCR_NSPB_EL1 ULL(0x3) 318 #define MDCR_TDOSA_BIT (ULL(1) << 10) 319 #define MDCR_TDA_BIT (ULL(1) << 9) 320 #define MDCR_TPM_BIT (ULL(1) << 6) 321 #define MDCR_EL3_RESET_VAL ULL(0x0) 322 323 /* MDCR_EL2 definitions */ 324 #define MDCR_EL2_HLP (U(1) << 26) 325 #define MDCR_EL2_HCCD (U(1) << 23) 326 #define MDCR_EL2_TTRF (U(1) << 19) 327 #define MDCR_EL2_HPMD (U(1) << 17) 328 #define MDCR_EL2_TPMS (U(1) << 14) 329 #define MDCR_EL2_E2PB(x) ((x) << 12) 330 #define MDCR_EL2_E2PB_EL1 U(0x3) 331 #define MDCR_EL2_TDRA_BIT (U(1) << 11) 332 #define MDCR_EL2_TDOSA_BIT (U(1) << 10) 333 #define MDCR_EL2_TDA_BIT (U(1) << 9) 334 #define MDCR_EL2_TDE_BIT (U(1) << 8) 335 #define MDCR_EL2_HPME_BIT (U(1) << 7) 336 #define MDCR_EL2_TPM_BIT (U(1) << 6) 337 #define MDCR_EL2_TPMCR_BIT (U(1) << 5) 338 #define MDCR_EL2_RESET_VAL U(0x0) 339 340 /* HSTR_EL2 definitions */ 341 #define HSTR_EL2_RESET_VAL U(0x0) 342 #define HSTR_EL2_T_MASK U(0xff) 343 344 /* CNTHP_CTL_EL2 definitions */ 345 #define CNTHP_CTL_ENABLE_BIT (U(1) << 0) 346 #define CNTHP_CTL_RESET_VAL U(0x0) 347 348 /* VTTBR_EL2 definitions */ 349 #define VTTBR_RESET_VAL ULL(0x0) 350 #define VTTBR_VMID_MASK ULL(0xff) 351 #define VTTBR_VMID_SHIFT U(48) 352 #define VTTBR_BADDR_MASK ULL(0xffffffffffff) 353 #define VTTBR_BADDR_SHIFT U(0) 354 355 /* HCR definitions */ 356 #define HCR_API_BIT (ULL(1) << 41) 357 #define HCR_APK_BIT (ULL(1) << 40) 358 #define HCR_TGE_BIT (ULL(1) << 27) 359 #define HCR_RW_SHIFT U(31) 360 #define HCR_RW_BIT (ULL(1) << HCR_RW_SHIFT) 361 #define HCR_AMO_BIT (ULL(1) << 5) 362 #define HCR_IMO_BIT (ULL(1) << 4) 363 #define HCR_FMO_BIT (ULL(1) << 3) 364 365 /* ISR definitions */ 366 #define ISR_A_SHIFT U(8) 367 #define ISR_I_SHIFT U(7) 368 #define ISR_F_SHIFT U(6) 369 370 /* CNTHCTL_EL2 definitions */ 371 #define CNTHCTL_RESET_VAL U(0x0) 372 #define EVNTEN_BIT (U(1) << 2) 373 #define EL1PCEN_BIT (U(1) << 1) 374 #define EL1PCTEN_BIT (U(1) << 0) 375 376 /* CNTKCTL_EL1 definitions */ 377 #define EL0PTEN_BIT (U(1) << 9) 378 #define EL0VTEN_BIT (U(1) << 8) 379 #define EL0PCTEN_BIT (U(1) << 0) 380 #define EL0VCTEN_BIT (U(1) << 1) 381 #define EVNTEN_BIT (U(1) << 2) 382 #define EVNTDIR_BIT (U(1) << 3) 383 #define EVNTI_SHIFT U(4) 384 #define EVNTI_MASK U(0xf) 385 386 /* CPTR_EL3 definitions */ 387 #define TCPAC_BIT (U(1) << 31) 388 #define TAM_BIT (U(1) << 30) 389 #define TTA_BIT (U(1) << 20) 390 #define TFP_BIT (U(1) << 10) 391 #define CPTR_EZ_BIT (U(1) << 8) 392 #define CPTR_EL3_RESET_VAL U(0x0) 393 394 /* CPTR_EL2 definitions */ 395 #define CPTR_EL2_RES1 ((U(1) << 13) | (U(1) << 12) | (U(0x3ff))) 396 #define CPTR_EL2_TCPAC_BIT (U(1) << 31) 397 #define CPTR_EL2_TAM_BIT (U(1) << 30) 398 #define CPTR_EL2_TTA_BIT (U(1) << 20) 399 #define CPTR_EL2_TFP_BIT (U(1) << 10) 400 #define CPTR_EL2_TZ_BIT (U(1) << 8) 401 #define CPTR_EL2_RESET_VAL CPTR_EL2_RES1 402 403 /* CPSR/SPSR definitions */ 404 #define DAIF_FIQ_BIT (U(1) << 0) 405 #define DAIF_IRQ_BIT (U(1) << 1) 406 #define DAIF_ABT_BIT (U(1) << 2) 407 #define DAIF_DBG_BIT (U(1) << 3) 408 #define SPSR_DAIF_SHIFT U(6) 409 #define SPSR_DAIF_MASK U(0xf) 410 411 #define SPSR_AIF_SHIFT U(6) 412 #define SPSR_AIF_MASK U(0x7) 413 414 #define SPSR_E_SHIFT U(9) 415 #define SPSR_E_MASK U(0x1) 416 #define SPSR_E_LITTLE U(0x0) 417 #define SPSR_E_BIG U(0x1) 418 419 #define SPSR_T_SHIFT U(5) 420 #define SPSR_T_MASK U(0x1) 421 #define SPSR_T_ARM U(0x0) 422 #define SPSR_T_THUMB U(0x1) 423 424 #define SPSR_M_SHIFT U(4) 425 #define SPSR_M_MASK U(0x1) 426 #define SPSR_M_AARCH64 U(0x0) 427 #define SPSR_M_AARCH32 U(0x1) 428 429 #define SPSR_SSBS_BIT_AARCH64 BIT_64(12) 430 #define SPSR_SSBS_BIT_AARCH32 BIT_64(23) 431 432 #define DISABLE_ALL_EXCEPTIONS \ 433 (DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT | DAIF_DBG_BIT) 434 435 #define DISABLE_INTERRUPTS (DAIF_FIQ_BIT | DAIF_IRQ_BIT) 436 437 /* 438 * RMR_EL3 definitions 439 */ 440 #define RMR_EL3_RR_BIT (U(1) << 1) 441 #define RMR_EL3_AA64_BIT (U(1) << 0) 442 443 /* 444 * HI-VECTOR address for AArch32 state 445 */ 446 #define HI_VECTOR_BASE U(0xFFFF0000) 447 448 /* 449 * TCR defintions 450 */ 451 #define TCR_EL3_RES1 ((ULL(1) << 31) | (ULL(1) << 23)) 452 #define TCR_EL2_RES1 ((ULL(1) << 31) | (ULL(1) << 23)) 453 #define TCR_EL1_IPS_SHIFT U(32) 454 #define TCR_EL2_PS_SHIFT U(16) 455 #define TCR_EL3_PS_SHIFT U(16) 456 457 #define TCR_TxSZ_MIN ULL(16) 458 #define TCR_TxSZ_MAX ULL(39) 459 #define TCR_TxSZ_MAX_TTST ULL(48) 460 461 #define TCR_T0SZ_SHIFT U(0) 462 #define TCR_T1SZ_SHIFT U(16) 463 464 /* (internal) physical address size bits in EL3/EL1 */ 465 #define TCR_PS_BITS_4GB ULL(0x0) 466 #define TCR_PS_BITS_64GB ULL(0x1) 467 #define TCR_PS_BITS_1TB ULL(0x2) 468 #define TCR_PS_BITS_4TB ULL(0x3) 469 #define TCR_PS_BITS_16TB ULL(0x4) 470 #define TCR_PS_BITS_256TB ULL(0x5) 471 472 #define ADDR_MASK_48_TO_63 ULL(0xFFFF000000000000) 473 #define ADDR_MASK_44_TO_47 ULL(0x0000F00000000000) 474 #define ADDR_MASK_42_TO_43 ULL(0x00000C0000000000) 475 #define ADDR_MASK_40_TO_41 ULL(0x0000030000000000) 476 #define ADDR_MASK_36_TO_39 ULL(0x000000F000000000) 477 #define ADDR_MASK_32_TO_35 ULL(0x0000000F00000000) 478 479 #define TCR_RGN_INNER_NC (ULL(0x0) << 8) 480 #define TCR_RGN_INNER_WBA (ULL(0x1) << 8) 481 #define TCR_RGN_INNER_WT (ULL(0x2) << 8) 482 #define TCR_RGN_INNER_WBNA (ULL(0x3) << 8) 483 484 #define TCR_RGN_OUTER_NC (ULL(0x0) << 10) 485 #define TCR_RGN_OUTER_WBA (ULL(0x1) << 10) 486 #define TCR_RGN_OUTER_WT (ULL(0x2) << 10) 487 #define TCR_RGN_OUTER_WBNA (ULL(0x3) << 10) 488 489 #define TCR_SH_NON_SHAREABLE (ULL(0x0) << 12) 490 #define TCR_SH_OUTER_SHAREABLE (ULL(0x2) << 12) 491 #define TCR_SH_INNER_SHAREABLE (ULL(0x3) << 12) 492 493 #define TCR_RGN1_INNER_NC (ULL(0x0) << 24) 494 #define TCR_RGN1_INNER_WBA (ULL(0x1) << 24) 495 #define TCR_RGN1_INNER_WT (ULL(0x2) << 24) 496 #define TCR_RGN1_INNER_WBNA (ULL(0x3) << 24) 497 498 #define TCR_RGN1_OUTER_NC (ULL(0x0) << 26) 499 #define TCR_RGN1_OUTER_WBA (ULL(0x1) << 26) 500 #define TCR_RGN1_OUTER_WT (ULL(0x2) << 26) 501 #define TCR_RGN1_OUTER_WBNA (ULL(0x3) << 26) 502 503 #define TCR_SH1_NON_SHAREABLE (ULL(0x0) << 28) 504 #define TCR_SH1_OUTER_SHAREABLE (ULL(0x2) << 28) 505 #define TCR_SH1_INNER_SHAREABLE (ULL(0x3) << 28) 506 507 #define TCR_TG0_SHIFT U(14) 508 #define TCR_TG0_MASK ULL(3) 509 #define TCR_TG0_4K (ULL(0) << TCR_TG0_SHIFT) 510 #define TCR_TG0_64K (ULL(1) << TCR_TG0_SHIFT) 511 #define TCR_TG0_16K (ULL(2) << TCR_TG0_SHIFT) 512 513 #define TCR_TG1_SHIFT U(30) 514 #define TCR_TG1_MASK ULL(3) 515 #define TCR_TG1_16K (ULL(1) << TCR_TG1_SHIFT) 516 #define TCR_TG1_4K (ULL(2) << TCR_TG1_SHIFT) 517 #define TCR_TG1_64K (ULL(3) << TCR_TG1_SHIFT) 518 519 #define TCR_EPD0_BIT (ULL(1) << 7) 520 #define TCR_EPD1_BIT (ULL(1) << 23) 521 522 #define MODE_SP_SHIFT U(0x0) 523 #define MODE_SP_MASK U(0x1) 524 #define MODE_SP_EL0 U(0x0) 525 #define MODE_SP_ELX U(0x1) 526 527 #define MODE_RW_SHIFT U(0x4) 528 #define MODE_RW_MASK U(0x1) 529 #define MODE_RW_64 U(0x0) 530 #define MODE_RW_32 U(0x1) 531 532 #define MODE_EL_SHIFT U(0x2) 533 #define MODE_EL_MASK U(0x3) 534 #define MODE_EL3 U(0x3) 535 #define MODE_EL2 U(0x2) 536 #define MODE_EL1 U(0x1) 537 #define MODE_EL0 U(0x0) 538 539 #define MODE32_SHIFT U(0) 540 #define MODE32_MASK U(0xf) 541 #define MODE32_usr U(0x0) 542 #define MODE32_fiq U(0x1) 543 #define MODE32_irq U(0x2) 544 #define MODE32_svc U(0x3) 545 #define MODE32_mon U(0x6) 546 #define MODE32_abt U(0x7) 547 #define MODE32_hyp U(0xa) 548 #define MODE32_und U(0xb) 549 #define MODE32_sys U(0xf) 550 551 #define GET_RW(mode) (((mode) >> MODE_RW_SHIFT) & MODE_RW_MASK) 552 #define GET_EL(mode) (((mode) >> MODE_EL_SHIFT) & MODE_EL_MASK) 553 #define GET_SP(mode) (((mode) >> MODE_SP_SHIFT) & MODE_SP_MASK) 554 #define GET_M32(mode) (((mode) >> MODE32_SHIFT) & MODE32_MASK) 555 556 #define SPSR_64(el, sp, daif) \ 557 (((MODE_RW_64 << MODE_RW_SHIFT) | \ 558 (((el) & MODE_EL_MASK) << MODE_EL_SHIFT) | \ 559 (((sp) & MODE_SP_MASK) << MODE_SP_SHIFT) | \ 560 (((daif) & SPSR_DAIF_MASK) << SPSR_DAIF_SHIFT)) & \ 561 (~(SPSR_SSBS_BIT_AARCH64))) 562 563 #define SPSR_MODE32(mode, isa, endian, aif) \ 564 (((MODE_RW_32 << MODE_RW_SHIFT) | \ 565 (((mode) & MODE32_MASK) << MODE32_SHIFT) | \ 566 (((isa) & SPSR_T_MASK) << SPSR_T_SHIFT) | \ 567 (((endian) & SPSR_E_MASK) << SPSR_E_SHIFT) | \ 568 (((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT)) & \ 569 (~(SPSR_SSBS_BIT_AARCH32))) 570 571 /* 572 * TTBR Definitions 573 */ 574 #define TTBR_CNP_BIT ULL(0x1) 575 576 /* 577 * CTR_EL0 definitions 578 */ 579 #define CTR_CWG_SHIFT U(24) 580 #define CTR_CWG_MASK U(0xf) 581 #define CTR_ERG_SHIFT U(20) 582 #define CTR_ERG_MASK U(0xf) 583 #define CTR_DMINLINE_SHIFT U(16) 584 #define CTR_DMINLINE_MASK U(0xf) 585 #define CTR_L1IP_SHIFT U(14) 586 #define CTR_L1IP_MASK U(0x3) 587 #define CTR_IMINLINE_SHIFT U(0) 588 #define CTR_IMINLINE_MASK U(0xf) 589 590 #define MAX_CACHE_LINE_SIZE U(0x800) /* 2KB */ 591 592 /* Physical timer control register bit fields shifts and masks */ 593 #define CNTP_CTL_ENABLE_SHIFT U(0) 594 #define CNTP_CTL_IMASK_SHIFT U(1) 595 #define CNTP_CTL_ISTATUS_SHIFT U(2) 596 597 #define CNTP_CTL_ENABLE_MASK U(1) 598 #define CNTP_CTL_IMASK_MASK U(1) 599 #define CNTP_CTL_ISTATUS_MASK U(1) 600 601 /* Physical timer control macros */ 602 #define CNTP_CTL_ENABLE_BIT (U(1) << CNTP_CTL_ENABLE_SHIFT) 603 #define CNTP_CTL_IMASK_BIT (U(1) << CNTP_CTL_IMASK_SHIFT) 604 605 /* Exception Syndrome register bits and bobs */ 606 #define ESR_EC_SHIFT U(26) 607 #define ESR_EC_MASK U(0x3f) 608 #define ESR_EC_LENGTH U(6) 609 #define ESR_ISS_SHIFT U(0) 610 #define ESR_ISS_LENGTH U(25) 611 #define EC_UNKNOWN U(0x0) 612 #define EC_WFE_WFI U(0x1) 613 #define EC_AARCH32_CP15_MRC_MCR U(0x3) 614 #define EC_AARCH32_CP15_MRRC_MCRR U(0x4) 615 #define EC_AARCH32_CP14_MRC_MCR U(0x5) 616 #define EC_AARCH32_CP14_LDC_STC U(0x6) 617 #define EC_FP_SIMD U(0x7) 618 #define EC_AARCH32_CP10_MRC U(0x8) 619 #define EC_AARCH32_CP14_MRRC_MCRR U(0xc) 620 #define EC_ILLEGAL U(0xe) 621 #define EC_AARCH32_SVC U(0x11) 622 #define EC_AARCH32_HVC U(0x12) 623 #define EC_AARCH32_SMC U(0x13) 624 #define EC_AARCH64_SVC U(0x15) 625 #define EC_AARCH64_HVC U(0x16) 626 #define EC_AARCH64_SMC U(0x17) 627 #define EC_AARCH64_SYS U(0x18) 628 #define EC_IABORT_LOWER_EL U(0x20) 629 #define EC_IABORT_CUR_EL U(0x21) 630 #define EC_PC_ALIGN U(0x22) 631 #define EC_DABORT_LOWER_EL U(0x24) 632 #define EC_DABORT_CUR_EL U(0x25) 633 #define EC_SP_ALIGN U(0x26) 634 #define EC_AARCH32_FP U(0x28) 635 #define EC_AARCH64_FP U(0x2c) 636 #define EC_SERROR U(0x2f) 637 #define EC_BRK U(0x3c) 638 639 /* 640 * External Abort bit in Instruction and Data Aborts synchronous exception 641 * syndromes. 642 */ 643 #define ESR_ISS_EABORT_EA_BIT U(9) 644 645 #define EC_BITS(x) (((x) >> ESR_EC_SHIFT) & ESR_EC_MASK) 646 647 /* Reset bit inside the Reset management register for EL3 (RMR_EL3) */ 648 #define RMR_RESET_REQUEST_SHIFT U(0x1) 649 #define RMR_WARM_RESET_CPU (U(1) << RMR_RESET_REQUEST_SHIFT) 650 651 /******************************************************************************* 652 * Definitions of register offsets, fields and macros for CPU system 653 * instructions. 654 ******************************************************************************/ 655 656 #define TLBI_ADDR_SHIFT U(12) 657 #define TLBI_ADDR_MASK ULL(0x00000FFFFFFFFFFF) 658 #define TLBI_ADDR(x) (((x) >> TLBI_ADDR_SHIFT) & TLBI_ADDR_MASK) 659 660 /******************************************************************************* 661 * Definitions of register offsets and fields in the CNTCTLBase Frame of the 662 * system level implementation of the Generic Timer. 663 ******************************************************************************/ 664 #define CNTCTLBASE_CNTFRQ U(0x0) 665 #define CNTNSAR U(0x4) 666 #define CNTNSAR_NS_SHIFT(x) (x) 667 668 #define CNTACR_BASE(x) (U(0x40) + ((x) << 2)) 669 #define CNTACR_RPCT_SHIFT U(0x0) 670 #define CNTACR_RVCT_SHIFT U(0x1) 671 #define CNTACR_RFRQ_SHIFT U(0x2) 672 #define CNTACR_RVOFF_SHIFT U(0x3) 673 #define CNTACR_RWVT_SHIFT U(0x4) 674 #define CNTACR_RWPT_SHIFT U(0x5) 675 676 /******************************************************************************* 677 * Definitions of register offsets and fields in the CNTBaseN Frame of the 678 * system level implementation of the Generic Timer. 679 ******************************************************************************/ 680 /* Physical Count register. */ 681 #define CNTPCT_LO U(0x0) 682 /* Counter Frequency register. */ 683 #define CNTBASEN_CNTFRQ U(0x10) 684 /* Physical Timer CompareValue register. */ 685 #define CNTP_CVAL_LO U(0x20) 686 /* Physical Timer Control register. */ 687 #define CNTP_CTL U(0x2c) 688 689 /* PMCR_EL0 definitions */ 690 #define PMCR_EL0_RESET_VAL U(0x0) 691 #define PMCR_EL0_N_SHIFT U(11) 692 #define PMCR_EL0_N_MASK U(0x1f) 693 #define PMCR_EL0_N_BITS (PMCR_EL0_N_MASK << PMCR_EL0_N_SHIFT) 694 #define PMCR_EL0_LP_BIT (U(1) << 7) 695 #define PMCR_EL0_LC_BIT (U(1) << 6) 696 #define PMCR_EL0_DP_BIT (U(1) << 5) 697 #define PMCR_EL0_X_BIT (U(1) << 4) 698 #define PMCR_EL0_D_BIT (U(1) << 3) 699 #define PMCR_EL0_C_BIT (U(1) << 2) 700 #define PMCR_EL0_P_BIT (U(1) << 1) 701 #define PMCR_EL0_E_BIT (U(1) << 0) 702 703 /******************************************************************************* 704 * Definitions for system register interface to SVE 705 ******************************************************************************/ 706 #define ZCR_EL3 S3_6_C1_C2_0 707 #define ZCR_EL2 S3_4_C1_C2_0 708 709 /* ZCR_EL3 definitions */ 710 #define ZCR_EL3_LEN_MASK U(0xf) 711 712 /* ZCR_EL2 definitions */ 713 #define ZCR_EL2_LEN_MASK U(0xf) 714 715 /******************************************************************************* 716 * Definitions of MAIR encodings for device and normal memory 717 ******************************************************************************/ 718 /* 719 * MAIR encodings for device memory attributes. 720 */ 721 #define MAIR_DEV_nGnRnE ULL(0x0) 722 #define MAIR_DEV_nGnRE ULL(0x4) 723 #define MAIR_DEV_nGRE ULL(0x8) 724 #define MAIR_DEV_GRE ULL(0xc) 725 726 /* 727 * MAIR encodings for normal memory attributes. 728 * 729 * Cache Policy 730 * WT: Write Through 731 * WB: Write Back 732 * NC: Non-Cacheable 733 * 734 * Transient Hint 735 * NTR: Non-Transient 736 * TR: Transient 737 * 738 * Allocation Policy 739 * RA: Read Allocate 740 * WA: Write Allocate 741 * RWA: Read and Write Allocate 742 * NA: No Allocation 743 */ 744 #define MAIR_NORM_WT_TR_WA ULL(0x1) 745 #define MAIR_NORM_WT_TR_RA ULL(0x2) 746 #define MAIR_NORM_WT_TR_RWA ULL(0x3) 747 #define MAIR_NORM_NC ULL(0x4) 748 #define MAIR_NORM_WB_TR_WA ULL(0x5) 749 #define MAIR_NORM_WB_TR_RA ULL(0x6) 750 #define MAIR_NORM_WB_TR_RWA ULL(0x7) 751 #define MAIR_NORM_WT_NTR_NA ULL(0x8) 752 #define MAIR_NORM_WT_NTR_WA ULL(0x9) 753 #define MAIR_NORM_WT_NTR_RA ULL(0xa) 754 #define MAIR_NORM_WT_NTR_RWA ULL(0xb) 755 #define MAIR_NORM_WB_NTR_NA ULL(0xc) 756 #define MAIR_NORM_WB_NTR_WA ULL(0xd) 757 #define MAIR_NORM_WB_NTR_RA ULL(0xe) 758 #define MAIR_NORM_WB_NTR_RWA ULL(0xf) 759 760 #define MAIR_NORM_OUTER_SHIFT U(4) 761 762 #define MAKE_MAIR_NORMAL_MEMORY(inner, outer) \ 763 ((inner) | ((outer) << MAIR_NORM_OUTER_SHIFT)) 764 765 /* PAR_EL1 fields */ 766 #define PAR_F_SHIFT U(0) 767 #define PAR_F_MASK ULL(0x1) 768 #define PAR_ADDR_SHIFT U(12) 769 #define PAR_ADDR_MASK (BIT(40) - ULL(1)) /* 40-bits-wide page address */ 770 771 /******************************************************************************* 772 * Definitions for system register interface to SPE 773 ******************************************************************************/ 774 #define PMBLIMITR_EL1 S3_0_C9_C10_0 775 776 /******************************************************************************* 777 * Definitions for system register interface to MPAM 778 ******************************************************************************/ 779 #define MPAMIDR_EL1 S3_0_C10_C4_4 780 #define MPAM2_EL2 S3_4_C10_C5_0 781 #define MPAMHCR_EL2 S3_4_C10_C4_0 782 #define MPAM3_EL3 S3_6_C10_C5_0 783 784 /******************************************************************************* 785 * Definitions for system register interface to AMU for ARMv8.4 onwards 786 ******************************************************************************/ 787 #define AMCR_EL0 S3_3_C13_C2_0 788 #define AMCFGR_EL0 S3_3_C13_C2_1 789 #define AMCGCR_EL0 S3_3_C13_C2_2 790 #define AMUSERENR_EL0 S3_3_C13_C2_3 791 #define AMCNTENCLR0_EL0 S3_3_C13_C2_4 792 #define AMCNTENSET0_EL0 S3_3_C13_C2_5 793 #define AMCNTENCLR1_EL0 S3_3_C13_C3_0 794 #define AMCNTENSET1_EL0 S3_3_C13_C3_1 795 796 /* Activity Monitor Group 0 Event Counter Registers */ 797 #define AMEVCNTR00_EL0 S3_3_C13_C4_0 798 #define AMEVCNTR01_EL0 S3_3_C13_C4_1 799 #define AMEVCNTR02_EL0 S3_3_C13_C4_2 800 #define AMEVCNTR03_EL0 S3_3_C13_C4_3 801 802 /* Activity Monitor Group 0 Event Type Registers */ 803 #define AMEVTYPER00_EL0 S3_3_C13_C6_0 804 #define AMEVTYPER01_EL0 S3_3_C13_C6_1 805 #define AMEVTYPER02_EL0 S3_3_C13_C6_2 806 #define AMEVTYPER03_EL0 S3_3_C13_C6_3 807 808 /* Activity Monitor Group 1 Event Counter Registers */ 809 #define AMEVCNTR10_EL0 S3_3_C13_C12_0 810 #define AMEVCNTR11_EL0 S3_3_C13_C12_1 811 #define AMEVCNTR12_EL0 S3_3_C13_C12_2 812 #define AMEVCNTR13_EL0 S3_3_C13_C12_3 813 #define AMEVCNTR14_EL0 S3_3_C13_C12_4 814 #define AMEVCNTR15_EL0 S3_3_C13_C12_5 815 #define AMEVCNTR16_EL0 S3_3_C13_C12_6 816 #define AMEVCNTR17_EL0 S3_3_C13_C12_7 817 #define AMEVCNTR18_EL0 S3_3_C13_C13_0 818 #define AMEVCNTR19_EL0 S3_3_C13_C13_1 819 #define AMEVCNTR1A_EL0 S3_3_C13_C13_2 820 #define AMEVCNTR1B_EL0 S3_3_C13_C13_3 821 #define AMEVCNTR1C_EL0 S3_3_C13_C13_4 822 #define AMEVCNTR1D_EL0 S3_3_C13_C13_5 823 #define AMEVCNTR1E_EL0 S3_3_C13_C13_6 824 #define AMEVCNTR1F_EL0 S3_3_C13_C13_7 825 826 /* Activity Monitor Group 1 Event Type Registers */ 827 #define AMEVTYPER10_EL0 S3_3_C13_C14_0 828 #define AMEVTYPER11_EL0 S3_3_C13_C14_1 829 #define AMEVTYPER12_EL0 S3_3_C13_C14_2 830 #define AMEVTYPER13_EL0 S3_3_C13_C14_3 831 #define AMEVTYPER14_EL0 S3_3_C13_C14_4 832 #define AMEVTYPER15_EL0 S3_3_C13_C14_5 833 #define AMEVTYPER16_EL0 S3_3_C13_C14_6 834 #define AMEVTYPER17_EL0 S3_3_C13_C14_7 835 #define AMEVTYPER18_EL0 S3_3_C13_C15_0 836 #define AMEVTYPER19_EL0 S3_3_C13_C15_1 837 #define AMEVTYPER1A_EL0 S3_3_C13_C15_2 838 #define AMEVTYPER1B_EL0 S3_3_C13_C15_3 839 #define AMEVTYPER1C_EL0 S3_3_C13_C15_4 840 #define AMEVTYPER1D_EL0 S3_3_C13_C15_5 841 #define AMEVTYPER1E_EL0 S3_3_C13_C15_6 842 #define AMEVTYPER1F_EL0 S3_3_C13_C15_7 843 844 /* AMCGCR_EL0 definitions */ 845 #define AMCGCR_EL0_CG1NC_SHIFT U(8) 846 #define AMCGCR_EL0_CG1NC_LENGTH U(8) 847 #define AMCGCR_EL0_CG1NC_MASK U(0xff) 848 849 /* MPAM register definitions */ 850 #define MPAM3_EL3_MPAMEN_BIT (ULL(1) << 63) 851 #define MPAMHCR_EL2_TRAP_MPAMIDR_EL1 (ULL(1) << 31) 852 853 #define MPAM2_EL2_TRAPMPAM0EL1 (ULL(1) << 49) 854 #define MPAM2_EL2_TRAPMPAM1EL1 (ULL(1) << 48) 855 856 #define MPAMIDR_HAS_HCR_BIT (ULL(1) << 17) 857 858 /******************************************************************************* 859 * RAS system registers 860 ******************************************************************************/ 861 #define DISR_EL1 S3_0_C12_C1_1 862 #define DISR_A_BIT U(31) 863 864 #define ERRIDR_EL1 S3_0_C5_C3_0 865 #define ERRIDR_MASK U(0xffff) 866 867 #define ERRSELR_EL1 S3_0_C5_C3_1 868 869 /* System register access to Standard Error Record registers */ 870 #define ERXFR_EL1 S3_0_C5_C4_0 871 #define ERXCTLR_EL1 S3_0_C5_C4_1 872 #define ERXSTATUS_EL1 S3_0_C5_C4_2 873 #define ERXADDR_EL1 S3_0_C5_C4_3 874 #define ERXPFGF_EL1 S3_0_C5_C4_4 875 #define ERXPFGCTL_EL1 S3_0_C5_C4_5 876 #define ERXPFGCDN_EL1 S3_0_C5_C4_6 877 #define ERXMISC0_EL1 S3_0_C5_C5_0 878 #define ERXMISC1_EL1 S3_0_C5_C5_1 879 880 #define ERXCTLR_ED_BIT (U(1) << 0) 881 #define ERXCTLR_UE_BIT (U(1) << 4) 882 883 #define ERXPFGCTL_UC_BIT (U(1) << 1) 884 #define ERXPFGCTL_UEU_BIT (U(1) << 2) 885 #define ERXPFGCTL_CDEN_BIT (U(1) << 31) 886 887 /******************************************************************************* 888 * Armv8.3 Pointer Authentication Registers 889 ******************************************************************************/ 890 #define APIAKeyLo_EL1 S3_0_C2_C1_0 891 #define APIAKeyHi_EL1 S3_0_C2_C1_1 892 #define APIBKeyLo_EL1 S3_0_C2_C1_2 893 #define APIBKeyHi_EL1 S3_0_C2_C1_3 894 #define APDAKeyLo_EL1 S3_0_C2_C2_0 895 #define APDAKeyHi_EL1 S3_0_C2_C2_1 896 #define APDBKeyLo_EL1 S3_0_C2_C2_2 897 #define APDBKeyHi_EL1 S3_0_C2_C2_3 898 #define APGAKeyLo_EL1 S3_0_C2_C3_0 899 #define APGAKeyHi_EL1 S3_0_C2_C3_1 900 901 /******************************************************************************* 902 * Armv8.4 Data Independent Timing Registers 903 ******************************************************************************/ 904 #define DIT S3_3_C4_C2_5 905 #define DIT_BIT BIT(24) 906 907 /******************************************************************************* 908 * Armv8.5 - new MSR encoding to directly access PSTATE.SSBS field 909 ******************************************************************************/ 910 #define SSBS S3_3_C4_C2_6 911 912 /******************************************************************************* 913 * Armv8.5 - Memory Tagging Extension Registers 914 ******************************************************************************/ 915 #define TFSRE0_EL1 S3_0_C5_C6_1 916 #define TFSR_EL1 S3_0_C5_C6_0 917 #define RGSR_EL1 S3_0_C1_C0_5 918 #define GCR_EL1 S3_0_C1_C0_6 919 920 #endif /* ARCH_H */ 921