1 /* 2 * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2020-2022, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef ARCH_H 9 #define ARCH_H 10 11 #include <lib/utils_def.h> 12 13 /******************************************************************************* 14 * MIDR bit definitions 15 ******************************************************************************/ 16 #define MIDR_IMPL_MASK U(0xff) 17 #define MIDR_IMPL_SHIFT U(0x18) 18 #define MIDR_VAR_SHIFT U(20) 19 #define MIDR_VAR_BITS U(4) 20 #define MIDR_VAR_MASK U(0xf) 21 #define MIDR_REV_SHIFT U(0) 22 #define MIDR_REV_BITS U(4) 23 #define MIDR_REV_MASK U(0xf) 24 #define MIDR_PN_MASK U(0xfff) 25 #define MIDR_PN_SHIFT U(0x4) 26 27 /* Extracts the CPU part number from MIDR for checking CPU match */ 28 #define EXTRACT_PARTNUM(x) ((x >> MIDR_PN_SHIFT) & MIDR_PN_MASK) 29 30 /******************************************************************************* 31 * MPIDR macros 32 ******************************************************************************/ 33 #define MPIDR_MT_MASK (ULL(1) << 24) 34 #define MPIDR_CPU_MASK MPIDR_AFFLVL_MASK 35 #define MPIDR_CLUSTER_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS) 36 #define MPIDR_AFFINITY_BITS U(8) 37 #define MPIDR_AFFLVL_MASK ULL(0xff) 38 #define MPIDR_AFF0_SHIFT U(0) 39 #define MPIDR_AFF1_SHIFT U(8) 40 #define MPIDR_AFF2_SHIFT U(16) 41 #define MPIDR_AFF3_SHIFT U(32) 42 #define MPIDR_AFF_SHIFT(_n) MPIDR_AFF##_n##_SHIFT 43 #define MPIDR_AFFINITY_MASK ULL(0xff00ffffff) 44 #define MPIDR_AFFLVL_SHIFT U(3) 45 #define MPIDR_AFFLVL0 ULL(0x0) 46 #define MPIDR_AFFLVL1 ULL(0x1) 47 #define MPIDR_AFFLVL2 ULL(0x2) 48 #define MPIDR_AFFLVL3 ULL(0x3) 49 #define MPIDR_AFFLVL(_n) MPIDR_AFFLVL##_n 50 #define MPIDR_AFFLVL0_VAL(mpidr) \ 51 (((mpidr) >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK) 52 #define MPIDR_AFFLVL1_VAL(mpidr) \ 53 (((mpidr) >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK) 54 #define MPIDR_AFFLVL2_VAL(mpidr) \ 55 (((mpidr) >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK) 56 #define MPIDR_AFFLVL3_VAL(mpidr) \ 57 (((mpidr) >> MPIDR_AFF3_SHIFT) & MPIDR_AFFLVL_MASK) 58 /* 59 * The MPIDR_MAX_AFFLVL count starts from 0. Take care to 60 * add one while using this macro to define array sizes. 61 * TODO: Support only the first 3 affinity levels for now. 62 */ 63 #define MPIDR_MAX_AFFLVL U(2) 64 65 #define MPID_MASK (MPIDR_MT_MASK | \ 66 (MPIDR_AFFLVL_MASK << MPIDR_AFF3_SHIFT) | \ 67 (MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT) | \ 68 (MPIDR_AFFLVL_MASK << MPIDR_AFF1_SHIFT) | \ 69 (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT)) 70 71 #define MPIDR_AFF_ID(mpid, n) \ 72 (((mpid) >> MPIDR_AFF_SHIFT(n)) & MPIDR_AFFLVL_MASK) 73 74 /* 75 * An invalid MPID. This value can be used by functions that return an MPID to 76 * indicate an error. 77 */ 78 #define INVALID_MPID U(0xFFFFFFFF) 79 80 /******************************************************************************* 81 * Definitions for Exception vector offsets 82 ******************************************************************************/ 83 #define CURRENT_EL_SP0 0x0 84 #define CURRENT_EL_SPX 0x200 85 #define LOWER_EL_AARCH64 0x400 86 #define LOWER_EL_AARCH32 0x600 87 88 #define SYNC_EXCEPTION 0x0 89 #define IRQ_EXCEPTION 0x80 90 #define FIQ_EXCEPTION 0x100 91 #define SERROR_EXCEPTION 0x180 92 93 /******************************************************************************* 94 * Encodings for GICv5 EL3 system registers 95 ******************************************************************************/ 96 #define ICC_PPI_DOMAINR0_EL3 S3_6_C12_C8_4 97 #define ICC_PPI_DOMAINR1_EL3 S3_6_C12_C8_5 98 #define ICC_PPI_DOMAINR2_EL3 S3_6_C12_C8_6 99 #define ICC_PPI_DOMAINR3_EL3 S3_6_C12_C8_7 100 101 #define ICC_PPI_DOMAINR_FIELD_MASK ULL(0x3) 102 #define ICC_PPI_DOMAINR_COUNT (32) 103 104 /******************************************************************************* 105 * Definitions for CPU system register interface to GICv3 106 ******************************************************************************/ 107 #define ICC_IGRPEN1_EL1 S3_0_C12_C12_7 108 #define ICC_SGI1R S3_0_C12_C11_5 109 #define ICC_ASGI1R S3_0_C12_C11_6 110 #define ICC_SRE_EL1 S3_0_C12_C12_5 111 #define ICC_SRE_EL2 S3_4_C12_C9_5 112 #define ICC_SRE_EL3 S3_6_C12_C12_5 113 #define ICC_CTLR_EL1 S3_0_C12_C12_4 114 #define ICC_CTLR_EL3 S3_6_C12_C12_4 115 #define ICC_PMR_EL1 S3_0_C4_C6_0 116 #define ICC_RPR_EL1 S3_0_C12_C11_3 117 #define ICC_IGRPEN1_EL3 S3_6_c12_c12_7 118 #define ICC_IGRPEN0_EL1 S3_0_c12_c12_6 119 #define ICC_HPPIR0_EL1 S3_0_c12_c8_2 120 #define ICC_HPPIR1_EL1 S3_0_c12_c12_2 121 #define ICC_IAR0_EL1 S3_0_c12_c8_0 122 #define ICC_IAR1_EL1 S3_0_c12_c12_0 123 #define ICC_EOIR0_EL1 S3_0_c12_c8_1 124 #define ICC_EOIR1_EL1 S3_0_c12_c12_1 125 #define ICC_SGI0R_EL1 S3_0_c12_c11_7 126 127 /******************************************************************************* 128 * Definitions for EL2 system registers for save/restore routine 129 ******************************************************************************/ 130 #define CNTPOFF_EL2 S3_4_C14_C0_6 131 #define HDFGRTR2_EL2 S3_4_C3_C1_0 132 #define HDFGWTR2_EL2 S3_4_C3_C1_1 133 #define HFGRTR2_EL2 S3_4_C3_C1_2 134 #define HFGWTR2_EL2 S3_4_C3_C1_3 135 #define HDFGRTR_EL2 S3_4_C3_C1_4 136 #define HDFGWTR_EL2 S3_4_C3_C1_5 137 #define HAFGRTR_EL2 S3_4_C3_C1_6 138 #define HFGITR2_EL2 S3_4_C3_C1_7 139 #define HFGITR_EL2 S3_4_C1_C1_6 140 #define HFGRTR_EL2 S3_4_C1_C1_4 141 #define HFGWTR_EL2 S3_4_C1_C1_5 142 #define ICH_HCR_EL2 S3_4_C12_C11_0 143 #define ICH_VMCR_EL2 S3_4_C12_C11_7 144 #define MPAMVPM0_EL2 S3_4_C10_C6_0 145 #define MPAMVPM1_EL2 S3_4_C10_C6_1 146 #define MPAMVPM2_EL2 S3_4_C10_C6_2 147 #define MPAMVPM3_EL2 S3_4_C10_C6_3 148 #define MPAMVPM4_EL2 S3_4_C10_C6_4 149 #define MPAMVPM5_EL2 S3_4_C10_C6_5 150 #define MPAMVPM6_EL2 S3_4_C10_C6_6 151 #define MPAMVPM7_EL2 S3_4_C10_C6_7 152 #define MPAMVPMV_EL2 S3_4_C10_C4_1 153 #define VNCR_EL2 S3_4_C2_C2_0 154 #define PMSCR_EL2 S3_4_C9_C9_0 155 #define TFSR_EL2 S3_4_C5_C6_0 156 #define CONTEXTIDR_EL2 S3_4_C13_C0_1 157 #define TTBR1_EL2 S3_4_C2_C0_1 158 159 /******************************************************************************* 160 * Generic timer memory mapped registers & offsets 161 ******************************************************************************/ 162 #define CNTCR_OFF U(0x000) 163 #define CNTCV_OFF U(0x008) 164 #define CNTFID_OFF U(0x020) 165 166 #define CNTCR_EN (U(1) << 0) 167 #define CNTCR_HDBG (U(1) << 1) 168 #define CNTCR_FCREQ(x) ((x) << 8) 169 170 /******************************************************************************* 171 * System register bit definitions 172 ******************************************************************************/ 173 /* CLIDR definitions */ 174 #define LOUIS_SHIFT U(21) 175 #define LOC_SHIFT U(24) 176 #define CTYPE_SHIFT(n) U(3 * (n - 1)) 177 #define CLIDR_FIELD_WIDTH U(3) 178 179 /* CSSELR definitions */ 180 #define LEVEL_SHIFT U(1) 181 182 /* Data cache set/way op type defines */ 183 #define DCISW U(0x0) 184 #define DCCISW U(0x1) 185 #if ERRATA_A53_827319 186 #define DCCSW DCCISW 187 #else 188 #define DCCSW U(0x2) 189 #endif 190 191 #define ID_REG_FIELD_MASK ULL(0xf) 192 193 /* ID_AA64PFR0_EL1 definitions */ 194 #define ID_AA64PFR0_EL0_SHIFT U(0) 195 #define ID_AA64PFR0_EL1_SHIFT U(4) 196 #define ID_AA64PFR0_EL2_SHIFT U(8) 197 #define ID_AA64PFR0_EL3_SHIFT U(12) 198 199 #define ID_AA64PFR0_AMU_SHIFT U(44) 200 #define ID_AA64PFR0_AMU_MASK ULL(0xf) 201 #define ID_AA64PFR0_AMU_V1 ULL(0x1) 202 #define ID_AA64PFR0_AMU_V1P1 U(0x2) 203 204 #define ID_AA64PFR0_ELX_MASK ULL(0xf) 205 206 #define ID_AA64PFR0_GIC_SHIFT U(24) 207 #define ID_AA64PFR0_GIC_WIDTH U(4) 208 #define ID_AA64PFR0_GIC_MASK ULL(0xf) 209 210 #define ID_AA64PFR0_SVE_SHIFT U(32) 211 #define ID_AA64PFR0_SVE_MASK ULL(0xf) 212 #define ID_AA64PFR0_SVE_LENGTH U(4) 213 #define SVE_IMPLEMENTED ULL(0x1) 214 215 #define ID_AA64PFR0_SEL2_SHIFT U(36) 216 #define ID_AA64PFR0_SEL2_MASK ULL(0xf) 217 218 #define ID_AA64PFR0_MPAM_SHIFT U(40) 219 #define ID_AA64PFR0_MPAM_MASK ULL(0xf) 220 221 #define ID_AA64PFR0_DIT_SHIFT U(48) 222 #define ID_AA64PFR0_DIT_MASK ULL(0xf) 223 #define ID_AA64PFR0_DIT_LENGTH U(4) 224 #define DIT_IMPLEMENTED ULL(1) 225 226 #define ID_AA64PFR0_CSV2_SHIFT U(56) 227 #define ID_AA64PFR0_CSV2_MASK ULL(0xf) 228 #define ID_AA64PFR0_CSV2_LENGTH U(4) 229 #define CSV2_2_IMPLEMENTED ULL(0x2) 230 #define CSV2_3_IMPLEMENTED ULL(0x3) 231 232 #define ID_AA64PFR0_FEAT_RME_SHIFT U(52) 233 #define ID_AA64PFR0_FEAT_RME_MASK ULL(0xf) 234 #define ID_AA64PFR0_FEAT_RME_LENGTH U(4) 235 #define RME_NOT_IMPLEMENTED ULL(0) 236 237 #define ID_AA64PFR0_RAS_SHIFT U(28) 238 #define ID_AA64PFR0_RAS_MASK ULL(0xf) 239 #define ID_AA64PFR0_RAS_LENGTH U(4) 240 241 /* Exception level handling */ 242 #define EL_IMPL_NONE ULL(0) 243 #define EL_IMPL_A64ONLY ULL(1) 244 #define EL_IMPL_A64_A32 ULL(2) 245 246 /* ID_AA64DFR0_EL1.DebugVer definitions */ 247 #define ID_AA64DFR0_DEBUGVER_SHIFT U(0) 248 #define ID_AA64DFR0_DEBUGVER_MASK ULL(0xf) 249 #define DEBUGVER_V8P9_IMPLEMENTED ULL(0xb) 250 251 /* ID_AA64DFR0_EL1.TraceVer definitions */ 252 #define ID_AA64DFR0_TRACEVER_SHIFT U(4) 253 #define ID_AA64DFR0_TRACEVER_MASK ULL(0xf) 254 #define ID_AA64DFR0_TRACEVER_LENGTH U(4) 255 256 #define ID_AA64DFR0_TRACEFILT_SHIFT U(40) 257 #define ID_AA64DFR0_TRACEFILT_MASK U(0xf) 258 #define ID_AA64DFR0_TRACEFILT_LENGTH U(4) 259 #define TRACEFILT_IMPLEMENTED ULL(1) 260 261 #define ID_AA64DFR0_PMUVER_LENGTH U(4) 262 #define ID_AA64DFR0_PMUVER_SHIFT U(8) 263 #define ID_AA64DFR0_PMUVER_MASK U(0xf) 264 #define ID_AA64DFR0_PMUVER_PMUV3 U(1) 265 #define ID_AA64DFR0_PMUVER_PMUV3P9 U(9) 266 #define ID_AA64DFR0_PMUVER_IMP_DEF U(0xf) 267 268 /* ID_AA64DFR0_EL1.SEBEP definitions */ 269 #define ID_AA64DFR0_SEBEP_SHIFT U(24) 270 #define ID_AA64DFR0_SEBEP_MASK ULL(0xf) 271 #define SEBEP_IMPLEMENTED ULL(1) 272 273 /* ID_AA64DFR0_EL1.PMS definitions (for ARMv8.2+) */ 274 #define ID_AA64DFR0_PMS_SHIFT U(32) 275 #define ID_AA64DFR0_PMS_MASK ULL(0xf) 276 #define SPE_IMPLEMENTED ULL(0x1) 277 #define SPE_NOT_IMPLEMENTED ULL(0x0) 278 279 /* ID_AA64DFR0_EL1.TraceBuffer definitions */ 280 #define ID_AA64DFR0_TRACEBUFFER_SHIFT U(44) 281 #define ID_AA64DFR0_TRACEBUFFER_MASK ULL(0xf) 282 #define TRACEBUFFER_IMPLEMENTED ULL(1) 283 284 /* ID_AA64DFR0_EL1.MTPMU definitions (for ARMv8.6+) */ 285 #define ID_AA64DFR0_MTPMU_SHIFT U(48) 286 #define ID_AA64DFR0_MTPMU_MASK ULL(0xf) 287 #define MTPMU_IMPLEMENTED ULL(1) 288 #define MTPMU_NOT_IMPLEMENTED ULL(15) 289 290 /* ID_AA64DFR0_EL1.BRBE definitions */ 291 #define ID_AA64DFR0_BRBE_SHIFT U(52) 292 #define ID_AA64DFR0_BRBE_MASK ULL(0xf) 293 #define BRBE_IMPLEMENTED ULL(1) 294 295 /* ID_AA64DFR1_EL1 definitions */ 296 #define ID_AA64DFR1_EBEP_SHIFT U(48) 297 #define ID_AA64DFR1_EBEP_MASK ULL(0xf) 298 #define EBEP_IMPLEMENTED ULL(1) 299 300 #define ID_AA64DFR1_BRP_SHIFT U(8) 301 #define ID_AA64DFR1_BRP_WIDTH U(8) 302 303 /* ID_AA64ISAR0_EL1 definitions */ 304 #define ID_AA64ISAR0_RNDR_SHIFT U(60) 305 #define ID_AA64ISAR0_RNDR_MASK ULL(0xf) 306 307 /* ID_AA64ISAR1_EL1 definitions */ 308 #define ID_AA64ISAR1_EL1 S3_0_C0_C6_1 309 310 #define ID_AA64ISAR1_LS64_SHIFT U(60) 311 #define ID_AA64ISAR1_LS64_MASK ULL(0xf) 312 #define LS64_ACCDATA_IMPLEMENTED ULL(0x3) 313 #define LS64_V_IMPLEMENTED ULL(0x2) 314 #define LS64_IMPLEMENTED ULL(0x1) 315 #define LS64_NOT_IMPLEMENTED ULL(0x0) 316 317 #define ID_AA64ISAR1_SB_SHIFT U(36) 318 #define ID_AA64ISAR1_SB_MASK ULL(0xf) 319 #define SB_IMPLEMENTED ULL(0x1) 320 #define SB_NOT_IMPLEMENTED ULL(0x0) 321 322 #define ID_AA64ISAR1_GPI_SHIFT U(28) 323 #define ID_AA64ISAR1_GPI_MASK ULL(0xf) 324 #define ID_AA64ISAR1_GPA_SHIFT U(24) 325 #define ID_AA64ISAR1_GPA_MASK ULL(0xf) 326 327 #define ID_AA64ISAR1_API_SHIFT U(8) 328 #define ID_AA64ISAR1_API_MASK ULL(0xf) 329 #define ID_AA64ISAR1_APA_SHIFT U(4) 330 #define ID_AA64ISAR1_APA_MASK ULL(0xf) 331 332 /* ID_AA64ISAR2_EL1 definitions */ 333 #define ID_AA64ISAR2_EL1 S3_0_C0_C6_2 334 #define ID_AA64ISAR2_EL1_MOPS_SHIFT U(16) 335 #define ID_AA64ISAR2_EL1_MOPS_MASK ULL(0xf) 336 337 #define MOPS_IMPLEMENTED ULL(0x1) 338 339 #define ID_AA64ISAR2_GPA3_SHIFT U(8) 340 #define ID_AA64ISAR2_GPA3_MASK ULL(0xf) 341 342 #define ID_AA64ISAR2_APA3_SHIFT U(12) 343 #define ID_AA64ISAR2_APA3_MASK ULL(0xf) 344 345 #define ID_AA64ISAR2_CLRBHB_SHIFT U(28) 346 #define ID_AA64ISAR2_CLRBHB_MASK ULL(0xf) 347 348 #define ID_AA64ISAR2_SYSREG128_SHIFT U(32) 349 #define ID_AA64ISAR2_SYSREG128_MASK ULL(0xf) 350 351 /* ID_AA64ISAR3_EL1 definitions */ 352 #define ID_AA64ISAR3_EL1 S3_0_C0_C6_3 353 #define ID_AA64ISAR3_EL1_CPA_SHIFT U(0) 354 #define ID_AA64ISAR3_EL1_CPA_MASK ULL(0xf) 355 356 #define CPA2_IMPLEMENTED ULL(0x2) 357 358 /* ID_AA64MMFR0_EL1 definitions */ 359 #define ID_AA64MMFR0_EL1_PARANGE_SHIFT U(0) 360 #define ID_AA64MMFR0_EL1_PARANGE_MASK ULL(0xf) 361 362 #define PARANGE_0000 U(32) 363 #define PARANGE_0001 U(36) 364 #define PARANGE_0010 U(40) 365 #define PARANGE_0011 U(42) 366 #define PARANGE_0100 U(44) 367 #define PARANGE_0101 U(48) 368 #define PARANGE_0110 U(52) 369 #define PARANGE_0111 U(56) 370 371 #define ID_AA64MMFR0_EL1_ECV_SHIFT U(60) 372 #define ID_AA64MMFR0_EL1_ECV_MASK ULL(0xf) 373 #define ID_AA64MMFR0_EL1_ECV_SELF_SYNCH ULL(0x2) 374 #define ECV_IMPLEMENTED ULL(0x1) 375 376 #define ID_AA64MMFR0_EL1_FGT_SHIFT U(56) 377 #define ID_AA64MMFR0_EL1_FGT_MASK ULL(0xf) 378 #define FGT2_IMPLEMENTED ULL(0x2) 379 #define FGT_IMPLEMENTED ULL(0x1) 380 #define FGT_NOT_IMPLEMENTED ULL(0x0) 381 382 #define ID_AA64MMFR0_EL1_TGRAN4_SHIFT U(28) 383 #define ID_AA64MMFR0_EL1_TGRAN4_MASK ULL(0xf) 384 385 #define ID_AA64MMFR0_EL1_TGRAN64_SHIFT U(24) 386 #define ID_AA64MMFR0_EL1_TGRAN64_MASK ULL(0xf) 387 388 #define ID_AA64MMFR0_EL1_TGRAN16_SHIFT U(20) 389 #define ID_AA64MMFR0_EL1_TGRAN16_MASK ULL(0xf) 390 #define TGRAN16_IMPLEMENTED ULL(0x1) 391 392 /* ID_AA64MMFR1_EL1 definitions */ 393 #define ID_AA64MMFR1_EL1_TWED_SHIFT U(32) 394 #define ID_AA64MMFR1_EL1_TWED_MASK ULL(0xf) 395 #define TWED_IMPLEMENTED ULL(0x1) 396 397 #define ID_AA64MMFR1_EL1_PAN_SHIFT U(20) 398 #define ID_AA64MMFR1_EL1_PAN_MASK ULL(0xf) 399 #define PAN_IMPLEMENTED ULL(0x1) 400 #define PAN2_IMPLEMENTED ULL(0x2) 401 #define PAN3_IMPLEMENTED ULL(0x3) 402 403 #define ID_AA64MMFR1_EL1_VHE_SHIFT U(8) 404 #define ID_AA64MMFR1_EL1_VHE_MASK ULL(0xf) 405 406 #define ID_AA64MMFR1_EL1_HCX_SHIFT U(40) 407 #define ID_AA64MMFR1_EL1_HCX_MASK ULL(0xf) 408 #define HCX_IMPLEMENTED ULL(0x1) 409 410 /* ID_AA64MMFR2_EL1 definitions */ 411 #define ID_AA64MMFR2_EL1 S3_0_C0_C7_2 412 413 #define ID_AA64MMFR2_EL1_ST_SHIFT U(28) 414 #define ID_AA64MMFR2_EL1_ST_MASK ULL(0xf) 415 416 #define ID_AA64MMFR2_EL1_CCIDX_SHIFT U(20) 417 #define ID_AA64MMFR2_EL1_CCIDX_MASK ULL(0xf) 418 #define ID_AA64MMFR2_EL1_CCIDX_LENGTH U(4) 419 420 #define ID_AA64MMFR2_EL1_UAO_SHIFT U(4) 421 #define ID_AA64MMFR2_EL1_UAO_MASK ULL(0xf) 422 423 #define ID_AA64MMFR2_EL1_CNP_SHIFT U(0) 424 #define ID_AA64MMFR2_EL1_CNP_MASK ULL(0xf) 425 426 #define ID_AA64MMFR2_EL1_NV_SHIFT U(24) 427 #define ID_AA64MMFR2_EL1_NV_MASK ULL(0xf) 428 #define NV2_IMPLEMENTED ULL(0x2) 429 430 /* ID_AA64MMFR3_EL1 definitions */ 431 #define ID_AA64MMFR3_EL1 S3_0_C0_C7_3 432 433 #define ID_AA64MMFR3_EL1_D128_SHIFT U(32) 434 #define ID_AA64MMFR3_EL1_D128_MASK ULL(0xf) 435 #define D128_IMPLEMENTED ULL(0x1) 436 437 #define ID_AA64MMFR3_EL1_MEC_SHIFT U(28) 438 #define ID_AA64MMFR3_EL1_MEC_MASK ULL(0xf) 439 440 #define ID_AA64MMFR3_EL1_AIE_SHIFT U(24) 441 #define ID_AA64MMFR3_EL1_AIE_MASK ULL(0xf) 442 443 #define ID_AA64MMFR3_EL1_S2POE_SHIFT U(20) 444 #define ID_AA64MMFR3_EL1_S2POE_MASK ULL(0xf) 445 446 #define ID_AA64MMFR3_EL1_S1POE_SHIFT U(16) 447 #define ID_AA64MMFR3_EL1_S1POE_MASK ULL(0xf) 448 449 #define ID_AA64MMFR3_EL1_S2PIE_SHIFT U(12) 450 #define ID_AA64MMFR3_EL1_S2PIE_MASK ULL(0xf) 451 452 #define ID_AA64MMFR3_EL1_S1PIE_SHIFT U(8) 453 #define ID_AA64MMFR3_EL1_S1PIE_MASK ULL(0xf) 454 455 #define ID_AA64MMFR3_EL1_SCTLR2_SHIFT U(4) 456 #define ID_AA64MMFR3_EL1_SCTLR2_MASK ULL(0xf) 457 #define SCTLR2_IMPLEMENTED ULL(1) 458 459 #define ID_AA64MMFR3_EL1_TCRX_SHIFT U(0) 460 #define ID_AA64MMFR3_EL1_TCRX_MASK ULL(0xf) 461 462 /* ID_AA64MMFR4_EL1 definitions */ 463 #define ID_AA64MMFR4_EL1 S3_0_C0_C7_4 464 465 #define ID_AA64MMFR4_EL1_FGWTE3_SHIFT U(16) 466 #define ID_AA64MMFR4_EL1_FGWTE3_MASK ULL(0xf) 467 #define FGWTE3_IMPLEMENTED ULL(0x1) 468 469 /* ID_AA64PFR1_EL1 definitions */ 470 471 #define ID_AA64PFR1_EL1_BT_SHIFT U(0) 472 #define ID_AA64PFR1_EL1_BT_MASK ULL(0xf) 473 #define BTI_IMPLEMENTED ULL(1) /* The BTI mechanism is implemented */ 474 475 #define ID_AA64PFR1_EL1_SSBS_SHIFT U(4) 476 #define ID_AA64PFR1_EL1_SSBS_MASK ULL(0xf) 477 #define SSBS_NOT_IMPLEMENTED ULL(0) /* No architectural SSBS support */ 478 479 #define ID_AA64PFR1_EL1_MTE_SHIFT U(8) 480 #define ID_AA64PFR1_EL1_MTE_MASK ULL(0xf) 481 482 #define ID_AA64PFR1_EL1_RNDR_TRAP_SHIFT U(28) 483 #define ID_AA64PFR1_EL1_RNDR_TRAP_MASK U(0xf) 484 #define RNG_TRAP_IMPLEMENTED ULL(0x1) 485 486 #define ID_AA64PFR1_EL1_NMI_SHIFT U(36) 487 #define ID_AA64PFR1_EL1_NMI_MASK ULL(0xf) 488 #define NMI_IMPLEMENTED ULL(1) 489 490 #define ID_AA64PFR1_EL1_GCS_SHIFT U(44) 491 #define ID_AA64PFR1_EL1_GCS_MASK ULL(0xf) 492 #define GCS_IMPLEMENTED ULL(1) 493 494 #define ID_AA64PFR1_EL1_THE_SHIFT U(48) 495 #define ID_AA64PFR1_EL1_THE_MASK ULL(0xf) 496 #define THE_IMPLEMENTED ULL(1) 497 498 #define ID_AA64PFR1_EL1_PFAR_SHIFT U(60) 499 #define ID_AA64PFR1_EL1_PFAR_MASK ULL(0xf) 500 501 502 /* ID_AA64PFR2_EL1 definitions */ 503 #define ID_AA64PFR2_EL1 S3_0_C0_C4_2 504 505 #define ID_AA64PFR2_EL1_MTEPERM_SHIFT U(0) 506 #define ID_AA64PFR2_EL1_MTEPERM_MASK ULL(0xf) 507 508 #define ID_AA64PFR2_EL1_MTESTOREONLY_SHIFT U(4) 509 #define ID_AA64PFR2_EL1_MTESTOREONLY_MASK ULL(0xf) 510 511 #define ID_AA64PFR2_EL1_MTEFAR_SHIFT U(8) 512 #define ID_AA64PFR2_EL1_MTEFAR_MASK ULL(0xf) 513 514 #define ID_AA64PFR2_EL1_FPMR_SHIFT U(32) 515 #define ID_AA64PFR2_EL1_FPMR_MASK ULL(0xf) 516 517 #define FPMR_IMPLEMENTED ULL(0x1) 518 519 #define VDISR_EL2 S3_4_C12_C1_1 520 #define VSESR_EL2 S3_4_C5_C2_3 521 522 /* Memory Tagging Extension is not implemented */ 523 #define MTE_UNIMPLEMENTED U(0) 524 /* FEAT_MTE: MTE instructions accessible at EL0 are implemented */ 525 #define MTE_IMPLEMENTED_EL0 U(1) 526 /* FEAT_MTE2: Full MTE is implemented */ 527 #define MTE_IMPLEMENTED_ELX U(2) 528 /* 529 * FEAT_MTE3: MTE is implemented with support for 530 * asymmetric Tag Check Fault handling 531 */ 532 #define MTE_IMPLEMENTED_ASY U(3) 533 534 #define ID_AA64PFR1_MPAM_FRAC_SHIFT ULL(16) 535 #define ID_AA64PFR1_MPAM_FRAC_MASK ULL(0xf) 536 537 #define ID_AA64PFR1_EL1_SME_SHIFT U(24) 538 #define ID_AA64PFR1_EL1_SME_MASK ULL(0xf) 539 #define ID_AA64PFR1_EL1_SME_WIDTH U(4) 540 #define SME_IMPLEMENTED ULL(0x1) 541 #define SME2_IMPLEMENTED ULL(0x2) 542 #define SME_NOT_IMPLEMENTED ULL(0x0) 543 544 /* ID_AA64PFR2_EL1 definitions */ 545 #define ID_AA64PFR2_EL1 S3_0_C0_C4_2 546 #define ID_AA64PFR2_EL1_GCIE_SHIFT 12 547 #define ID_AA64PFR2_EL1_GCIE_MASK ULL(0xf) 548 549 /* ID_PFR1_EL1 definitions */ 550 #define ID_PFR1_VIRTEXT_SHIFT U(12) 551 #define ID_PFR1_VIRTEXT_MASK U(0xf) 552 #define GET_VIRT_EXT(id) (((id) >> ID_PFR1_VIRTEXT_SHIFT) \ 553 & ID_PFR1_VIRTEXT_MASK) 554 555 /* SCTLR definitions */ 556 #define SCTLR_EL2_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ 557 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \ 558 (U(1) << 11) | (U(1) << 5) | (U(1) << 4)) 559 560 #define SCTLR_EL1_RES1 ((UL(1) << 29) | (UL(1) << 28) | (UL(1) << 23) | \ 561 (UL(1) << 22) | (UL(1) << 20) | (UL(1) << 11)) 562 563 #define SCTLR_AARCH32_EL1_RES1 \ 564 ((U(1) << 23) | (U(1) << 22) | (U(1) << 11) | \ 565 (U(1) << 4) | (U(1) << 3)) 566 567 #define SCTLR_EL3_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ 568 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \ 569 (U(1) << 11) | (U(1) << 5) | (U(1) << 4)) 570 571 #define SCTLR_M_BIT (ULL(1) << 0) 572 #define SCTLR_A_BIT (ULL(1) << 1) 573 #define SCTLR_C_BIT (ULL(1) << 2) 574 #define SCTLR_SA_BIT (ULL(1) << 3) 575 #define SCTLR_SA0_BIT (ULL(1) << 4) 576 #define SCTLR_CP15BEN_BIT (ULL(1) << 5) 577 #define SCTLR_nAA_BIT (ULL(1) << 6) 578 #define SCTLR_ITD_BIT (ULL(1) << 7) 579 #define SCTLR_SED_BIT (ULL(1) << 8) 580 #define SCTLR_UMA_BIT (ULL(1) << 9) 581 #define SCTLR_EnRCTX_BIT (ULL(1) << 10) 582 #define SCTLR_EOS_BIT (ULL(1) << 11) 583 #define SCTLR_I_BIT (ULL(1) << 12) 584 #define SCTLR_EnDB_BIT (ULL(1) << 13) 585 #define SCTLR_DZE_BIT (ULL(1) << 14) 586 #define SCTLR_UCT_BIT (ULL(1) << 15) 587 #define SCTLR_NTWI_BIT (ULL(1) << 16) 588 #define SCTLR_NTWE_BIT (ULL(1) << 18) 589 #define SCTLR_WXN_BIT (ULL(1) << 19) 590 #define SCTLR_TSCXT_BIT (ULL(1) << 20) 591 #define SCTLR_IESB_BIT (ULL(1) << 21) 592 #define SCTLR_EIS_BIT (ULL(1) << 22) 593 #define SCTLR_SPAN_BIT (ULL(1) << 23) 594 #define SCTLR_E0E_BIT (ULL(1) << 24) 595 #define SCTLR_EE_BIT (ULL(1) << 25) 596 #define SCTLR_UCI_BIT (ULL(1) << 26) 597 #define SCTLR_EnDA_BIT (ULL(1) << 27) 598 #define SCTLR_nTLSMD_BIT (ULL(1) << 28) 599 #define SCTLR_LSMAOE_BIT (ULL(1) << 29) 600 #define SCTLR_EnIB_BIT (ULL(1) << 30) 601 #define SCTLR_EnIA_BIT (ULL(1) << 31) 602 #define SCTLR_BT0_BIT (ULL(1) << 35) 603 #define SCTLR_BT1_BIT (ULL(1) << 36) 604 #define SCTLR_BT_BIT (ULL(1) << 36) 605 #define SCTLR_ITFSB_BIT (ULL(1) << 37) 606 #define SCTLR_TCF0_SHIFT U(38) 607 #define SCTLR_TCF0_MASK ULL(3) 608 #define SCTLR_ENTP2_BIT (ULL(1) << 60) 609 #define SCTLR_SPINTMASK_BIT (ULL(1) << 62) 610 611 /* Tag Check Faults in EL0 have no effect on the PE */ 612 #define SCTLR_TCF0_NO_EFFECT U(0) 613 /* Tag Check Faults in EL0 cause a synchronous exception */ 614 #define SCTLR_TCF0_SYNC U(1) 615 /* Tag Check Faults in EL0 are asynchronously accumulated */ 616 #define SCTLR_TCF0_ASYNC U(2) 617 /* 618 * Tag Check Faults in EL0 cause a synchronous exception on reads, 619 * and are asynchronously accumulated on writes 620 */ 621 #define SCTLR_TCF0_SYNCR_ASYNCW U(3) 622 623 #define SCTLR_TCF_SHIFT U(40) 624 #define SCTLR_TCF_MASK ULL(3) 625 626 /* Tag Check Faults in EL1 have no effect on the PE */ 627 #define SCTLR_TCF_NO_EFFECT U(0) 628 /* Tag Check Faults in EL1 cause a synchronous exception */ 629 #define SCTLR_TCF_SYNC U(1) 630 /* Tag Check Faults in EL1 are asynchronously accumulated */ 631 #define SCTLR_TCF_ASYNC U(2) 632 /* 633 * Tag Check Faults in EL1 cause a synchronous exception on reads, 634 * and are asynchronously accumulated on writes 635 */ 636 #define SCTLR_TCF_SYNCR_ASYNCW U(3) 637 638 #define SCTLR_ATA0_BIT (ULL(1) << 42) 639 #define SCTLR_ATA_BIT (ULL(1) << 43) 640 #define SCTLR_DSSBS_SHIFT U(44) 641 #define SCTLR_DSSBS_BIT (ULL(1) << SCTLR_DSSBS_SHIFT) 642 #define SCTLR_TWEDEn_BIT (ULL(1) << 45) 643 #define SCTLR_TWEDEL_SHIFT U(46) 644 #define SCTLR_TWEDEL_MASK ULL(0xf) 645 #define SCTLR_EnASR_BIT (ULL(1) << 54) 646 #define SCTLR_EnAS0_BIT (ULL(1) << 55) 647 #define SCTLR_EnALS_BIT (ULL(1) << 56) 648 #define SCTLR_EPAN_BIT (ULL(1) << 57) 649 #define SCTLR_RESET_VAL SCTLR_EL3_RES1 650 651 #define SCTLR2_EnPACM_BIT (ULL(1) << 7) 652 #define SCTLR2_CPTA_BIT (ULL(1) << 9) 653 #define SCTLR2_CPTM_BIT (ULL(1) << 11) 654 655 /* SCTLR2 currently has no RES1 fields so reset to 0 */ 656 #define SCTLR2_RESET_VAL ULL(0) 657 658 /* CPACR_EL1 definitions */ 659 #define CPACR_EL1_FPEN(x) ((x) << 20) 660 #define CPACR_EL1_FP_TRAP_EL0 UL(0x1) 661 #define CPACR_EL1_FP_TRAP_ALL UL(0x2) 662 #define CPACR_EL1_FP_TRAP_NONE UL(0x3) 663 #define CPACR_EL1_SMEN_SHIFT U(24) 664 #define CPACR_EL1_SMEN_MASK ULL(0x3) 665 666 /* SCR definitions */ 667 #if ENABLE_FEAT_GCIE 668 #define SCR_RES1_BITS ((U(1) << 4) | (U(1) << 5) | SCR_FIQ_BIT) 669 #else 670 #define SCR_RES1_BITS ((U(1) << 4) | (U(1) << 5)) 671 #endif 672 #define SCR_NSE_SHIFT U(62) 673 #define SCR_NSE_BIT (ULL(1) << SCR_NSE_SHIFT) 674 #define SCR_FGTEN2_BIT (UL(1) << 59) 675 #define SCR_PFAREn_BIT (UL(1) << 53) 676 #define SCR_EnFPM_BIT (ULL(1) << 50) 677 #define SCR_MECEn_BIT (UL(1) << 49) 678 #define SCR_GPF_BIT (UL(1) << 48) 679 #define SCR_D128En_BIT (UL(1) << 47) 680 #define SCR_AIEn_BIT (UL(1) << 46) 681 #define SCR_TWEDEL_SHIFT U(30) 682 #define SCR_TWEDEL_MASK ULL(0xf) 683 #define SCR_PIEN_BIT (UL(1) << 45) 684 #define SCR_SCTLR2En_BIT (UL(1) << 44) 685 #define SCR_TCR2EN_BIT (UL(1) << 43) 686 #define SCR_RCWMASKEn_BIT (UL(1) << 42) 687 #define SCR_ENTP2_SHIFT U(41) 688 #define SCR_ENTP2_BIT (UL(1) << SCR_ENTP2_SHIFT) 689 #define SCR_TRNDR_BIT (UL(1) << 40) 690 #define SCR_GCSEn_BIT (UL(1) << 39) 691 #define SCR_HXEn_BIT (UL(1) << 38) 692 #define SCR_ADEn_BIT (UL(1) << 37) 693 #define SCR_EnAS0_BIT (UL(1) << 36) 694 #define SCR_AMVOFFEN_SHIFT U(35) 695 #define SCR_AMVOFFEN_BIT (UL(1) << SCR_AMVOFFEN_SHIFT) 696 #define SCR_TWEDEn_BIT (UL(1) << 29) 697 #define SCR_ECVEN_BIT (UL(1) << 28) 698 #define SCR_FGTEN_BIT (UL(1) << 27) 699 #define SCR_ATA_BIT (UL(1) << 26) 700 #define SCR_EnSCXT_BIT (UL(1) << 25) 701 #define SCR_FIEN_BIT (UL(1) << 21) 702 #define SCR_EEL2_BIT (UL(1) << 18) 703 #define SCR_API_BIT (UL(1) << 17) 704 #define SCR_APK_BIT (UL(1) << 16) 705 #define SCR_TERR_BIT (UL(1) << 15) 706 #define SCR_TWE_BIT (UL(1) << 13) 707 #define SCR_TWI_BIT (UL(1) << 12) 708 #define SCR_ST_BIT (UL(1) << 11) 709 #define SCR_RW_BIT (UL(1) << 10) 710 #define SCR_SIF_BIT (UL(1) << 9) 711 #define SCR_HCE_BIT (UL(1) << 8) 712 #define SCR_SMD_BIT (UL(1) << 7) 713 #define SCR_EA_BIT (UL(1) << 3) 714 #define SCR_FIQ_BIT (UL(1) << 2) 715 #define SCR_IRQ_BIT (UL(1) << 1) 716 #define SCR_NS_BIT (UL(1) << 0) 717 #define SCR_VALID_BIT_MASK U(0x24000002F8F) 718 #define SCR_RESET_VAL SCR_RES1_BITS 719 720 /* MDCR_EL3 definitions */ 721 #define MDCR_EBWE_BIT (ULL(1) << 43) 722 #define MDCR_EnPMS3_BIT (ULL(1) << 42) 723 #define MDCR_PMEE(x) ((x) << 40) 724 #define MDCR_PMEE_CTRL_EL2 ULL(0x1) 725 #define MDCR_E3BREC_BIT (ULL(1) << 38) 726 #define MDCR_E3BREW_BIT (ULL(1) << 37) 727 #define MDCR_EnPMSN_BIT (ULL(1) << 36) 728 #define MDCR_MPMX_BIT (ULL(1) << 35) 729 #define MDCR_MCCD_BIT (ULL(1) << 34) 730 #define MDCR_SBRBE_SHIFT U(32) 731 #define MDCR_SBRBE(x) ((x) << MDCR_SBRBE_SHIFT) 732 #define MDCR_SBRBE_ALL ULL(0x3) 733 #define MDCR_SBRBE_NS ULL(0x1) 734 #define MDCR_NSTB_EN_BIT (ULL(1) << 24) 735 #define MDCR_NSTB_SS_BIT (ULL(1) << 25) 736 #define MDCR_NSTBE_BIT (ULL(1) << 26) 737 #define MDCR_MTPME_BIT (ULL(1) << 28) 738 #define MDCR_TDCC_BIT (ULL(1) << 27) 739 #define MDCR_SCCD_BIT (ULL(1) << 23) 740 #define MDCR_EPMAD_BIT (ULL(1) << 21) 741 #define MDCR_EDAD_BIT (ULL(1) << 20) 742 #define MDCR_TTRF_BIT (ULL(1) << 19) 743 #define MDCR_STE_BIT (ULL(1) << 18) 744 #define MDCR_SPME_BIT (ULL(1) << 17) 745 #define MDCR_SDD_BIT (ULL(1) << 16) 746 #define MDCR_SPD32(x) ((x) << 14) 747 #define MDCR_SPD32_LEGACY ULL(0x0) 748 #define MDCR_SPD32_DISABLE ULL(0x2) 749 #define MDCR_SPD32_ENABLE ULL(0x3) 750 #define MDCR_NSPB_SS_BIT (ULL(1) << 13) 751 #define MDCR_NSPB_EN_BIT (ULL(1) << 12) 752 #define MDCR_NSPBE_BIT (ULL(1) << 11) 753 #define MDCR_TDOSA_BIT (ULL(1) << 10) 754 #define MDCR_TDA_BIT (ULL(1) << 9) 755 #define MDCR_EnPM2_BIT (ULL(1) << 7) 756 #define MDCR_TPM_BIT (ULL(1) << 6) 757 #define MDCR_RLTE_BIT (ULL(1) << 0) 758 #define MDCR_EL3_RESET_VAL MDCR_MTPME_BIT 759 760 /* MDCR_EL2 definitions */ 761 #define MDCR_EL2_MTPME (ULL(1) << 28) 762 #define MDCR_EL2_HLP_BIT (ULL(1) << 26) 763 #define MDCR_EL2_E2TB(x) ULL((x) << 24) 764 #define MDCR_EL2_E2TB_EL1 ULL(0x3) 765 #define MDCR_EL2_HCCD_BIT (ULL(1) << 23) 766 #define MDCR_EL2_TTRF (ULL(1) << 19) 767 #define MDCR_EL2_HPMD_BIT (ULL(1) << 17) 768 #define MDCR_EL2_TPMS (ULL(1) << 14) 769 #define MDCR_EL2_E2PB(x) ULL((x) << 12) 770 #define MDCR_EL2_E2PB_EL1 ULL(0x3) 771 #define MDCR_EL2_TDRA_BIT (ULL(1) << 11) 772 #define MDCR_EL2_TDOSA_BIT (ULL(1) << 10) 773 #define MDCR_EL2_TDA_BIT (ULL(1) << 9) 774 #define MDCR_EL2_TDE_BIT (ULL(1) << 8) 775 #define MDCR_EL2_HPME_BIT (ULL(1) << 7) 776 #define MDCR_EL2_TPM_BIT (ULL(1) << 6) 777 #define MDCR_EL2_TPMCR_BIT (ULL(1) << 5) 778 #define MDCR_EL2_HPMN_MASK ULL(0x1f) 779 #define MDCR_EL2_RESET_VAL ULL(0x0) 780 781 /* HSTR_EL2 definitions */ 782 #define HSTR_EL2_RESET_VAL U(0x0) 783 #define HSTR_EL2_T_MASK U(0xff) 784 785 /* CNTHP_CTL_EL2 definitions */ 786 #define CNTHP_CTL_ENABLE_BIT (U(1) << 0) 787 #define CNTHP_CTL_RESET_VAL U(0x0) 788 789 /* VTTBR_EL2 definitions */ 790 #define VTTBR_RESET_VAL ULL(0x0) 791 #define VTTBR_VMID_MASK ULL(0xff) 792 #define VTTBR_VMID_SHIFT U(48) 793 #define VTTBR_BADDR_MASK ULL(0xffffffffffff) 794 #define VTTBR_BADDR_SHIFT U(0) 795 796 /* HCR definitions */ 797 #define HCR_RESET_VAL ULL(0x0) 798 #define HCR_AMVOFFEN_SHIFT U(51) 799 #define HCR_AMVOFFEN_BIT (ULL(1) << HCR_AMVOFFEN_SHIFT) 800 #define HCR_TEA_BIT (ULL(1) << 47) 801 #define HCR_API_BIT (ULL(1) << 41) 802 #define HCR_APK_BIT (ULL(1) << 40) 803 #define HCR_E2H_BIT (ULL(1) << 34) 804 #define HCR_HCD_BIT (ULL(1) << 29) 805 #define HCR_TGE_BIT (ULL(1) << 27) 806 #define HCR_RW_SHIFT U(31) 807 #define HCR_RW_BIT (ULL(1) << HCR_RW_SHIFT) 808 #define HCR_TWE_BIT (ULL(1) << 14) 809 #define HCR_TWI_BIT (ULL(1) << 13) 810 #define HCR_AMO_BIT (ULL(1) << 5) 811 #define HCR_IMO_BIT (ULL(1) << 4) 812 #define HCR_FMO_BIT (ULL(1) << 3) 813 814 /* ISR definitions */ 815 #define ISR_A_SHIFT U(8) 816 #define ISR_I_SHIFT U(7) 817 #define ISR_F_SHIFT U(6) 818 819 /* CNTHCTL_EL2 definitions */ 820 #define CNTHCTL_RESET_VAL U(0x0) 821 #define EVNTEN_BIT (U(1) << 2) 822 #define EL1PCEN_BIT (U(1) << 1) 823 #define EL1PCTEN_BIT (U(1) << 0) 824 825 /* CNTKCTL_EL1 definitions */ 826 #define EL0PTEN_BIT (U(1) << 9) 827 #define EL0VTEN_BIT (U(1) << 8) 828 #define EL0PCTEN_BIT (U(1) << 0) 829 #define EL0VCTEN_BIT (U(1) << 1) 830 #define EVNTEN_BIT (U(1) << 2) 831 #define EVNTDIR_BIT (U(1) << 3) 832 #define EVNTI_SHIFT U(4) 833 #define EVNTI_MASK U(0xf) 834 835 /* CPTR_EL3 definitions */ 836 #define TCPAC_BIT (U(1) << 31) 837 #define TAM_SHIFT U(30) 838 #define TAM_BIT (U(1) << TAM_SHIFT) 839 #define TTA_BIT (U(1) << 20) 840 #define ESM_BIT (U(1) << 12) 841 #define TFP_BIT (U(1) << 10) 842 #define CPTR_EZ_BIT (U(1) << 8) 843 /* TCPAC is always set by default as the register is always present */ 844 #define CPTR_EL3_RESET_VAL ((TAM_BIT | TTA_BIT) & \ 845 ~(CPTR_EZ_BIT | ESM_BIT | TFP_BIT | TCPAC_BIT)) 846 847 /* CPTR_EL2 definitions */ 848 #define CPTR_EL2_RES1 ((U(1) << 13) | (U(1) << 12) | (U(0x3ff))) 849 #define CPTR_EL2_TCPAC_BIT (U(1) << 31) 850 #define CPTR_EL2_TAM_SHIFT U(30) 851 #define CPTR_EL2_TAM_BIT (U(1) << CPTR_EL2_TAM_SHIFT) 852 #define CPTR_EL2_SMEN_MASK ULL(0x3) 853 #define CPTR_EL2_SMEN_SHIFT U(24) 854 #define CPTR_EL2_TTA_BIT (U(1) << 20) 855 #define CPTR_EL2_ZEN_MASK ULL(0x3) 856 #define CPTR_EL2_ZEN_SHIFT U(16) 857 #define CPTR_EL2_TSM_BIT (U(1) << 12) 858 #define CPTR_EL2_TFP_BIT (ULL(1) << 10) 859 #define CPTR_EL2_TZ_BIT (ULL(1) << 8) 860 #define CPTR_EL2_RESET_VAL CPTR_EL2_RES1 861 862 /* VTCR_EL2 definitions */ 863 #define VTCR_RESET_VAL U(0x0) 864 #define VTCR_EL2_MSA (U(1) << 31) 865 866 /* CPSR/SPSR definitions */ 867 #define DAIF_FIQ_BIT (U(1) << 0) 868 #define DAIF_IRQ_BIT (U(1) << 1) 869 #define DAIF_ABT_BIT (U(1) << 2) 870 #define DAIF_DBG_BIT (U(1) << 3) 871 #define SPSR_V_BIT (U(1) << 28) 872 #define SPSR_C_BIT (U(1) << 29) 873 #define SPSR_Z_BIT (U(1) << 30) 874 #define SPSR_N_BIT (U(1) << 31) 875 #define SPSR_DAIF_SHIFT U(6) 876 #define SPSR_DAIF_MASK U(0xf) 877 878 #define SPSR_AIF_SHIFT U(6) 879 #define SPSR_AIF_MASK U(0x7) 880 881 #define SPSR_E_SHIFT U(9) 882 #define SPSR_E_MASK U(0x1) 883 #define SPSR_E_LITTLE U(0x0) 884 #define SPSR_E_BIG U(0x1) 885 886 #define SPSR_T_SHIFT U(5) 887 #define SPSR_T_MASK U(0x1) 888 #define SPSR_T_ARM U(0x0) 889 #define SPSR_T_THUMB U(0x1) 890 891 #define SPSR_M_SHIFT U(4) 892 #define SPSR_M_MASK U(0x1) 893 #define SPSR_M_AARCH64 U(0x0) 894 #define SPSR_M_AARCH32 U(0x1) 895 #define SPSR_M_EL1H U(0x5) 896 #define SPSR_M_EL2H U(0x9) 897 898 #define SPSR_EL_SHIFT U(2) 899 #define SPSR_EL_WIDTH U(2) 900 901 #define SPSR_BTYPE_SHIFT_AARCH64 U(10) 902 #define SPSR_BTYPE_MASK_AARCH64 U(0x3) 903 #define SPSR_SSBS_SHIFT_AARCH64 U(12) 904 #define SPSR_SSBS_BIT_AARCH64 (ULL(1) << SPSR_SSBS_SHIFT_AARCH64) 905 #define SPSR_SSBS_SHIFT_AARCH32 U(23) 906 #define SPSR_SSBS_BIT_AARCH32 (ULL(1) << SPSR_SSBS_SHIFT_AARCH32) 907 #define SPSR_ALLINT_BIT_AARCH64 BIT_64(13) 908 #define SPSR_IL_BIT BIT_64(20) 909 #define SPSR_SS_BIT BIT_64(21) 910 #define SPSR_PAN_BIT BIT_64(22) 911 #define SPSR_UAO_BIT_AARCH64 BIT_64(23) 912 #define SPSR_DIT_BIT BIT(24) 913 #define SPSR_TCO_BIT_AARCH64 BIT_64(25) 914 #define SPSR_PM_BIT_AARCH64 BIT_64(32) 915 #define SPSR_PPEND_BIT BIT(33) 916 #define SPSR_EXLOCK_BIT_AARCH64 BIT_64(34) 917 #define SPSR_NZCV (SPSR_V_BIT | SPSR_C_BIT | SPSR_Z_BIT | SPSR_N_BIT) 918 #define SPSR_PACM_BIT_AARCH64 BIT_64(35) 919 920 /* 921 * SPSR_EL2 922 * M=0x9 (0b1001 EL2h) 923 * M[4]=0 924 * DAIF=0xF Exceptions masked on entry. 925 * BTYPE=0 BTI not yet supported. 926 * SSBS=0 Not yet supported. 927 * IL=0 Not an illegal exception return. 928 * SS=0 Not single stepping. 929 * PAN=1 RMM shouldn't access Unprivileged memory when running in VHE mode. 930 * UAO=0 931 * DIT=0 932 * TCO=0 933 * NZCV=0 934 */ 935 #define SPSR_EL2_REALM (SPSR_M_EL2H | (0xF << SPSR_DAIF_SHIFT) | \ 936 SPSR_PAN_BIT) 937 938 #define DISABLE_ALL_EXCEPTIONS \ 939 (DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT | DAIF_DBG_BIT) 940 #define DISABLE_INTERRUPTS (DAIF_FIQ_BIT | DAIF_IRQ_BIT) 941 942 /* 943 * RMR_EL3 definitions 944 */ 945 #define RMR_EL3_RR_BIT (U(1) << 1) 946 #define RMR_EL3_AA64_BIT (U(1) << 0) 947 948 /* 949 * HI-VECTOR address for AArch32 state 950 */ 951 #define HI_VECTOR_BASE U(0xFFFF0000) 952 953 /* 954 * TCR definitions 955 */ 956 #define TCR_EL3_RES1 ((ULL(1) << 31) | (ULL(1) << 23)) 957 #define TCR_EL2_RES1 ((ULL(1) << 31) | (ULL(1) << 23)) 958 #define TCR_EL1_IPS_SHIFT U(32) 959 #define TCR_EL2_PS_SHIFT U(16) 960 #define TCR_EL3_PS_SHIFT U(16) 961 962 #define TCR_TxSZ_MIN ULL(16) 963 #define TCR_TxSZ_MAX ULL(39) 964 #define TCR_TxSZ_MAX_TTST ULL(48) 965 966 #define TCR_T0SZ_SHIFT U(0) 967 #define TCR_T1SZ_SHIFT U(16) 968 969 /* (internal) physical address size bits in EL3/EL1 */ 970 #define TCR_PS_BITS_4GB ULL(0x0) 971 #define TCR_PS_BITS_64GB ULL(0x1) 972 #define TCR_PS_BITS_1TB ULL(0x2) 973 #define TCR_PS_BITS_4TB ULL(0x3) 974 #define TCR_PS_BITS_16TB ULL(0x4) 975 #define TCR_PS_BITS_256TB ULL(0x5) 976 977 #define ADDR_MASK_48_TO_63 ULL(0xFFFF000000000000) 978 #define ADDR_MASK_44_TO_47 ULL(0x0000F00000000000) 979 #define ADDR_MASK_42_TO_43 ULL(0x00000C0000000000) 980 #define ADDR_MASK_40_TO_41 ULL(0x0000030000000000) 981 #define ADDR_MASK_36_TO_39 ULL(0x000000F000000000) 982 #define ADDR_MASK_32_TO_35 ULL(0x0000000F00000000) 983 984 #define TCR_RGN_INNER_NC (ULL(0x0) << 8) 985 #define TCR_RGN_INNER_WBA (ULL(0x1) << 8) 986 #define TCR_RGN_INNER_WT (ULL(0x2) << 8) 987 #define TCR_RGN_INNER_WBNA (ULL(0x3) << 8) 988 989 #define TCR_RGN_OUTER_NC (ULL(0x0) << 10) 990 #define TCR_RGN_OUTER_WBA (ULL(0x1) << 10) 991 #define TCR_RGN_OUTER_WT (ULL(0x2) << 10) 992 #define TCR_RGN_OUTER_WBNA (ULL(0x3) << 10) 993 994 #define TCR_SH_NON_SHAREABLE (ULL(0x0) << 12) 995 #define TCR_SH_OUTER_SHAREABLE (ULL(0x2) << 12) 996 #define TCR_SH_INNER_SHAREABLE (ULL(0x3) << 12) 997 998 #define TCR_RGN1_INNER_NC (ULL(0x0) << 24) 999 #define TCR_RGN1_INNER_WBA (ULL(0x1) << 24) 1000 #define TCR_RGN1_INNER_WT (ULL(0x2) << 24) 1001 #define TCR_RGN1_INNER_WBNA (ULL(0x3) << 24) 1002 1003 #define TCR_RGN1_OUTER_NC (ULL(0x0) << 26) 1004 #define TCR_RGN1_OUTER_WBA (ULL(0x1) << 26) 1005 #define TCR_RGN1_OUTER_WT (ULL(0x2) << 26) 1006 #define TCR_RGN1_OUTER_WBNA (ULL(0x3) << 26) 1007 1008 #define TCR_SH1_NON_SHAREABLE (ULL(0x0) << 28) 1009 #define TCR_SH1_OUTER_SHAREABLE (ULL(0x2) << 28) 1010 #define TCR_SH1_INNER_SHAREABLE (ULL(0x3) << 28) 1011 1012 #define TCR_TG0_SHIFT U(14) 1013 #define TCR_TG0_MASK ULL(3) 1014 #define TCR_TG0_4K (ULL(0) << TCR_TG0_SHIFT) 1015 #define TCR_TG0_64K (ULL(1) << TCR_TG0_SHIFT) 1016 #define TCR_TG0_16K (ULL(2) << TCR_TG0_SHIFT) 1017 1018 #define TCR_TG1_SHIFT U(30) 1019 #define TCR_TG1_MASK ULL(3) 1020 #define TCR_TG1_16K (ULL(1) << TCR_TG1_SHIFT) 1021 #define TCR_TG1_4K (ULL(2) << TCR_TG1_SHIFT) 1022 #define TCR_TG1_64K (ULL(3) << TCR_TG1_SHIFT) 1023 1024 #define TCR_EPD0_BIT (ULL(1) << 7) 1025 #define TCR_EPD1_BIT (ULL(1) << 23) 1026 1027 #define MODE_SP_SHIFT U(0x0) 1028 #define MODE_SP_MASK U(0x1) 1029 #define MODE_SP_EL0 U(0x0) 1030 #define MODE_SP_ELX U(0x1) 1031 1032 #define MODE_RW_SHIFT U(0x4) 1033 #define MODE_RW_MASK U(0x1) 1034 #define MODE_RW_64 U(0x0) 1035 #define MODE_RW_32 U(0x1) 1036 1037 #define MODE_EL_SHIFT U(0x2) 1038 #define MODE_EL_MASK U(0x3) 1039 #define MODE_EL_WIDTH U(0x2) 1040 #define MODE_EL3 U(0x3) 1041 #define MODE_EL2 U(0x2) 1042 #define MODE_EL1 U(0x1) 1043 #define MODE_EL0 U(0x0) 1044 1045 #define MODE32_SHIFT U(0) 1046 #define MODE32_MASK U(0xf) 1047 #define MODE32_usr U(0x0) 1048 #define MODE32_fiq U(0x1) 1049 #define MODE32_irq U(0x2) 1050 #define MODE32_svc U(0x3) 1051 #define MODE32_mon U(0x6) 1052 #define MODE32_abt U(0x7) 1053 #define MODE32_hyp U(0xa) 1054 #define MODE32_und U(0xb) 1055 #define MODE32_sys U(0xf) 1056 1057 #define GET_RW(mode) (((mode) >> MODE_RW_SHIFT) & MODE_RW_MASK) 1058 #define GET_EL(mode) (((mode) >> MODE_EL_SHIFT) & MODE_EL_MASK) 1059 #define GET_SP(mode) (((mode) >> MODE_SP_SHIFT) & MODE_SP_MASK) 1060 #define GET_M32(mode) (((mode) >> MODE32_SHIFT) & MODE32_MASK) 1061 1062 #define SPSR_64(el, sp, daif) \ 1063 (((MODE_RW_64 << MODE_RW_SHIFT) | \ 1064 (((el) & MODE_EL_MASK) << MODE_EL_SHIFT) | \ 1065 (((sp) & MODE_SP_MASK) << MODE_SP_SHIFT) | \ 1066 (((daif) & SPSR_DAIF_MASK) << SPSR_DAIF_SHIFT)) & \ 1067 (~(SPSR_SSBS_BIT_AARCH64))) 1068 1069 #define SPSR_MODE32(mode, isa, endian, aif) \ 1070 (((MODE_RW_32 << MODE_RW_SHIFT) | \ 1071 (((mode) & MODE32_MASK) << MODE32_SHIFT) | \ 1072 (((isa) & SPSR_T_MASK) << SPSR_T_SHIFT) | \ 1073 (((endian) & SPSR_E_MASK) << SPSR_E_SHIFT) | \ 1074 (((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT)) & \ 1075 (~(SPSR_SSBS_BIT_AARCH32))) 1076 1077 /* 1078 * TTBR Definitions 1079 */ 1080 #define TTBR_CNP_BIT ULL(0x1) 1081 1082 /* 1083 * CTR_EL0 definitions 1084 */ 1085 #define CTR_CWG_SHIFT U(24) 1086 #define CTR_CWG_MASK U(0xf) 1087 #define CTR_ERG_SHIFT U(20) 1088 #define CTR_ERG_MASK U(0xf) 1089 #define CTR_DMINLINE_SHIFT U(16) 1090 #define CTR_DMINLINE_MASK U(0xf) 1091 #define CTR_L1IP_SHIFT U(14) 1092 #define CTR_L1IP_MASK U(0x3) 1093 #define CTR_IMINLINE_SHIFT U(0) 1094 #define CTR_IMINLINE_MASK U(0xf) 1095 1096 #define MAX_CACHE_LINE_SIZE U(0x800) /* 2KB */ 1097 1098 /* Physical timer control register bit fields shifts and masks */ 1099 #define CNTP_CTL_ENABLE_SHIFT U(0) 1100 #define CNTP_CTL_IMASK_SHIFT U(1) 1101 #define CNTP_CTL_ISTATUS_SHIFT U(2) 1102 1103 #define CNTP_CTL_ENABLE_MASK U(1) 1104 #define CNTP_CTL_IMASK_MASK U(1) 1105 #define CNTP_CTL_ISTATUS_MASK U(1) 1106 1107 /* Physical timer control macros */ 1108 #define CNTP_CTL_ENABLE_BIT (U(1) << CNTP_CTL_ENABLE_SHIFT) 1109 #define CNTP_CTL_IMASK_BIT (U(1) << CNTP_CTL_IMASK_SHIFT) 1110 1111 /* Exception Syndrome register bits and bobs */ 1112 #define ESR_EC_SHIFT U(26) 1113 #define ESR_EC_MASK U(0x3f) 1114 #define ESR_EC_LENGTH U(6) 1115 #define ESR_ISS_SHIFT U(0) 1116 #define ESR_ISS_LENGTH U(25) 1117 #define ESR_IL_BIT (U(1) << 25) 1118 #define EC_UNKNOWN U(0x0) 1119 #define EC_WFE_WFI U(0x1) 1120 #define EC_AARCH32_CP15_MRC_MCR U(0x3) 1121 #define EC_AARCH32_CP15_MRRC_MCRR U(0x4) 1122 #define EC_AARCH32_CP14_MRC_MCR U(0x5) 1123 #define EC_AARCH32_CP14_LDC_STC U(0x6) 1124 #define EC_FP_SIMD U(0x7) 1125 #define EC_AARCH32_CP10_MRC U(0x8) 1126 #define EC_AARCH32_CP14_MRRC_MCRR U(0xc) 1127 #define EC_ILLEGAL U(0xe) 1128 #define EC_AARCH32_SVC U(0x11) 1129 #define EC_AARCH32_HVC U(0x12) 1130 #define EC_AARCH32_SMC U(0x13) 1131 #define EC_AARCH64_SVC U(0x15) 1132 #define EC_AARCH64_HVC U(0x16) 1133 #define EC_AARCH64_SMC U(0x17) 1134 #define EC_AARCH64_SYS U(0x18) 1135 #define EC_IMP_DEF_EL3 U(0x1f) 1136 #define EC_IABORT_LOWER_EL U(0x20) 1137 #define EC_IABORT_CUR_EL U(0x21) 1138 #define EC_PC_ALIGN U(0x22) 1139 #define EC_DABORT_LOWER_EL U(0x24) 1140 #define EC_DABORT_CUR_EL U(0x25) 1141 #define EC_SP_ALIGN U(0x26) 1142 #define EC_AARCH32_FP U(0x28) 1143 #define EC_AARCH64_FP U(0x2c) 1144 #define EC_SERROR U(0x2f) 1145 #define EC_BRK U(0x3c) 1146 1147 /* 1148 * External Abort bit in Instruction and Data Aborts synchronous exception 1149 * syndromes. 1150 */ 1151 #define ESR_ISS_EABORT_EA_BIT U(9) 1152 1153 #define EC_BITS(x) (((x) >> ESR_EC_SHIFT) & ESR_EC_MASK) 1154 1155 /* Reset bit inside the Reset management register for EL3 (RMR_EL3) */ 1156 #define RMR_RESET_REQUEST_SHIFT U(0x1) 1157 #define RMR_WARM_RESET_CPU (U(1) << RMR_RESET_REQUEST_SHIFT) 1158 1159 /******************************************************************************* 1160 * Definitions of register offsets, fields and macros for CPU system 1161 * instructions. 1162 ******************************************************************************/ 1163 1164 #define TLBI_ADDR_SHIFT U(12) 1165 #define TLBI_ADDR_MASK ULL(0x00000FFFFFFFFFFF) 1166 #define TLBI_ADDR(x) (((x) >> TLBI_ADDR_SHIFT) & TLBI_ADDR_MASK) 1167 1168 /******************************************************************************* 1169 * Definitions of register offsets and fields in the CNTCTLBase Frame of the 1170 * system level implementation of the Generic Timer. 1171 ******************************************************************************/ 1172 #define CNTCTLBASE_CNTFRQ U(0x0) 1173 #define CNTNSAR U(0x4) 1174 #define CNTNSAR_NS_SHIFT(x) (x) 1175 1176 #define CNTACR_BASE(x) (U(0x40) + ((x) << 2)) 1177 #define CNTACR_RPCT_SHIFT U(0x0) 1178 #define CNTACR_RVCT_SHIFT U(0x1) 1179 #define CNTACR_RFRQ_SHIFT U(0x2) 1180 #define CNTACR_RVOFF_SHIFT U(0x3) 1181 #define CNTACR_RWVT_SHIFT U(0x4) 1182 #define CNTACR_RWPT_SHIFT U(0x5) 1183 1184 /******************************************************************************* 1185 * Definitions of register offsets and fields in the CNTBaseN Frame of the 1186 * system level implementation of the Generic Timer. 1187 ******************************************************************************/ 1188 /* Physical Count register. */ 1189 #define CNTPCT_LO U(0x0) 1190 /* Counter Frequency register. */ 1191 #define CNTBASEN_CNTFRQ U(0x10) 1192 /* Physical Timer CompareValue register. */ 1193 #define CNTP_CVAL_LO U(0x20) 1194 /* Physical Timer Control register. */ 1195 #define CNTP_CTL U(0x2c) 1196 1197 /* PMCR_EL0 definitions */ 1198 #define PMCR_EL0_RESET_VAL U(0x0) 1199 #define PMCR_EL0_N_SHIFT U(11) 1200 #define PMCR_EL0_N_MASK U(0x1f) 1201 #define PMCR_EL0_N_BITS (PMCR_EL0_N_MASK << PMCR_EL0_N_SHIFT) 1202 #define PMCR_EL0_LP_BIT (U(1) << 7) 1203 #define PMCR_EL0_LC_BIT (U(1) << 6) 1204 #define PMCR_EL0_DP_BIT (U(1) << 5) 1205 #define PMCR_EL0_X_BIT (U(1) << 4) 1206 #define PMCR_EL0_D_BIT (U(1) << 3) 1207 #define PMCR_EL0_C_BIT (U(1) << 2) 1208 #define PMCR_EL0_P_BIT (U(1) << 1) 1209 #define PMCR_EL0_E_BIT (U(1) << 0) 1210 1211 /******************************************************************************* 1212 * Definitions for system register interface to SVE 1213 ******************************************************************************/ 1214 #define ZCR_EL3 S3_6_C1_C2_0 1215 #define ZCR_EL2 S3_4_C1_C2_0 1216 1217 /* ZCR_EL3 definitions */ 1218 #define ZCR_EL3_LEN_MASK U(0xf) 1219 1220 /* ZCR_EL2 definitions */ 1221 #define ZCR_EL2_LEN_MASK U(0xf) 1222 1223 /******************************************************************************* 1224 * Definitions for system register interface to SME as needed in EL3 1225 ******************************************************************************/ 1226 #define ID_AA64SMFR0_EL1 S3_0_C0_C4_5 1227 #define SMCR_EL3 S3_6_C1_C2_6 1228 #define SVCR S3_3_C4_C2_2 1229 1230 /* ID_AA64SMFR0_EL1 definitions */ 1231 #define ID_AA64SMFR0_EL1_SME_FA64_SHIFT U(63) 1232 #define ID_AA64SMFR0_EL1_SME_FA64_MASK U(0x1) 1233 #define SME_FA64_IMPLEMENTED U(0x1) 1234 #define ID_AA64SMFR0_EL1_SME_VER_SHIFT U(55) 1235 #define ID_AA64SMFR0_EL1_SME_VER_MASK ULL(0xf) 1236 #define SME_INST_IMPLEMENTED ULL(0x0) 1237 #define SME2_INST_IMPLEMENTED ULL(0x1) 1238 1239 /* SMCR_ELx definitions */ 1240 #define SMCR_ELX_LEN_SHIFT U(0) 1241 #define SMCR_ELX_LEN_MAX U(0x1ff) 1242 #define SMCR_ELX_FA64_BIT (U(1) << 31) 1243 #define SMCR_ELX_EZT0_BIT (U(1) << 30) 1244 1245 /******************************************************************************* 1246 * Definitions of MAIR encodings for device and normal memory 1247 ******************************************************************************/ 1248 /* 1249 * MAIR encodings for device memory attributes. 1250 */ 1251 #define MAIR_DEV_nGnRnE ULL(0x0) 1252 #define MAIR_DEV_nGnRE ULL(0x4) 1253 #define MAIR_DEV_nGRE ULL(0x8) 1254 #define MAIR_DEV_GRE ULL(0xc) 1255 1256 /* 1257 * MAIR encodings for normal memory attributes. 1258 * 1259 * Cache Policy 1260 * WT: Write Through 1261 * WB: Write Back 1262 * NC: Non-Cacheable 1263 * 1264 * Transient Hint 1265 * NTR: Non-Transient 1266 * TR: Transient 1267 * 1268 * Allocation Policy 1269 * RA: Read Allocate 1270 * WA: Write Allocate 1271 * RWA: Read and Write Allocate 1272 * NA: No Allocation 1273 */ 1274 #define MAIR_NORM_WT_TR_WA ULL(0x1) 1275 #define MAIR_NORM_WT_TR_RA ULL(0x2) 1276 #define MAIR_NORM_WT_TR_RWA ULL(0x3) 1277 #define MAIR_NORM_NC ULL(0x4) 1278 #define MAIR_NORM_WB_TR_WA ULL(0x5) 1279 #define MAIR_NORM_WB_TR_RA ULL(0x6) 1280 #define MAIR_NORM_WB_TR_RWA ULL(0x7) 1281 #define MAIR_NORM_WT_NTR_NA ULL(0x8) 1282 #define MAIR_NORM_WT_NTR_WA ULL(0x9) 1283 #define MAIR_NORM_WT_NTR_RA ULL(0xa) 1284 #define MAIR_NORM_WT_NTR_RWA ULL(0xb) 1285 #define MAIR_NORM_WB_NTR_NA ULL(0xc) 1286 #define MAIR_NORM_WB_NTR_WA ULL(0xd) 1287 #define MAIR_NORM_WB_NTR_RA ULL(0xe) 1288 #define MAIR_NORM_WB_NTR_RWA ULL(0xf) 1289 1290 #define MAIR_NORM_OUTER_SHIFT U(4) 1291 1292 #define MAKE_MAIR_NORMAL_MEMORY(inner, outer) \ 1293 ((inner) | ((outer) << MAIR_NORM_OUTER_SHIFT)) 1294 1295 /* PAR_EL1 fields */ 1296 #define PAR_F_SHIFT U(0) 1297 #define PAR_F_MASK ULL(0x1) 1298 1299 #define PAR_D128_ADDR_MASK GENMASK(55, 12) /* 44-bits-wide page address */ 1300 #define PAR_ADDR_MASK GENMASK(51, 12) /* 40-bits-wide page address */ 1301 1302 /******************************************************************************* 1303 * Definitions for system register interface to SPE 1304 ******************************************************************************/ 1305 #define PMBLIMITR_EL1 S3_0_C9_C10_0 1306 1307 /******************************************************************************* 1308 * Definitions for system register interface, shifts and masks for MPAM 1309 ******************************************************************************/ 1310 #define MPAMIDR_EL1 S3_0_C10_C4_4 1311 #define MPAM2_EL2 S3_4_C10_C5_0 1312 #define MPAMHCR_EL2 S3_4_C10_C4_0 1313 #define MPAM3_EL3 S3_6_C10_C5_0 1314 1315 #define MPAMIDR_EL1_VPMR_MAX_SHIFT ULL(18) 1316 #define MPAMIDR_EL1_VPMR_MAX_MASK ULL(0x7) 1317 /******************************************************************************* 1318 * Definitions for system register interface to AMU for FEAT_AMUv1 1319 ******************************************************************************/ 1320 #define AMCR_EL0 S3_3_C13_C2_0 1321 #define AMCFGR_EL0 S3_3_C13_C2_1 1322 #define AMCGCR_EL0 S3_3_C13_C2_2 1323 #define AMUSERENR_EL0 S3_3_C13_C2_3 1324 #define AMCNTENCLR0_EL0 S3_3_C13_C2_4 1325 #define AMCNTENSET0_EL0 S3_3_C13_C2_5 1326 #define AMCNTENCLR1_EL0 S3_3_C13_C3_0 1327 #define AMCNTENSET1_EL0 S3_3_C13_C3_1 1328 1329 /* Activity Monitor Group 0 Event Counter Registers */ 1330 #define AMEVCNTR00_EL0 S3_3_C13_C4_0 1331 #define AMEVCNTR01_EL0 S3_3_C13_C4_1 1332 #define AMEVCNTR02_EL0 S3_3_C13_C4_2 1333 #define AMEVCNTR03_EL0 S3_3_C13_C4_3 1334 1335 /* Activity Monitor Group 0 Event Type Registers */ 1336 #define AMEVTYPER00_EL0 S3_3_C13_C6_0 1337 #define AMEVTYPER01_EL0 S3_3_C13_C6_1 1338 #define AMEVTYPER02_EL0 S3_3_C13_C6_2 1339 #define AMEVTYPER03_EL0 S3_3_C13_C6_3 1340 1341 /* Activity Monitor Group 1 Event Counter Registers */ 1342 #define AMEVCNTR10_EL0 S3_3_C13_C12_0 1343 #define AMEVCNTR11_EL0 S3_3_C13_C12_1 1344 #define AMEVCNTR12_EL0 S3_3_C13_C12_2 1345 #define AMEVCNTR13_EL0 S3_3_C13_C12_3 1346 #define AMEVCNTR14_EL0 S3_3_C13_C12_4 1347 #define AMEVCNTR15_EL0 S3_3_C13_C12_5 1348 #define AMEVCNTR16_EL0 S3_3_C13_C12_6 1349 #define AMEVCNTR17_EL0 S3_3_C13_C12_7 1350 #define AMEVCNTR18_EL0 S3_3_C13_C13_0 1351 #define AMEVCNTR19_EL0 S3_3_C13_C13_1 1352 #define AMEVCNTR1A_EL0 S3_3_C13_C13_2 1353 #define AMEVCNTR1B_EL0 S3_3_C13_C13_3 1354 #define AMEVCNTR1C_EL0 S3_3_C13_C13_4 1355 #define AMEVCNTR1D_EL0 S3_3_C13_C13_5 1356 #define AMEVCNTR1E_EL0 S3_3_C13_C13_6 1357 #define AMEVCNTR1F_EL0 S3_3_C13_C13_7 1358 1359 /* Activity Monitor Group 1 Event Type Registers */ 1360 #define AMEVTYPER10_EL0 S3_3_C13_C14_0 1361 #define AMEVTYPER11_EL0 S3_3_C13_C14_1 1362 #define AMEVTYPER12_EL0 S3_3_C13_C14_2 1363 #define AMEVTYPER13_EL0 S3_3_C13_C14_3 1364 #define AMEVTYPER14_EL0 S3_3_C13_C14_4 1365 #define AMEVTYPER15_EL0 S3_3_C13_C14_5 1366 #define AMEVTYPER16_EL0 S3_3_C13_C14_6 1367 #define AMEVTYPER17_EL0 S3_3_C13_C14_7 1368 #define AMEVTYPER18_EL0 S3_3_C13_C15_0 1369 #define AMEVTYPER19_EL0 S3_3_C13_C15_1 1370 #define AMEVTYPER1A_EL0 S3_3_C13_C15_2 1371 #define AMEVTYPER1B_EL0 S3_3_C13_C15_3 1372 #define AMEVTYPER1C_EL0 S3_3_C13_C15_4 1373 #define AMEVTYPER1D_EL0 S3_3_C13_C15_5 1374 #define AMEVTYPER1E_EL0 S3_3_C13_C15_6 1375 #define AMEVTYPER1F_EL0 S3_3_C13_C15_7 1376 1377 /* AMCNTENSET0_EL0 definitions */ 1378 #define AMCNTENSET0_EL0_Pn_SHIFT U(0) 1379 #define AMCNTENSET0_EL0_Pn_MASK ULL(0xffff) 1380 1381 /* AMCNTENSET1_EL0 definitions */ 1382 #define AMCNTENSET1_EL0_Pn_SHIFT U(0) 1383 #define AMCNTENSET1_EL0_Pn_MASK ULL(0xffff) 1384 1385 /* AMCNTENCLR0_EL0 definitions */ 1386 #define AMCNTENCLR0_EL0_Pn_SHIFT U(0) 1387 #define AMCNTENCLR0_EL0_Pn_MASK ULL(0xffff) 1388 1389 /* AMCNTENCLR1_EL0 definitions */ 1390 #define AMCNTENCLR1_EL0_Pn_SHIFT U(0) 1391 #define AMCNTENCLR1_EL0_Pn_MASK ULL(0xffff) 1392 1393 /* AMCFGR_EL0 definitions */ 1394 #define AMCFGR_EL0_NCG_SHIFT U(28) 1395 #define AMCFGR_EL0_NCG_MASK U(0xf) 1396 #define AMCFGR_EL0_N_SHIFT U(0) 1397 #define AMCFGR_EL0_N_MASK U(0xff) 1398 1399 /* AMCGCR_EL0 definitions */ 1400 #define AMCGCR_EL0_CG0NC_SHIFT U(0) 1401 #define AMCGCR_EL0_CG0NC_MASK U(0xff) 1402 #define AMCGCR_EL0_CG1NC_SHIFT U(8) 1403 #define AMCGCR_EL0_CG1NC_MASK U(0xff) 1404 1405 /* MPAM register definitions */ 1406 #define MPAM3_EL3_MPAMEN_BIT (ULL(1) << 63) 1407 #define MPAM3_EL3_TRAPLOWER_BIT (ULL(1) << 62) 1408 #define MPAMHCR_EL2_TRAP_MPAMIDR_EL1 (ULL(1) << 31) 1409 #define MPAM3_EL3_RESET_VAL MPAM3_EL3_TRAPLOWER_BIT 1410 1411 #define MPAM2_EL2_TRAPMPAM0EL1 (ULL(1) << 49) 1412 #define MPAM2_EL2_TRAPMPAM1EL1 (ULL(1) << 48) 1413 1414 #define MPAMIDR_HAS_BW_CTRL_BIT (ULL(1) << 56) 1415 #define MPAMIDR_HAS_HCR_BIT (ULL(1) << 17) 1416 1417 /* MPAM_PE_BW_CTRL register definitions */ 1418 #define MPAMBW2_EL2 S3_4_C10_C5_4 1419 #define MPAMBW2_EL2_HW_SCALE_ENABLE_BIT (ULL(1) << 63) 1420 #define MPAMBW2_EL2_ENABLED_BIT (ULL(1) << 62) 1421 #define MPAMBW2_EL2_HARDLIM_BIT (ULL(1) << 61) 1422 #define MPAMBW2_EL2_NTRAP_MPAMBWIDR_EL1_BIT (ULL(1) << 52) 1423 #define MPAMBW2_EL2_NTRAP_MPAMBW0_EL1_BIT (ULL(1) << 51) 1424 #define MPAMBW2_EL2_NTRAP_MPAMBW1_EL1_BIT (ULL(1) << 50) 1425 #define MPAMBW2_EL2_NTRAP_MPAMBWSM_EL1_BIT (ULL(1) << 49) 1426 1427 #define MPAMBW3_EL3 S3_6_C10_C5_4 1428 #define MPAMBW3_EL3_HW_SCALE_ENABLE_BIT (ULL(1) << 63) 1429 #define MPAMBW3_EL3_ENABLED_BIT (ULL(1) << 62) 1430 #define MPAMBW3_EL3_HARDLIM_BIT (ULL(1) << 61) 1431 #define MPAMBW3_EL3_NTRAPLOWER_BIT (ULL(1) << 49) 1432 1433 /******************************************************************************* 1434 * Definitions for system register interface to AMU for FEAT_AMUv1p1 1435 ******************************************************************************/ 1436 1437 /* Definition for register defining which virtual offsets are implemented. */ 1438 #define AMCG1IDR_EL0 S3_3_C13_C2_6 1439 #define AMCG1IDR_CTR_MASK ULL(0xffff) 1440 #define AMCG1IDR_CTR_SHIFT U(0) 1441 #define AMCG1IDR_VOFF_MASK ULL(0xffff) 1442 #define AMCG1IDR_VOFF_SHIFT U(16) 1443 1444 /* New bit added to AMCR_EL0 */ 1445 #define AMCR_CG1RZ_SHIFT U(17) 1446 #define AMCR_CG1RZ_BIT (ULL(0x1) << AMCR_CG1RZ_SHIFT) 1447 1448 /* 1449 * Definitions for virtual offset registers for architected activity monitor 1450 * event counters. 1451 * AMEVCNTVOFF01_EL2 intentionally left undefined, as it does not exist. 1452 */ 1453 #define AMEVCNTVOFF00_EL2 S3_4_C13_C8_0 1454 #define AMEVCNTVOFF02_EL2 S3_4_C13_C8_2 1455 #define AMEVCNTVOFF03_EL2 S3_4_C13_C8_3 1456 1457 /* 1458 * Definitions for virtual offset registers for auxiliary activity monitor event 1459 * counters. 1460 */ 1461 #define AMEVCNTVOFF10_EL2 S3_4_C13_C10_0 1462 #define AMEVCNTVOFF11_EL2 S3_4_C13_C10_1 1463 #define AMEVCNTVOFF12_EL2 S3_4_C13_C10_2 1464 #define AMEVCNTVOFF13_EL2 S3_4_C13_C10_3 1465 #define AMEVCNTVOFF14_EL2 S3_4_C13_C10_4 1466 #define AMEVCNTVOFF15_EL2 S3_4_C13_C10_5 1467 #define AMEVCNTVOFF16_EL2 S3_4_C13_C10_6 1468 #define AMEVCNTVOFF17_EL2 S3_4_C13_C10_7 1469 #define AMEVCNTVOFF18_EL2 S3_4_C13_C11_0 1470 #define AMEVCNTVOFF19_EL2 S3_4_C13_C11_1 1471 #define AMEVCNTVOFF1A_EL2 S3_4_C13_C11_2 1472 #define AMEVCNTVOFF1B_EL2 S3_4_C13_C11_3 1473 #define AMEVCNTVOFF1C_EL2 S3_4_C13_C11_4 1474 #define AMEVCNTVOFF1D_EL2 S3_4_C13_C11_5 1475 #define AMEVCNTVOFF1E_EL2 S3_4_C13_C11_6 1476 #define AMEVCNTVOFF1F_EL2 S3_4_C13_C11_7 1477 1478 /******************************************************************************* 1479 * Realm management extension register definitions 1480 ******************************************************************************/ 1481 #define GPCCR_EL3 S3_6_C2_C1_6 1482 #define GPTBR_EL3 S3_6_C2_C1_4 1483 1484 #define SCXTNUM_EL2 S3_4_C13_C0_7 1485 #define SCXTNUM_EL1 S3_0_C13_C0_7 1486 #define SCXTNUM_EL0 S3_3_C13_C0_7 1487 1488 /******************************************************************************* 1489 * RAS system registers 1490 ******************************************************************************/ 1491 #define DISR_EL1 S3_0_C12_C1_1 1492 #define DISR_A_BIT U(31) 1493 1494 #define ERRIDR_EL1 S3_0_C5_C3_0 1495 #define ERRIDR_MASK U(0xffff) 1496 1497 #define ERRSELR_EL1 S3_0_C5_C3_1 1498 1499 /* System register access to Standard Error Record registers */ 1500 #define ERXFR_EL1 S3_0_C5_C4_0 1501 #define ERXCTLR_EL1 S3_0_C5_C4_1 1502 #define ERXSTATUS_EL1 S3_0_C5_C4_2 1503 #define ERXADDR_EL1 S3_0_C5_C4_3 1504 #define ERXPFGF_EL1 S3_0_C5_C4_4 1505 #define ERXPFGCTL_EL1 S3_0_C5_C4_5 1506 #define ERXPFGCDN_EL1 S3_0_C5_C4_6 1507 #define ERXMISC0_EL1 S3_0_C5_C5_0 1508 #define ERXMISC1_EL1 S3_0_C5_C5_1 1509 1510 #define ERXCTLR_ED_SHIFT U(0) 1511 #define ERXCTLR_ED_BIT (U(1) << ERXCTLR_ED_SHIFT) 1512 #define ERXCTLR_UE_BIT (U(1) << 4) 1513 1514 #define ERXPFGCTL_UC_BIT (U(1) << 1) 1515 #define ERXPFGCTL_UEU_BIT (U(1) << 2) 1516 #define ERXPFGCTL_CDEN_BIT (U(1) << 31) 1517 1518 /******************************************************************************* 1519 * Armv8.3 Pointer Authentication Registers 1520 ******************************************************************************/ 1521 #define APIAKeyLo_EL1 S3_0_C2_C1_0 1522 #define APIAKeyHi_EL1 S3_0_C2_C1_1 1523 #define APIBKeyLo_EL1 S3_0_C2_C1_2 1524 #define APIBKeyHi_EL1 S3_0_C2_C1_3 1525 #define APDAKeyLo_EL1 S3_0_C2_C2_0 1526 #define APDAKeyHi_EL1 S3_0_C2_C2_1 1527 #define APDBKeyLo_EL1 S3_0_C2_C2_2 1528 #define APDBKeyHi_EL1 S3_0_C2_C2_3 1529 #define APGAKeyLo_EL1 S3_0_C2_C3_0 1530 #define APGAKeyHi_EL1 S3_0_C2_C3_1 1531 1532 /******************************************************************************* 1533 * Armv8.4 Data Independent Timing Registers 1534 ******************************************************************************/ 1535 #define DIT S3_3_C4_C2_5 1536 #define DIT_BIT BIT(24) 1537 1538 /******************************************************************************* 1539 * Armv8.5 - new MSR encoding to directly access PSTATE.SSBS field 1540 ******************************************************************************/ 1541 #define SSBS S3_3_C4_C2_6 1542 1543 /******************************************************************************* 1544 * Armv8.5 - Memory Tagging Extension Registers 1545 ******************************************************************************/ 1546 #define TFSRE0_EL1 S3_0_C5_C6_1 1547 #define TFSR_EL1 S3_0_C5_C6_0 1548 #define RGSR_EL1 S3_0_C1_C0_5 1549 #define GCR_EL1 S3_0_C1_C0_6 1550 1551 #define GCR_EL1_RRND_BIT (UL(1) << 16) 1552 1553 /******************************************************************************* 1554 * Armv8.5 - Random Number Generator Registers 1555 ******************************************************************************/ 1556 #define RNDR S3_3_C2_C4_0 1557 #define RNDRRS S3_3_C2_C4_1 1558 1559 /******************************************************************************* 1560 * FEAT_HCX - Extended Hypervisor Configuration Register 1561 ******************************************************************************/ 1562 #define HCRX_EL2 S3_4_C1_C2_2 1563 #define HCRX_EL2_MSCEn_BIT (UL(1) << 11) 1564 #define HCRX_EL2_MCE2_BIT (UL(1) << 10) 1565 #define HCRX_EL2_CMOW_BIT (UL(1) << 9) 1566 #define HCRX_EL2_VFNMI_BIT (UL(1) << 8) 1567 #define HCRX_EL2_VINMI_BIT (UL(1) << 7) 1568 #define HCRX_EL2_TALLINT_BIT (UL(1) << 6) 1569 #define HCRX_EL2_SMPME_BIT (UL(1) << 5) 1570 #define HCRX_EL2_FGTnXS_BIT (UL(1) << 4) 1571 #define HCRX_EL2_FnXS_BIT (UL(1) << 3) 1572 #define HCRX_EL2_EnASR_BIT (UL(1) << 2) 1573 #define HCRX_EL2_EnALS_BIT (UL(1) << 1) 1574 #define HCRX_EL2_EnAS0_BIT (UL(1) << 0) 1575 #define HCRX_EL2_INIT_VAL ULL(0x0) 1576 1577 /******************************************************************************* 1578 * FEAT_FGT - Definitions for Fine-Grained Trap registers 1579 ******************************************************************************/ 1580 #define HFGITR_EL2_INIT_VAL ULL(0x180000000000000) 1581 #define HFGRTR_EL2_INIT_VAL ULL(0xC4000000000000) 1582 #define HFGWTR_EL2_INIT_VAL ULL(0xC4000000000000) 1583 1584 /******************************************************************************* 1585 * FEAT_TCR2 - Extended Translation Control Registers 1586 ******************************************************************************/ 1587 #define TCR2_EL1 S3_0_C2_C0_3 1588 #define TCR2_EL2 S3_4_C2_C0_3 1589 1590 /******************************************************************************* 1591 * Permission indirection and overlay Registers 1592 ******************************************************************************/ 1593 1594 #define PIRE0_EL1 S3_0_C10_C2_2 1595 #define PIRE0_EL2 S3_4_C10_C2_2 1596 #define PIR_EL1 S3_0_C10_C2_3 1597 #define PIR_EL2 S3_4_C10_C2_3 1598 #define POR_EL1 S3_0_C10_C2_4 1599 #define POR_EL2 S3_4_C10_C2_4 1600 #define S2PIR_EL2 S3_4_C10_C2_5 1601 #define S2POR_EL1 S3_0_C10_C2_5 1602 1603 /******************************************************************************* 1604 * FEAT_GCS - Guarded Control Stack Registers 1605 ******************************************************************************/ 1606 #define GCSCR_EL2 S3_4_C2_C5_0 1607 #define GCSPR_EL2 S3_4_C2_C5_1 1608 #define GCSCR_EL1 S3_0_C2_C5_0 1609 #define GCSCRE0_EL1 S3_0_C2_C5_2 1610 #define GCSPR_EL1 S3_0_C2_C5_1 1611 #define GCSPR_EL0 S3_3_C2_C5_1 1612 1613 #define GCSCR_EXLOCK_EN_BIT (UL(1) << 6) 1614 1615 /******************************************************************************* 1616 * FEAT_TRF - Trace Filter Control Registers 1617 ******************************************************************************/ 1618 #define TRFCR_EL2 S3_4_C1_C2_1 1619 #define TRFCR_EL1 S3_0_C1_C2_1 1620 1621 /******************************************************************************* 1622 * FEAT_THE - Translation Hardening Extension Registers 1623 ******************************************************************************/ 1624 #define RCWMASK_EL1 S3_0_C13_C0_6 1625 #define RCWSMASK_EL1 S3_0_C13_C0_3 1626 1627 /******************************************************************************* 1628 * FEAT_SCTLR2 - Extension to SCTLR_ELx Registers 1629 ******************************************************************************/ 1630 #define SCTLR2_EL3 S3_6_C1_C0_3 1631 #define SCTLR2_EL2 S3_4_C1_C0_3 1632 #define SCTLR2_EL1 S3_0_C1_C0_3 1633 1634 /******************************************************************************* 1635 * FEAT_BRBE - Branch Record Buffer Extension Registers 1636 ******************************************************************************/ 1637 #define BRBCR_EL2 S2_4_C9_C0_0 1638 1639 /******************************************************************************* 1640 * FEAT_LS64_ACCDATA - LoadStore64B with status data 1641 ******************************************************************************/ 1642 #define ACCDATA_EL1 S3_0_C13_C0_5 1643 1644 /******************************************************************************* 1645 * Definitions for DynamicIQ Shared Unit registers 1646 ******************************************************************************/ 1647 #define CLUSTERPWRDN_EL1 S3_0_C15_C3_6 1648 1649 /******************************************************************************* 1650 * FEAT_FPMR - Floating point Mode Register 1651 ******************************************************************************/ 1652 #define FPMR S3_3_C4_C4_2 1653 1654 /* CLUSTERPWRDN_EL1 register definitions */ 1655 #define DSU_CLUSTER_PWR_OFF 0 1656 #define DSU_CLUSTER_PWR_ON 1 1657 #define DSU_CLUSTER_PWR_MASK U(1) 1658 #define DSU_CLUSTER_MEM_RET BIT(1) 1659 1660 /* CLUSTERPMMDCR register definitions */ 1661 #define CLUSTERPMMDCR_SPME U(1) 1662 1663 /******************************************************************************* 1664 * Definitions for CPU Power/Performance Management registers 1665 ******************************************************************************/ 1666 1667 #define CPUPPMCR_EL3 S3_6_C15_C2_0 1668 #define CPUPPMCR_EL3_MPMMPINCTL_BIT BIT(0) 1669 1670 #define CPUMPMMCR_EL3 S3_6_C15_C2_1 1671 #define CPUMPMMCR_EL3_MPMM_EN_BIT BIT(0) 1672 1673 /* alternative system register encoding for the "sb" speculation barrier */ 1674 #define SYSREG_SB S0_3_C3_C0_7 1675 1676 #define CLUSTERPMCR_EL1 S3_0_C15_C5_0 1677 #define CLUSTERPMCNTENSET_EL1 S3_0_C15_C5_1 1678 #define CLUSTERPMCCNTR_EL1 S3_0_C15_C6_0 1679 #define CLUSTERPMOVSSET_EL1 S3_0_C15_C5_3 1680 #define CLUSTERPMOVSCLR_EL1 S3_0_C15_C5_4 1681 #define CLUSTERPMSELR_EL1 S3_0_C15_C5_5 1682 #define CLUSTERPMXEVTYPER_EL1 S3_0_C15_C6_1 1683 #define CLUSTERPMXEVCNTR_EL1 S3_0_C15_C6_2 1684 #define CLUSTERPMMDCR_EL3 S3_6_C15_C6_3 1685 1686 #define CLUSTERPMCR_E_BIT BIT(0) 1687 #define CLUSTERPMCR_N_SHIFT U(11) 1688 #define CLUSTERPMCR_N_MASK U(0x1f) 1689 1690 /******************************************************************************* 1691 * FEAT_MEC - Memory Encryption Contexts 1692 ******************************************************************************/ 1693 #define MECIDR_EL2 S3_4_C10_C8_7 1694 #define MECIDR_EL2_MECIDWidthm1_MASK U(0xf) 1695 #define MECIDR_EL2_MECIDWidthm1_SHIFT U(0) 1696 1697 /****************************************************************************** 1698 * FEAT_FGWTE3 - Fine Grained Write Trap 1699 ******************************************************************************/ 1700 #define FGWTE3_EL3 S3_6_C1_C1_5 1701 1702 /* FGWTE3_EL3 Defintions */ 1703 #define FGWTE3_EL3_VBAR_EL3_BIT (U(1) << 21) 1704 #define FGWTE3_EL3_TTBR0_EL3_BIT (U(1) << 20) 1705 #define FGWTE3_EL3_TPIDR_EL3_BIT (U(1) << 19) 1706 #define FGWTE3_EL3_TCR_EL3_BIT (U(1) << 18) 1707 #define FGWTE3_EL3_SPMROOTCR_EL3_BIT (U(1) << 17) 1708 #define FGWTE3_EL3_SCTLR2_EL3_BIT (U(1) << 16) 1709 #define FGWTE3_EL3_SCTLR_EL3_BIT (U(1) << 15) 1710 #define FGWTE3_EL3_PIR_EL3_BIT (U(1) << 14) 1711 #define FGWTE3_EL3_MECID_RL_A_EL3_BIT (U(1) << 12) 1712 #define FGWTE3_EL3_MAIR2_EL3_BIT (U(1) << 10) 1713 #define FGWTE3_EL3_MAIR_EL3_BIT (U(1) << 9) 1714 #define FGWTE3_EL3_GPTBR_EL3_BIT (U(1) << 8) 1715 #define FGWTE3_EL3_GPCCR_EL3_BIT (U(1) << 7) 1716 #define FGWTE3_EL3_GCSPR_EL3_BIT (U(1) << 6) 1717 #define FGWTE3_EL3_GCSCR_EL3_BIT (U(1) << 5) 1718 #define FGWTE3_EL3_AMAIR2_EL3_BIT (U(1) << 4) 1719 #define FGWTE3_EL3_AMAIR_EL3_BIT (U(1) << 3) 1720 #define FGWTE3_EL3_AFSR1_EL3_BIT (U(1) << 2) 1721 #define FGWTE3_EL3_AFSR0_EL3_BIT (U(1) << 1) 1722 #define FGWTE3_EL3_ACTLR_EL3_BIT (U(1) << 0) 1723 1724 #define FGWTE3_EL3_EARLY_INIT_VAL ( \ 1725 FGWTE3_EL3_VBAR_EL3_BIT | \ 1726 FGWTE3_EL3_TTBR0_EL3_BIT | \ 1727 FGWTE3_EL3_SPMROOTCR_EL3_BIT | \ 1728 FGWTE3_EL3_SCTLR2_EL3_BIT | \ 1729 FGWTE3_EL3_PIR_EL3_BIT | \ 1730 FGWTE3_EL3_MECID_RL_A_EL3_BIT | \ 1731 FGWTE3_EL3_MAIR2_EL3_BIT | \ 1732 FGWTE3_EL3_MAIR_EL3_BIT | \ 1733 FGWTE3_EL3_GPTBR_EL3_BIT | \ 1734 FGWTE3_EL3_GPCCR_EL3_BIT | \ 1735 FGWTE3_EL3_GCSPR_EL3_BIT | \ 1736 FGWTE3_EL3_GCSCR_EL3_BIT | \ 1737 FGWTE3_EL3_AMAIR2_EL3_BIT | \ 1738 FGWTE3_EL3_AMAIR_EL3_BIT | \ 1739 FGWTE3_EL3_AFSR1_EL3_BIT | \ 1740 FGWTE3_EL3_AFSR0_EL3_BIT) 1741 1742 #if HW_ASSISTED_COHERENCY 1743 #define FGWTE3_EL3_LATE_INIT_SCTLR_EL3_BIT FGWTE3_EL3_SCTLR_EL3_BIT | 1744 #else 1745 #define FGWTE3_EL3_LATE_INIT_SCTLR_EL3_BIT 1746 #endif 1747 1748 #if !(CRASH_REPORTING) 1749 #define FGWTE3_EL3_LATE_INIT_TPIDR_EL3_BIT FGWTE3_EL3_TPIDR_EL3_BIT | 1750 #else 1751 #define FGWTE3_EL3_LATE_INIT_TPIDR_EL3_BIT 1752 #endif 1753 1754 #define FGWTE3_EL3_LATE_INIT_VAL ( \ 1755 FGWTE3_EL3_EARLY_INIT_VAL | \ 1756 FGWTE3_EL3_LATE_INIT_SCTLR_EL3_BIT \ 1757 FGWTE3_EL3_LATE_INIT_TPIDR_EL3_BIT \ 1758 FGWTE3_EL3_TCR_EL3_BIT | \ 1759 FGWTE3_EL3_ACTLR_EL3_BIT) 1760 1761 #endif /* ARCH_H */ 1762