1 /* 2 * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2020-2022, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef ARCH_H 9 #define ARCH_H 10 11 #include <lib/utils_def.h> 12 13 /******************************************************************************* 14 * MIDR bit definitions 15 ******************************************************************************/ 16 #define MIDR_IMPL_MASK U(0xff) 17 #define MIDR_IMPL_SHIFT U(0x18) 18 #define MIDR_VAR_SHIFT U(20) 19 #define MIDR_VAR_BITS U(4) 20 #define MIDR_VAR_MASK U(0xf) 21 #define MIDR_REV_SHIFT U(0) 22 #define MIDR_REV_BITS U(4) 23 #define MIDR_REV_MASK U(0xf) 24 #define MIDR_PN_MASK U(0xfff) 25 #define MIDR_PN_SHIFT U(0x4) 26 27 /******************************************************************************* 28 * MPIDR macros 29 ******************************************************************************/ 30 #define MPIDR_MT_MASK (ULL(1) << 24) 31 #define MPIDR_CPU_MASK MPIDR_AFFLVL_MASK 32 #define MPIDR_CLUSTER_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS) 33 #define MPIDR_AFFINITY_BITS U(8) 34 #define MPIDR_AFFLVL_MASK ULL(0xff) 35 #define MPIDR_AFF0_SHIFT U(0) 36 #define MPIDR_AFF1_SHIFT U(8) 37 #define MPIDR_AFF2_SHIFT U(16) 38 #define MPIDR_AFF3_SHIFT U(32) 39 #define MPIDR_AFF_SHIFT(_n) MPIDR_AFF##_n##_SHIFT 40 #define MPIDR_AFFINITY_MASK ULL(0xff00ffffff) 41 #define MPIDR_AFFLVL_SHIFT U(3) 42 #define MPIDR_AFFLVL0 ULL(0x0) 43 #define MPIDR_AFFLVL1 ULL(0x1) 44 #define MPIDR_AFFLVL2 ULL(0x2) 45 #define MPIDR_AFFLVL3 ULL(0x3) 46 #define MPIDR_AFFLVL(_n) MPIDR_AFFLVL##_n 47 #define MPIDR_AFFLVL0_VAL(mpidr) \ 48 (((mpidr) >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK) 49 #define MPIDR_AFFLVL1_VAL(mpidr) \ 50 (((mpidr) >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK) 51 #define MPIDR_AFFLVL2_VAL(mpidr) \ 52 (((mpidr) >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK) 53 #define MPIDR_AFFLVL3_VAL(mpidr) \ 54 (((mpidr) >> MPIDR_AFF3_SHIFT) & MPIDR_AFFLVL_MASK) 55 /* 56 * The MPIDR_MAX_AFFLVL count starts from 0. Take care to 57 * add one while using this macro to define array sizes. 58 * TODO: Support only the first 3 affinity levels for now. 59 */ 60 #define MPIDR_MAX_AFFLVL U(2) 61 62 #define MPID_MASK (MPIDR_MT_MASK | \ 63 (MPIDR_AFFLVL_MASK << MPIDR_AFF3_SHIFT) | \ 64 (MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT) | \ 65 (MPIDR_AFFLVL_MASK << MPIDR_AFF1_SHIFT) | \ 66 (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT)) 67 68 #define MPIDR_AFF_ID(mpid, n) \ 69 (((mpid) >> MPIDR_AFF_SHIFT(n)) & MPIDR_AFFLVL_MASK) 70 71 /* 72 * An invalid MPID. This value can be used by functions that return an MPID to 73 * indicate an error. 74 */ 75 #define INVALID_MPID U(0xFFFFFFFF) 76 77 /******************************************************************************* 78 * Definitions for CPU system register interface to GICv3 79 ******************************************************************************/ 80 #define ICC_IGRPEN1_EL1 S3_0_C12_C12_7 81 #define ICC_SGI1R S3_0_C12_C11_5 82 #define ICC_ASGI1R S3_0_C12_C11_6 83 #define ICC_SRE_EL1 S3_0_C12_C12_5 84 #define ICC_SRE_EL2 S3_4_C12_C9_5 85 #define ICC_SRE_EL3 S3_6_C12_C12_5 86 #define ICC_CTLR_EL1 S3_0_C12_C12_4 87 #define ICC_CTLR_EL3 S3_6_C12_C12_4 88 #define ICC_PMR_EL1 S3_0_C4_C6_0 89 #define ICC_RPR_EL1 S3_0_C12_C11_3 90 #define ICC_IGRPEN1_EL3 S3_6_c12_c12_7 91 #define ICC_IGRPEN0_EL1 S3_0_c12_c12_6 92 #define ICC_HPPIR0_EL1 S3_0_c12_c8_2 93 #define ICC_HPPIR1_EL1 S3_0_c12_c12_2 94 #define ICC_IAR0_EL1 S3_0_c12_c8_0 95 #define ICC_IAR1_EL1 S3_0_c12_c12_0 96 #define ICC_EOIR0_EL1 S3_0_c12_c8_1 97 #define ICC_EOIR1_EL1 S3_0_c12_c12_1 98 #define ICC_SGI0R_EL1 S3_0_c12_c11_7 99 100 /******************************************************************************* 101 * Definitions for EL2 system registers for save/restore routine 102 ******************************************************************************/ 103 #define CNTPOFF_EL2 S3_4_C14_C0_6 104 #define HAFGRTR_EL2 S3_4_C3_C1_6 105 #define HDFGRTR_EL2 S3_4_C3_C1_4 106 #define HDFGWTR_EL2 S3_4_C3_C1_5 107 #define HFGITR_EL2 S3_4_C1_C1_6 108 #define HFGRTR_EL2 S3_4_C1_C1_4 109 #define HFGWTR_EL2 S3_4_C1_C1_5 110 #define ICH_HCR_EL2 S3_4_C12_C11_0 111 #define ICH_VMCR_EL2 S3_4_C12_C11_7 112 #define MPAMVPM0_EL2 S3_4_C10_C6_0 113 #define MPAMVPM1_EL2 S3_4_C10_C6_1 114 #define MPAMVPM2_EL2 S3_4_C10_C6_2 115 #define MPAMVPM3_EL2 S3_4_C10_C6_3 116 #define MPAMVPM4_EL2 S3_4_C10_C6_4 117 #define MPAMVPM5_EL2 S3_4_C10_C6_5 118 #define MPAMVPM6_EL2 S3_4_C10_C6_6 119 #define MPAMVPM7_EL2 S3_4_C10_C6_7 120 #define MPAMVPMV_EL2 S3_4_C10_C4_1 121 #define TRFCR_EL2 S3_4_C1_C2_1 122 #define PMSCR_EL2 S3_4_C9_C9_0 123 #define TFSR_EL2 S3_4_C5_C6_0 124 125 /******************************************************************************* 126 * Generic timer memory mapped registers & offsets 127 ******************************************************************************/ 128 #define CNTCR_OFF U(0x000) 129 #define CNTCV_OFF U(0x008) 130 #define CNTFID_OFF U(0x020) 131 132 #define CNTCR_EN (U(1) << 0) 133 #define CNTCR_HDBG (U(1) << 1) 134 #define CNTCR_FCREQ(x) ((x) << 8) 135 136 /******************************************************************************* 137 * System register bit definitions 138 ******************************************************************************/ 139 /* CLIDR definitions */ 140 #define LOUIS_SHIFT U(21) 141 #define LOC_SHIFT U(24) 142 #define CTYPE_SHIFT(n) U(3 * (n - 1)) 143 #define CLIDR_FIELD_WIDTH U(3) 144 145 /* CSSELR definitions */ 146 #define LEVEL_SHIFT U(1) 147 148 /* Data cache set/way op type defines */ 149 #define DCISW U(0x0) 150 #define DCCISW U(0x1) 151 #if ERRATA_A53_827319 152 #define DCCSW DCCISW 153 #else 154 #define DCCSW U(0x2) 155 #endif 156 157 /* ID_AA64PFR0_EL1 definitions */ 158 #define ID_AA64PFR0_EL0_SHIFT U(0) 159 #define ID_AA64PFR0_EL1_SHIFT U(4) 160 #define ID_AA64PFR0_EL2_SHIFT U(8) 161 #define ID_AA64PFR0_EL3_SHIFT U(12) 162 163 #define ID_AA64PFR0_AMU_SHIFT U(44) 164 #define ID_AA64PFR0_AMU_MASK ULL(0xf) 165 #define ID_AA64PFR0_AMU_NOT_SUPPORTED U(0x0) 166 #define ID_AA64PFR0_AMU_V1 ULL(0x1) 167 #define ID_AA64PFR0_AMU_V1P1 U(0x2) 168 169 #define ID_AA64PFR0_ELX_MASK ULL(0xf) 170 171 #define ID_AA64PFR0_GIC_SHIFT U(24) 172 #define ID_AA64PFR0_GIC_WIDTH U(4) 173 #define ID_AA64PFR0_GIC_MASK ULL(0xf) 174 175 #define ID_AA64PFR0_SVE_SHIFT U(32) 176 #define ID_AA64PFR0_SVE_MASK ULL(0xf) 177 #define ID_AA64PFR0_SVE_SUPPORTED ULL(0x1) 178 #define ID_AA64PFR0_SVE_LENGTH U(4) 179 180 #define ID_AA64PFR0_SEL2_SHIFT U(36) 181 #define ID_AA64PFR0_SEL2_MASK ULL(0xf) 182 183 #define ID_AA64PFR0_MPAM_SHIFT U(40) 184 #define ID_AA64PFR0_MPAM_MASK ULL(0xf) 185 186 #define ID_AA64PFR0_DIT_SHIFT U(48) 187 #define ID_AA64PFR0_DIT_MASK ULL(0xf) 188 #define ID_AA64PFR0_DIT_LENGTH U(4) 189 #define ID_AA64PFR0_DIT_SUPPORTED U(1) 190 191 #define ID_AA64PFR0_CSV2_SHIFT U(56) 192 #define ID_AA64PFR0_CSV2_MASK ULL(0xf) 193 #define ID_AA64PFR0_CSV2_LENGTH U(4) 194 #define ID_AA64PFR0_CSV2_2_SUPPORTED ULL(0x2) 195 196 #define ID_AA64PFR0_FEAT_RME_SHIFT U(52) 197 #define ID_AA64PFR0_FEAT_RME_MASK ULL(0xf) 198 #define ID_AA64PFR0_FEAT_RME_LENGTH U(4) 199 #define ID_AA64PFR0_FEAT_RME_NOT_SUPPORTED U(0) 200 #define ID_AA64PFR0_FEAT_RME_V1 U(1) 201 202 #define ID_AA64PFR0_RAS_SHIFT U(28) 203 #define ID_AA64PFR0_RAS_MASK ULL(0xf) 204 #define ID_AA64PFR0_RAS_NOT_SUPPORTED ULL(0x0) 205 #define ID_AA64PFR0_RAS_LENGTH U(4) 206 207 /* Exception level handling */ 208 #define EL_IMPL_NONE ULL(0) 209 #define EL_IMPL_A64ONLY ULL(1) 210 #define EL_IMPL_A64_A32 ULL(2) 211 212 /* ID_AA64DFR0_EL1.TraceVer definitions */ 213 #define ID_AA64DFR0_TRACEVER_SHIFT U(4) 214 #define ID_AA64DFR0_TRACEVER_MASK ULL(0xf) 215 #define ID_AA64DFR0_TRACEVER_SUPPORTED ULL(1) 216 #define ID_AA64DFR0_TRACEVER_LENGTH U(4) 217 #define ID_AA64DFR0_TRACEFILT_SHIFT U(40) 218 #define ID_AA64DFR0_TRACEFILT_MASK U(0xf) 219 #define ID_AA64DFR0_TRACEFILT_SUPPORTED U(1) 220 #define ID_AA64DFR0_TRACEFILT_LENGTH U(4) 221 222 /* ID_AA64DFR0_EL1.PMS definitions (for ARMv8.2+) */ 223 #define ID_AA64DFR0_PMS_SHIFT U(32) 224 #define ID_AA64DFR0_PMS_MASK ULL(0xf) 225 #define ID_AA64DFR0_SPE_SUPPORTED ULL(0x1) 226 #define ID_AA64DFR0_SPE_NOT_SUPPORTED ULL(0x0) 227 228 /* ID_AA64DFR0_EL1.TraceBuffer definitions */ 229 #define ID_AA64DFR0_TRACEBUFFER_SHIFT U(44) 230 #define ID_AA64DFR0_TRACEBUFFER_MASK ULL(0xf) 231 #define ID_AA64DFR0_TRACEBUFFER_SUPPORTED ULL(1) 232 233 /* ID_AA64DFR0_EL1.MTPMU definitions (for ARMv8.6+) */ 234 #define ID_AA64DFR0_MTPMU_SHIFT U(48) 235 #define ID_AA64DFR0_MTPMU_MASK ULL(0xf) 236 #define ID_AA64DFR0_MTPMU_SUPPORTED ULL(1) 237 238 /* ID_AA64DFR0_EL1.BRBE definitions */ 239 #define ID_AA64DFR0_BRBE_SHIFT U(52) 240 #define ID_AA64DFR0_BRBE_MASK ULL(0xf) 241 #define ID_AA64DFR0_BRBE_SUPPORTED ULL(1) 242 243 /* ID_AA64ISAR0_EL1 definitions */ 244 #define ID_AA64ISAR0_RNDR_SHIFT U(60) 245 #define ID_AA64ISAR0_RNDR_MASK ULL(0xf) 246 247 /* ID_AA64ISAR1_EL1 definitions */ 248 #define ID_AA64ISAR1_EL1 S3_0_C0_C6_1 249 250 #define ID_AA64ISAR1_GPI_SHIFT U(28) 251 #define ID_AA64ISAR1_GPI_MASK ULL(0xf) 252 #define ID_AA64ISAR1_GPA_SHIFT U(24) 253 #define ID_AA64ISAR1_GPA_MASK ULL(0xf) 254 255 #define ID_AA64ISAR1_API_SHIFT U(8) 256 #define ID_AA64ISAR1_API_MASK ULL(0xf) 257 #define ID_AA64ISAR1_APA_SHIFT U(4) 258 #define ID_AA64ISAR1_APA_MASK ULL(0xf) 259 260 #define ID_AA64ISAR1_SB_SHIFT U(36) 261 #define ID_AA64ISAR1_SB_MASK ULL(0xf) 262 #define ID_AA64ISAR1_SB_SUPPORTED ULL(0x1) 263 #define ID_AA64ISAR1_SB_NOT_SUPPORTED ULL(0x0) 264 265 /* ID_AA64ISAR2_EL1 definitions */ 266 #define ID_AA64ISAR2_EL1 S3_0_C0_C6_2 267 268 #define ID_AA64ISAR2_GPA3_SHIFT U(8) 269 #define ID_AA64ISAR2_GPA3_MASK ULL(0xf) 270 271 #define ID_AA64ISAR2_APA3_SHIFT U(12) 272 #define ID_AA64ISAR2_APA3_MASK ULL(0xf) 273 274 /* ID_AA64MMFR0_EL1 definitions */ 275 #define ID_AA64MMFR0_EL1_PARANGE_SHIFT U(0) 276 #define ID_AA64MMFR0_EL1_PARANGE_MASK ULL(0xf) 277 278 #define PARANGE_0000 U(32) 279 #define PARANGE_0001 U(36) 280 #define PARANGE_0010 U(40) 281 #define PARANGE_0011 U(42) 282 #define PARANGE_0100 U(44) 283 #define PARANGE_0101 U(48) 284 #define PARANGE_0110 U(52) 285 286 #define ID_AA64MMFR0_EL1_ECV_SHIFT U(60) 287 #define ID_AA64MMFR0_EL1_ECV_MASK ULL(0xf) 288 #define ID_AA64MMFR0_EL1_ECV_NOT_SUPPORTED ULL(0x0) 289 #define ID_AA64MMFR0_EL1_ECV_SUPPORTED ULL(0x1) 290 #define ID_AA64MMFR0_EL1_ECV_SELF_SYNCH ULL(0x2) 291 292 #define ID_AA64MMFR0_EL1_FGT_SHIFT U(56) 293 #define ID_AA64MMFR0_EL1_FGT_MASK ULL(0xf) 294 #define ID_AA64MMFR0_EL1_FGT_SUPPORTED ULL(0x1) 295 #define ID_AA64MMFR0_EL1_FGT_NOT_SUPPORTED ULL(0x0) 296 297 #define ID_AA64MMFR0_EL1_TGRAN4_SHIFT U(28) 298 #define ID_AA64MMFR0_EL1_TGRAN4_MASK ULL(0xf) 299 #define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED ULL(0x0) 300 #define ID_AA64MMFR0_EL1_TGRAN4_NOT_SUPPORTED ULL(0xf) 301 302 #define ID_AA64MMFR0_EL1_TGRAN64_SHIFT U(24) 303 #define ID_AA64MMFR0_EL1_TGRAN64_MASK ULL(0xf) 304 #define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED ULL(0x0) 305 #define ID_AA64MMFR0_EL1_TGRAN64_NOT_SUPPORTED ULL(0xf) 306 307 #define ID_AA64MMFR0_EL1_TGRAN16_SHIFT U(20) 308 #define ID_AA64MMFR0_EL1_TGRAN16_MASK ULL(0xf) 309 #define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED ULL(0x1) 310 #define ID_AA64MMFR0_EL1_TGRAN16_NOT_SUPPORTED ULL(0x0) 311 312 /* ID_AA64MMFR1_EL1 definitions */ 313 #define ID_AA64MMFR1_EL1_TWED_SHIFT U(32) 314 #define ID_AA64MMFR1_EL1_TWED_MASK ULL(0xf) 315 #define ID_AA64MMFR1_EL1_TWED_SUPPORTED ULL(0x1) 316 #define ID_AA64MMFR1_EL1_TWED_NOT_SUPPORTED ULL(0x0) 317 318 #define ID_AA64MMFR1_EL1_PAN_SHIFT U(20) 319 #define ID_AA64MMFR1_EL1_PAN_MASK ULL(0xf) 320 #define ID_AA64MMFR1_EL1_PAN_NOT_SUPPORTED ULL(0x0) 321 #define ID_AA64MMFR1_EL1_PAN_SUPPORTED ULL(0x1) 322 #define ID_AA64MMFR1_EL1_PAN2_SUPPORTED ULL(0x2) 323 #define ID_AA64MMFR1_EL1_PAN3_SUPPORTED ULL(0x3) 324 325 #define ID_AA64MMFR1_EL1_VHE_SHIFT U(8) 326 #define ID_AA64MMFR1_EL1_VHE_MASK ULL(0xf) 327 328 #define ID_AA64MMFR1_EL1_HCX_SHIFT U(40) 329 #define ID_AA64MMFR1_EL1_HCX_MASK ULL(0xf) 330 #define ID_AA64MMFR1_EL1_HCX_SUPPORTED ULL(0x1) 331 #define ID_AA64MMFR1_EL1_HCX_NOT_SUPPORTED ULL(0x0) 332 333 /* ID_AA64MMFR2_EL1 definitions */ 334 #define ID_AA64MMFR2_EL1 S3_0_C0_C7_2 335 336 #define ID_AA64MMFR2_EL1_ST_SHIFT U(28) 337 #define ID_AA64MMFR2_EL1_ST_MASK ULL(0xf) 338 339 #define ID_AA64MMFR2_EL1_CCIDX_SHIFT U(20) 340 #define ID_AA64MMFR2_EL1_CCIDX_MASK ULL(0xf) 341 #define ID_AA64MMFR2_EL1_CCIDX_LENGTH U(4) 342 343 #define ID_AA64MMFR2_EL1_CNP_SHIFT U(0) 344 #define ID_AA64MMFR2_EL1_CNP_MASK ULL(0xf) 345 346 #define ID_AA64MMFR2_EL1_NV_SHIFT U(24) 347 #define ID_AA64MMFR2_EL1_NV_MASK ULL(0xf) 348 #define ID_AA64MMFR2_EL1_NV_NOT_SUPPORTED ULL(0x0) 349 #define ID_AA64MMFR2_EL1_NV_SUPPORTED ULL(0x1) 350 #define ID_AA64MMFR2_EL1_NV2_SUPPORTED ULL(0x2) 351 352 /* ID_AA64MMFR3_EL1 definitions */ 353 #define ID_AA64MMFR3_EL1 S3_0_C0_C7_3 354 355 #define ID_AA64MMFR3_EL1_TCRX_SHIFT U(0) 356 #define ID_AA64MMFR3_EL1_TCRX_MASK ULL(0xf) 357 358 /* ID_AA64PFR1_EL1 definitions */ 359 #define ID_AA64PFR1_EL1_SSBS_SHIFT U(4) 360 #define ID_AA64PFR1_EL1_SSBS_MASK ULL(0xf) 361 362 #define SSBS_UNAVAILABLE ULL(0) /* No architectural SSBS support */ 363 364 #define ID_AA64PFR1_EL1_BT_SHIFT U(0) 365 #define ID_AA64PFR1_EL1_BT_MASK ULL(0xf) 366 367 #define BTI_IMPLEMENTED ULL(1) /* The BTI mechanism is implemented */ 368 369 #define ID_AA64PFR1_EL1_MTE_SHIFT U(8) 370 #define ID_AA64PFR1_EL1_MTE_MASK ULL(0xf) 371 372 #define ID_AA64PFR1_EL1_RNDR_TRAP_SHIFT U(28) 373 #define ID_AA64PFR1_EL1_RNDR_TRAP_MASK U(0xf) 374 375 #define ID_AA64PFR1_EL1_RNG_TRAP_SUPPORTED ULL(0x1) 376 #define ID_AA64PFR1_EL1_RNG_TRAP_NOT_SUPPORTED ULL(0x0) 377 378 /* Memory Tagging Extension is not implemented */ 379 #define MTE_UNIMPLEMENTED U(0) 380 /* FEAT_MTE: MTE instructions accessible at EL0 are implemented */ 381 #define MTE_IMPLEMENTED_EL0 U(1) 382 /* FEAT_MTE2: Full MTE is implemented */ 383 #define MTE_IMPLEMENTED_ELX U(2) 384 /* 385 * FEAT_MTE3: MTE is implemented with support for 386 * asymmetric Tag Check Fault handling 387 */ 388 #define MTE_IMPLEMENTED_ASY U(3) 389 390 #define ID_AA64PFR1_MPAM_FRAC_SHIFT ULL(16) 391 #define ID_AA64PFR1_MPAM_FRAC_MASK ULL(0xf) 392 393 #define ID_AA64PFR1_EL1_SME_SHIFT U(24) 394 #define ID_AA64PFR1_EL1_SME_MASK ULL(0xf) 395 396 /* ID_PFR1_EL1 definitions */ 397 #define ID_PFR1_VIRTEXT_SHIFT U(12) 398 #define ID_PFR1_VIRTEXT_MASK U(0xf) 399 #define GET_VIRT_EXT(id) (((id) >> ID_PFR1_VIRTEXT_SHIFT) \ 400 & ID_PFR1_VIRTEXT_MASK) 401 402 /* SCTLR definitions */ 403 #define SCTLR_EL2_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ 404 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \ 405 (U(1) << 11) | (U(1) << 5) | (U(1) << 4)) 406 407 #define SCTLR_EL1_RES1 ((UL(1) << 29) | (UL(1) << 28) | (UL(1) << 23) | \ 408 (UL(1) << 22) | (UL(1) << 20) | (UL(1) << 11)) 409 410 #define SCTLR_AARCH32_EL1_RES1 \ 411 ((U(1) << 23) | (U(1) << 22) | (U(1) << 11) | \ 412 (U(1) << 4) | (U(1) << 3)) 413 414 #define SCTLR_EL3_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ 415 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \ 416 (U(1) << 11) | (U(1) << 5) | (U(1) << 4)) 417 418 #define SCTLR_M_BIT (ULL(1) << 0) 419 #define SCTLR_A_BIT (ULL(1) << 1) 420 #define SCTLR_C_BIT (ULL(1) << 2) 421 #define SCTLR_SA_BIT (ULL(1) << 3) 422 #define SCTLR_SA0_BIT (ULL(1) << 4) 423 #define SCTLR_CP15BEN_BIT (ULL(1) << 5) 424 #define SCTLR_nAA_BIT (ULL(1) << 6) 425 #define SCTLR_ITD_BIT (ULL(1) << 7) 426 #define SCTLR_SED_BIT (ULL(1) << 8) 427 #define SCTLR_UMA_BIT (ULL(1) << 9) 428 #define SCTLR_EnRCTX_BIT (ULL(1) << 10) 429 #define SCTLR_EOS_BIT (ULL(1) << 11) 430 #define SCTLR_I_BIT (ULL(1) << 12) 431 #define SCTLR_EnDB_BIT (ULL(1) << 13) 432 #define SCTLR_DZE_BIT (ULL(1) << 14) 433 #define SCTLR_UCT_BIT (ULL(1) << 15) 434 #define SCTLR_NTWI_BIT (ULL(1) << 16) 435 #define SCTLR_NTWE_BIT (ULL(1) << 18) 436 #define SCTLR_WXN_BIT (ULL(1) << 19) 437 #define SCTLR_TSCXT_BIT (ULL(1) << 20) 438 #define SCTLR_IESB_BIT (ULL(1) << 21) 439 #define SCTLR_EIS_BIT (ULL(1) << 22) 440 #define SCTLR_SPAN_BIT (ULL(1) << 23) 441 #define SCTLR_E0E_BIT (ULL(1) << 24) 442 #define SCTLR_EE_BIT (ULL(1) << 25) 443 #define SCTLR_UCI_BIT (ULL(1) << 26) 444 #define SCTLR_EnDA_BIT (ULL(1) << 27) 445 #define SCTLR_nTLSMD_BIT (ULL(1) << 28) 446 #define SCTLR_LSMAOE_BIT (ULL(1) << 29) 447 #define SCTLR_EnIB_BIT (ULL(1) << 30) 448 #define SCTLR_EnIA_BIT (ULL(1) << 31) 449 #define SCTLR_BT0_BIT (ULL(1) << 35) 450 #define SCTLR_BT1_BIT (ULL(1) << 36) 451 #define SCTLR_BT_BIT (ULL(1) << 36) 452 #define SCTLR_ITFSB_BIT (ULL(1) << 37) 453 #define SCTLR_TCF0_SHIFT U(38) 454 #define SCTLR_TCF0_MASK ULL(3) 455 #define SCTLR_ENTP2_BIT (ULL(1) << 60) 456 457 /* Tag Check Faults in EL0 have no effect on the PE */ 458 #define SCTLR_TCF0_NO_EFFECT U(0) 459 /* Tag Check Faults in EL0 cause a synchronous exception */ 460 #define SCTLR_TCF0_SYNC U(1) 461 /* Tag Check Faults in EL0 are asynchronously accumulated */ 462 #define SCTLR_TCF0_ASYNC U(2) 463 /* 464 * Tag Check Faults in EL0 cause a synchronous exception on reads, 465 * and are asynchronously accumulated on writes 466 */ 467 #define SCTLR_TCF0_SYNCR_ASYNCW U(3) 468 469 #define SCTLR_TCF_SHIFT U(40) 470 #define SCTLR_TCF_MASK ULL(3) 471 472 /* Tag Check Faults in EL1 have no effect on the PE */ 473 #define SCTLR_TCF_NO_EFFECT U(0) 474 /* Tag Check Faults in EL1 cause a synchronous exception */ 475 #define SCTLR_TCF_SYNC U(1) 476 /* Tag Check Faults in EL1 are asynchronously accumulated */ 477 #define SCTLR_TCF_ASYNC U(2) 478 /* 479 * Tag Check Faults in EL1 cause a synchronous exception on reads, 480 * and are asynchronously accumulated on writes 481 */ 482 #define SCTLR_TCF_SYNCR_ASYNCW U(3) 483 484 #define SCTLR_ATA0_BIT (ULL(1) << 42) 485 #define SCTLR_ATA_BIT (ULL(1) << 43) 486 #define SCTLR_DSSBS_SHIFT U(44) 487 #define SCTLR_DSSBS_BIT (ULL(1) << SCTLR_DSSBS_SHIFT) 488 #define SCTLR_TWEDEn_BIT (ULL(1) << 45) 489 #define SCTLR_TWEDEL_SHIFT U(46) 490 #define SCTLR_TWEDEL_MASK ULL(0xf) 491 #define SCTLR_EnASR_BIT (ULL(1) << 54) 492 #define SCTLR_EnAS0_BIT (ULL(1) << 55) 493 #define SCTLR_EnALS_BIT (ULL(1) << 56) 494 #define SCTLR_EPAN_BIT (ULL(1) << 57) 495 #define SCTLR_RESET_VAL SCTLR_EL3_RES1 496 497 /* CPACR_EL1 definitions */ 498 #define CPACR_EL1_FPEN(x) ((x) << 20) 499 #define CPACR_EL1_FP_TRAP_EL0 UL(0x1) 500 #define CPACR_EL1_FP_TRAP_ALL UL(0x2) 501 #define CPACR_EL1_FP_TRAP_NONE UL(0x3) 502 503 /* SCR definitions */ 504 #define SCR_RES1_BITS ((U(1) << 4) | (U(1) << 5)) 505 #define SCR_NSE_SHIFT U(62) 506 #define SCR_NSE_BIT (ULL(1) << SCR_NSE_SHIFT) 507 #define SCR_GPF_BIT (UL(1) << 48) 508 #define SCR_TWEDEL_SHIFT U(30) 509 #define SCR_TWEDEL_MASK ULL(0xf) 510 #define SCR_TCR2EN_BIT (UL(1) << 43) 511 #define SCR_TRNDR_BIT (UL(1) << 40) 512 #define SCR_HXEn_BIT (UL(1) << 38) 513 #define SCR_ENTP2_SHIFT U(41) 514 #define SCR_ENTP2_BIT (UL(1) << SCR_ENTP2_SHIFT) 515 #define SCR_AMVOFFEN_SHIFT U(35) 516 #define SCR_AMVOFFEN_BIT (UL(1) << SCR_AMVOFFEN_SHIFT) 517 #define SCR_TWEDEn_BIT (UL(1) << 29) 518 #define SCR_ECVEN_BIT (UL(1) << 28) 519 #define SCR_FGTEN_BIT (UL(1) << 27) 520 #define SCR_ATA_BIT (UL(1) << 26) 521 #define SCR_EnSCXT_BIT (UL(1) << 25) 522 #define SCR_FIEN_BIT (UL(1) << 21) 523 #define SCR_EEL2_BIT (UL(1) << 18) 524 #define SCR_API_BIT (UL(1) << 17) 525 #define SCR_APK_BIT (UL(1) << 16) 526 #define SCR_TERR_BIT (UL(1) << 15) 527 #define SCR_TWE_BIT (UL(1) << 13) 528 #define SCR_TWI_BIT (UL(1) << 12) 529 #define SCR_ST_BIT (UL(1) << 11) 530 #define SCR_RW_BIT (UL(1) << 10) 531 #define SCR_SIF_BIT (UL(1) << 9) 532 #define SCR_HCE_BIT (UL(1) << 8) 533 #define SCR_SMD_BIT (UL(1) << 7) 534 #define SCR_EA_BIT (UL(1) << 3) 535 #define SCR_FIQ_BIT (UL(1) << 2) 536 #define SCR_IRQ_BIT (UL(1) << 1) 537 #define SCR_NS_BIT (UL(1) << 0) 538 #define SCR_VALID_BIT_MASK U(0x24000002F8F) 539 #define SCR_RESET_VAL SCR_RES1_BITS 540 541 /* MDCR_EL3 definitions */ 542 #define MDCR_EnPMSN_BIT (ULL(1) << 36) 543 #define MDCR_MPMX_BIT (ULL(1) << 35) 544 #define MDCR_MCCD_BIT (ULL(1) << 34) 545 #define MDCR_SBRBE_SHIFT U(32) 546 #define MDCR_SBRBE_MASK ULL(0x3) 547 #define MDCR_NSTB(x) ((x) << 24) 548 #define MDCR_NSTB_EL1 ULL(0x3) 549 #define MDCR_NSTBE (ULL(1) << 26) 550 #define MDCR_MTPME_BIT (ULL(1) << 28) 551 #define MDCR_TDCC_BIT (ULL(1) << 27) 552 #define MDCR_SCCD_BIT (ULL(1) << 23) 553 #define MDCR_EPMAD_BIT (ULL(1) << 21) 554 #define MDCR_EDAD_BIT (ULL(1) << 20) 555 #define MDCR_TTRF_BIT (ULL(1) << 19) 556 #define MDCR_STE_BIT (ULL(1) << 18) 557 #define MDCR_SPME_BIT (ULL(1) << 17) 558 #define MDCR_SDD_BIT (ULL(1) << 16) 559 #define MDCR_SPD32(x) ((x) << 14) 560 #define MDCR_SPD32_LEGACY ULL(0x0) 561 #define MDCR_SPD32_DISABLE ULL(0x2) 562 #define MDCR_SPD32_ENABLE ULL(0x3) 563 #define MDCR_NSPB(x) ((x) << 12) 564 #define MDCR_NSPB_EL1 ULL(0x3) 565 #define MDCR_TDOSA_BIT (ULL(1) << 10) 566 #define MDCR_TDA_BIT (ULL(1) << 9) 567 #define MDCR_TPM_BIT (ULL(1) << 6) 568 #define MDCR_EL3_RESET_VAL ULL(0x0) 569 570 /* MDCR_EL2 definitions */ 571 #define MDCR_EL2_MTPME (U(1) << 28) 572 #define MDCR_EL2_HLP (U(1) << 26) 573 #define MDCR_EL2_E2TB(x) ((x) << 24) 574 #define MDCR_EL2_E2TB_EL1 U(0x3) 575 #define MDCR_EL2_HCCD (U(1) << 23) 576 #define MDCR_EL2_TTRF (U(1) << 19) 577 #define MDCR_EL2_HPMD (U(1) << 17) 578 #define MDCR_EL2_TPMS (U(1) << 14) 579 #define MDCR_EL2_E2PB(x) ((x) << 12) 580 #define MDCR_EL2_E2PB_EL1 U(0x3) 581 #define MDCR_EL2_TDRA_BIT (U(1) << 11) 582 #define MDCR_EL2_TDOSA_BIT (U(1) << 10) 583 #define MDCR_EL2_TDA_BIT (U(1) << 9) 584 #define MDCR_EL2_TDE_BIT (U(1) << 8) 585 #define MDCR_EL2_HPME_BIT (U(1) << 7) 586 #define MDCR_EL2_TPM_BIT (U(1) << 6) 587 #define MDCR_EL2_TPMCR_BIT (U(1) << 5) 588 #define MDCR_EL2_RESET_VAL U(0x0) 589 590 /* HSTR_EL2 definitions */ 591 #define HSTR_EL2_RESET_VAL U(0x0) 592 #define HSTR_EL2_T_MASK U(0xff) 593 594 /* CNTHP_CTL_EL2 definitions */ 595 #define CNTHP_CTL_ENABLE_BIT (U(1) << 0) 596 #define CNTHP_CTL_RESET_VAL U(0x0) 597 598 /* VTTBR_EL2 definitions */ 599 #define VTTBR_RESET_VAL ULL(0x0) 600 #define VTTBR_VMID_MASK ULL(0xff) 601 #define VTTBR_VMID_SHIFT U(48) 602 #define VTTBR_BADDR_MASK ULL(0xffffffffffff) 603 #define VTTBR_BADDR_SHIFT U(0) 604 605 /* HCR definitions */ 606 #define HCR_RESET_VAL ULL(0x0) 607 #define HCR_AMVOFFEN_SHIFT U(51) 608 #define HCR_AMVOFFEN_BIT (ULL(1) << HCR_AMVOFFEN_SHIFT) 609 #define HCR_TEA_BIT (ULL(1) << 47) 610 #define HCR_API_BIT (ULL(1) << 41) 611 #define HCR_APK_BIT (ULL(1) << 40) 612 #define HCR_E2H_BIT (ULL(1) << 34) 613 #define HCR_HCD_BIT (ULL(1) << 29) 614 #define HCR_TGE_BIT (ULL(1) << 27) 615 #define HCR_RW_SHIFT U(31) 616 #define HCR_RW_BIT (ULL(1) << HCR_RW_SHIFT) 617 #define HCR_TWE_BIT (ULL(1) << 14) 618 #define HCR_TWI_BIT (ULL(1) << 13) 619 #define HCR_AMO_BIT (ULL(1) << 5) 620 #define HCR_IMO_BIT (ULL(1) << 4) 621 #define HCR_FMO_BIT (ULL(1) << 3) 622 623 /* ISR definitions */ 624 #define ISR_A_SHIFT U(8) 625 #define ISR_I_SHIFT U(7) 626 #define ISR_F_SHIFT U(6) 627 628 /* CNTHCTL_EL2 definitions */ 629 #define CNTHCTL_RESET_VAL U(0x0) 630 #define EVNTEN_BIT (U(1) << 2) 631 #define EL1PCEN_BIT (U(1) << 1) 632 #define EL1PCTEN_BIT (U(1) << 0) 633 634 /* CNTKCTL_EL1 definitions */ 635 #define EL0PTEN_BIT (U(1) << 9) 636 #define EL0VTEN_BIT (U(1) << 8) 637 #define EL0PCTEN_BIT (U(1) << 0) 638 #define EL0VCTEN_BIT (U(1) << 1) 639 #define EVNTEN_BIT (U(1) << 2) 640 #define EVNTDIR_BIT (U(1) << 3) 641 #define EVNTI_SHIFT U(4) 642 #define EVNTI_MASK U(0xf) 643 644 /* CPTR_EL3 definitions */ 645 #define TCPAC_BIT (U(1) << 31) 646 #define TAM_SHIFT U(30) 647 #define TAM_BIT (U(1) << TAM_SHIFT) 648 #define TTA_BIT (U(1) << 20) 649 #define ESM_BIT (U(1) << 12) 650 #define TFP_BIT (U(1) << 10) 651 #define CPTR_EZ_BIT (U(1) << 8) 652 #define CPTR_EL3_RESET_VAL ((TCPAC_BIT | TAM_BIT | TTA_BIT | TFP_BIT) & \ 653 ~(CPTR_EZ_BIT | ESM_BIT)) 654 655 /* CPTR_EL2 definitions */ 656 #define CPTR_EL2_RES1 ((U(1) << 13) | (U(1) << 12) | (U(0x3ff))) 657 #define CPTR_EL2_TCPAC_BIT (U(1) << 31) 658 #define CPTR_EL2_TAM_SHIFT U(30) 659 #define CPTR_EL2_TAM_BIT (U(1) << CPTR_EL2_TAM_SHIFT) 660 #define CPTR_EL2_SMEN_MASK ULL(0x3) 661 #define CPTR_EL2_SMEN_SHIFT U(24) 662 #define CPTR_EL2_TTA_BIT (U(1) << 20) 663 #define CPTR_EL2_TSM_BIT (U(1) << 12) 664 #define CPTR_EL2_TFP_BIT (U(1) << 10) 665 #define CPTR_EL2_TZ_BIT (U(1) << 8) 666 #define CPTR_EL2_RESET_VAL CPTR_EL2_RES1 667 668 /* VTCR_EL2 definitions */ 669 #define VTCR_RESET_VAL U(0x0) 670 #define VTCR_EL2_MSA (U(1) << 31) 671 672 /* CPSR/SPSR definitions */ 673 #define DAIF_FIQ_BIT (U(1) << 0) 674 #define DAIF_IRQ_BIT (U(1) << 1) 675 #define DAIF_ABT_BIT (U(1) << 2) 676 #define DAIF_DBG_BIT (U(1) << 3) 677 #define SPSR_DAIF_SHIFT U(6) 678 #define SPSR_DAIF_MASK U(0xf) 679 680 #define SPSR_AIF_SHIFT U(6) 681 #define SPSR_AIF_MASK U(0x7) 682 683 #define SPSR_E_SHIFT U(9) 684 #define SPSR_E_MASK U(0x1) 685 #define SPSR_E_LITTLE U(0x0) 686 #define SPSR_E_BIG U(0x1) 687 688 #define SPSR_T_SHIFT U(5) 689 #define SPSR_T_MASK U(0x1) 690 #define SPSR_T_ARM U(0x0) 691 #define SPSR_T_THUMB U(0x1) 692 693 #define SPSR_M_SHIFT U(4) 694 #define SPSR_M_MASK U(0x1) 695 #define SPSR_M_AARCH64 U(0x0) 696 #define SPSR_M_AARCH32 U(0x1) 697 #define SPSR_M_EL2H U(0x9) 698 699 #define SPSR_EL_SHIFT U(2) 700 #define SPSR_EL_WIDTH U(2) 701 702 #define SPSR_SSBS_SHIFT_AARCH64 U(12) 703 #define SPSR_SSBS_BIT_AARCH64 (ULL(1) << SPSR_SSBS_SHIFT_AARCH64) 704 #define SPSR_SSBS_SHIFT_AARCH32 U(23) 705 #define SPSR_SSBS_BIT_AARCH32 (ULL(1) << SPSR_SSBS_SHIFT_AARCH32) 706 707 #define SPSR_PAN_BIT BIT_64(22) 708 709 #define SPSR_DIT_BIT BIT(24) 710 711 #define SPSR_TCO_BIT_AARCH64 BIT_64(25) 712 713 #define DISABLE_ALL_EXCEPTIONS \ 714 (DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT | DAIF_DBG_BIT) 715 716 #define DISABLE_INTERRUPTS (DAIF_FIQ_BIT | DAIF_IRQ_BIT) 717 718 /* 719 * RMR_EL3 definitions 720 */ 721 #define RMR_EL3_RR_BIT (U(1) << 1) 722 #define RMR_EL3_AA64_BIT (U(1) << 0) 723 724 /* 725 * HI-VECTOR address for AArch32 state 726 */ 727 #define HI_VECTOR_BASE U(0xFFFF0000) 728 729 /* 730 * TCR defintions 731 */ 732 #define TCR_EL3_RES1 ((ULL(1) << 31) | (ULL(1) << 23)) 733 #define TCR_EL2_RES1 ((ULL(1) << 31) | (ULL(1) << 23)) 734 #define TCR_EL1_IPS_SHIFT U(32) 735 #define TCR_EL2_PS_SHIFT U(16) 736 #define TCR_EL3_PS_SHIFT U(16) 737 738 #define TCR_TxSZ_MIN ULL(16) 739 #define TCR_TxSZ_MAX ULL(39) 740 #define TCR_TxSZ_MAX_TTST ULL(48) 741 742 #define TCR_T0SZ_SHIFT U(0) 743 #define TCR_T1SZ_SHIFT U(16) 744 745 /* (internal) physical address size bits in EL3/EL1 */ 746 #define TCR_PS_BITS_4GB ULL(0x0) 747 #define TCR_PS_BITS_64GB ULL(0x1) 748 #define TCR_PS_BITS_1TB ULL(0x2) 749 #define TCR_PS_BITS_4TB ULL(0x3) 750 #define TCR_PS_BITS_16TB ULL(0x4) 751 #define TCR_PS_BITS_256TB ULL(0x5) 752 753 #define ADDR_MASK_48_TO_63 ULL(0xFFFF000000000000) 754 #define ADDR_MASK_44_TO_47 ULL(0x0000F00000000000) 755 #define ADDR_MASK_42_TO_43 ULL(0x00000C0000000000) 756 #define ADDR_MASK_40_TO_41 ULL(0x0000030000000000) 757 #define ADDR_MASK_36_TO_39 ULL(0x000000F000000000) 758 #define ADDR_MASK_32_TO_35 ULL(0x0000000F00000000) 759 760 #define TCR_RGN_INNER_NC (ULL(0x0) << 8) 761 #define TCR_RGN_INNER_WBA (ULL(0x1) << 8) 762 #define TCR_RGN_INNER_WT (ULL(0x2) << 8) 763 #define TCR_RGN_INNER_WBNA (ULL(0x3) << 8) 764 765 #define TCR_RGN_OUTER_NC (ULL(0x0) << 10) 766 #define TCR_RGN_OUTER_WBA (ULL(0x1) << 10) 767 #define TCR_RGN_OUTER_WT (ULL(0x2) << 10) 768 #define TCR_RGN_OUTER_WBNA (ULL(0x3) << 10) 769 770 #define TCR_SH_NON_SHAREABLE (ULL(0x0) << 12) 771 #define TCR_SH_OUTER_SHAREABLE (ULL(0x2) << 12) 772 #define TCR_SH_INNER_SHAREABLE (ULL(0x3) << 12) 773 774 #define TCR_RGN1_INNER_NC (ULL(0x0) << 24) 775 #define TCR_RGN1_INNER_WBA (ULL(0x1) << 24) 776 #define TCR_RGN1_INNER_WT (ULL(0x2) << 24) 777 #define TCR_RGN1_INNER_WBNA (ULL(0x3) << 24) 778 779 #define TCR_RGN1_OUTER_NC (ULL(0x0) << 26) 780 #define TCR_RGN1_OUTER_WBA (ULL(0x1) << 26) 781 #define TCR_RGN1_OUTER_WT (ULL(0x2) << 26) 782 #define TCR_RGN1_OUTER_WBNA (ULL(0x3) << 26) 783 784 #define TCR_SH1_NON_SHAREABLE (ULL(0x0) << 28) 785 #define TCR_SH1_OUTER_SHAREABLE (ULL(0x2) << 28) 786 #define TCR_SH1_INNER_SHAREABLE (ULL(0x3) << 28) 787 788 #define TCR_TG0_SHIFT U(14) 789 #define TCR_TG0_MASK ULL(3) 790 #define TCR_TG0_4K (ULL(0) << TCR_TG0_SHIFT) 791 #define TCR_TG0_64K (ULL(1) << TCR_TG0_SHIFT) 792 #define TCR_TG0_16K (ULL(2) << TCR_TG0_SHIFT) 793 794 #define TCR_TG1_SHIFT U(30) 795 #define TCR_TG1_MASK ULL(3) 796 #define TCR_TG1_16K (ULL(1) << TCR_TG1_SHIFT) 797 #define TCR_TG1_4K (ULL(2) << TCR_TG1_SHIFT) 798 #define TCR_TG1_64K (ULL(3) << TCR_TG1_SHIFT) 799 800 #define TCR_EPD0_BIT (ULL(1) << 7) 801 #define TCR_EPD1_BIT (ULL(1) << 23) 802 803 #define MODE_SP_SHIFT U(0x0) 804 #define MODE_SP_MASK U(0x1) 805 #define MODE_SP_EL0 U(0x0) 806 #define MODE_SP_ELX U(0x1) 807 808 #define MODE_RW_SHIFT U(0x4) 809 #define MODE_RW_MASK U(0x1) 810 #define MODE_RW_64 U(0x0) 811 #define MODE_RW_32 U(0x1) 812 813 #define MODE_EL_SHIFT U(0x2) 814 #define MODE_EL_MASK U(0x3) 815 #define MODE_EL_WIDTH U(0x2) 816 #define MODE_EL3 U(0x3) 817 #define MODE_EL2 U(0x2) 818 #define MODE_EL1 U(0x1) 819 #define MODE_EL0 U(0x0) 820 821 #define MODE32_SHIFT U(0) 822 #define MODE32_MASK U(0xf) 823 #define MODE32_usr U(0x0) 824 #define MODE32_fiq U(0x1) 825 #define MODE32_irq U(0x2) 826 #define MODE32_svc U(0x3) 827 #define MODE32_mon U(0x6) 828 #define MODE32_abt U(0x7) 829 #define MODE32_hyp U(0xa) 830 #define MODE32_und U(0xb) 831 #define MODE32_sys U(0xf) 832 833 #define GET_RW(mode) (((mode) >> MODE_RW_SHIFT) & MODE_RW_MASK) 834 #define GET_EL(mode) (((mode) >> MODE_EL_SHIFT) & MODE_EL_MASK) 835 #define GET_SP(mode) (((mode) >> MODE_SP_SHIFT) & MODE_SP_MASK) 836 #define GET_M32(mode) (((mode) >> MODE32_SHIFT) & MODE32_MASK) 837 838 #define SPSR_64(el, sp, daif) \ 839 (((MODE_RW_64 << MODE_RW_SHIFT) | \ 840 (((el) & MODE_EL_MASK) << MODE_EL_SHIFT) | \ 841 (((sp) & MODE_SP_MASK) << MODE_SP_SHIFT) | \ 842 (((daif) & SPSR_DAIF_MASK) << SPSR_DAIF_SHIFT)) & \ 843 (~(SPSR_SSBS_BIT_AARCH64))) 844 845 #define SPSR_MODE32(mode, isa, endian, aif) \ 846 (((MODE_RW_32 << MODE_RW_SHIFT) | \ 847 (((mode) & MODE32_MASK) << MODE32_SHIFT) | \ 848 (((isa) & SPSR_T_MASK) << SPSR_T_SHIFT) | \ 849 (((endian) & SPSR_E_MASK) << SPSR_E_SHIFT) | \ 850 (((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT)) & \ 851 (~(SPSR_SSBS_BIT_AARCH32))) 852 853 /* 854 * TTBR Definitions 855 */ 856 #define TTBR_CNP_BIT ULL(0x1) 857 858 /* 859 * CTR_EL0 definitions 860 */ 861 #define CTR_CWG_SHIFT U(24) 862 #define CTR_CWG_MASK U(0xf) 863 #define CTR_ERG_SHIFT U(20) 864 #define CTR_ERG_MASK U(0xf) 865 #define CTR_DMINLINE_SHIFT U(16) 866 #define CTR_DMINLINE_MASK U(0xf) 867 #define CTR_L1IP_SHIFT U(14) 868 #define CTR_L1IP_MASK U(0x3) 869 #define CTR_IMINLINE_SHIFT U(0) 870 #define CTR_IMINLINE_MASK U(0xf) 871 872 #define MAX_CACHE_LINE_SIZE U(0x800) /* 2KB */ 873 874 /* Physical timer control register bit fields shifts and masks */ 875 #define CNTP_CTL_ENABLE_SHIFT U(0) 876 #define CNTP_CTL_IMASK_SHIFT U(1) 877 #define CNTP_CTL_ISTATUS_SHIFT U(2) 878 879 #define CNTP_CTL_ENABLE_MASK U(1) 880 #define CNTP_CTL_IMASK_MASK U(1) 881 #define CNTP_CTL_ISTATUS_MASK U(1) 882 883 /* Physical timer control macros */ 884 #define CNTP_CTL_ENABLE_BIT (U(1) << CNTP_CTL_ENABLE_SHIFT) 885 #define CNTP_CTL_IMASK_BIT (U(1) << CNTP_CTL_IMASK_SHIFT) 886 887 /* Exception Syndrome register bits and bobs */ 888 #define ESR_EC_SHIFT U(26) 889 #define ESR_EC_MASK U(0x3f) 890 #define ESR_EC_LENGTH U(6) 891 #define ESR_ISS_SHIFT U(0) 892 #define ESR_ISS_LENGTH U(25) 893 #define EC_UNKNOWN U(0x0) 894 #define EC_WFE_WFI U(0x1) 895 #define EC_AARCH32_CP15_MRC_MCR U(0x3) 896 #define EC_AARCH32_CP15_MRRC_MCRR U(0x4) 897 #define EC_AARCH32_CP14_MRC_MCR U(0x5) 898 #define EC_AARCH32_CP14_LDC_STC U(0x6) 899 #define EC_FP_SIMD U(0x7) 900 #define EC_AARCH32_CP10_MRC U(0x8) 901 #define EC_AARCH32_CP14_MRRC_MCRR U(0xc) 902 #define EC_ILLEGAL U(0xe) 903 #define EC_AARCH32_SVC U(0x11) 904 #define EC_AARCH32_HVC U(0x12) 905 #define EC_AARCH32_SMC U(0x13) 906 #define EC_AARCH64_SVC U(0x15) 907 #define EC_AARCH64_HVC U(0x16) 908 #define EC_AARCH64_SMC U(0x17) 909 #define EC_AARCH64_SYS U(0x18) 910 #define EC_IABORT_LOWER_EL U(0x20) 911 #define EC_IABORT_CUR_EL U(0x21) 912 #define EC_PC_ALIGN U(0x22) 913 #define EC_DABORT_LOWER_EL U(0x24) 914 #define EC_DABORT_CUR_EL U(0x25) 915 #define EC_SP_ALIGN U(0x26) 916 #define EC_AARCH32_FP U(0x28) 917 #define EC_AARCH64_FP U(0x2c) 918 #define EC_SERROR U(0x2f) 919 #define EC_BRK U(0x3c) 920 921 /* 922 * External Abort bit in Instruction and Data Aborts synchronous exception 923 * syndromes. 924 */ 925 #define ESR_ISS_EABORT_EA_BIT U(9) 926 927 #define EC_BITS(x) (((x) >> ESR_EC_SHIFT) & ESR_EC_MASK) 928 929 /* Reset bit inside the Reset management register for EL3 (RMR_EL3) */ 930 #define RMR_RESET_REQUEST_SHIFT U(0x1) 931 #define RMR_WARM_RESET_CPU (U(1) << RMR_RESET_REQUEST_SHIFT) 932 933 /******************************************************************************* 934 * Definitions of register offsets, fields and macros for CPU system 935 * instructions. 936 ******************************************************************************/ 937 938 #define TLBI_ADDR_SHIFT U(12) 939 #define TLBI_ADDR_MASK ULL(0x00000FFFFFFFFFFF) 940 #define TLBI_ADDR(x) (((x) >> TLBI_ADDR_SHIFT) & TLBI_ADDR_MASK) 941 942 /******************************************************************************* 943 * Definitions of register offsets and fields in the CNTCTLBase Frame of the 944 * system level implementation of the Generic Timer. 945 ******************************************************************************/ 946 #define CNTCTLBASE_CNTFRQ U(0x0) 947 #define CNTNSAR U(0x4) 948 #define CNTNSAR_NS_SHIFT(x) (x) 949 950 #define CNTACR_BASE(x) (U(0x40) + ((x) << 2)) 951 #define CNTACR_RPCT_SHIFT U(0x0) 952 #define CNTACR_RVCT_SHIFT U(0x1) 953 #define CNTACR_RFRQ_SHIFT U(0x2) 954 #define CNTACR_RVOFF_SHIFT U(0x3) 955 #define CNTACR_RWVT_SHIFT U(0x4) 956 #define CNTACR_RWPT_SHIFT U(0x5) 957 958 /******************************************************************************* 959 * Definitions of register offsets and fields in the CNTBaseN Frame of the 960 * system level implementation of the Generic Timer. 961 ******************************************************************************/ 962 /* Physical Count register. */ 963 #define CNTPCT_LO U(0x0) 964 /* Counter Frequency register. */ 965 #define CNTBASEN_CNTFRQ U(0x10) 966 /* Physical Timer CompareValue register. */ 967 #define CNTP_CVAL_LO U(0x20) 968 /* Physical Timer Control register. */ 969 #define CNTP_CTL U(0x2c) 970 971 /* PMCR_EL0 definitions */ 972 #define PMCR_EL0_RESET_VAL U(0x0) 973 #define PMCR_EL0_N_SHIFT U(11) 974 #define PMCR_EL0_N_MASK U(0x1f) 975 #define PMCR_EL0_N_BITS (PMCR_EL0_N_MASK << PMCR_EL0_N_SHIFT) 976 #define PMCR_EL0_LP_BIT (U(1) << 7) 977 #define PMCR_EL0_LC_BIT (U(1) << 6) 978 #define PMCR_EL0_DP_BIT (U(1) << 5) 979 #define PMCR_EL0_X_BIT (U(1) << 4) 980 #define PMCR_EL0_D_BIT (U(1) << 3) 981 #define PMCR_EL0_C_BIT (U(1) << 2) 982 #define PMCR_EL0_P_BIT (U(1) << 1) 983 #define PMCR_EL0_E_BIT (U(1) << 0) 984 985 /******************************************************************************* 986 * Definitions for system register interface to SVE 987 ******************************************************************************/ 988 #define ZCR_EL3 S3_6_C1_C2_0 989 #define ZCR_EL2 S3_4_C1_C2_0 990 991 /* ZCR_EL3 definitions */ 992 #define ZCR_EL3_LEN_MASK U(0xf) 993 994 /* ZCR_EL2 definitions */ 995 #define ZCR_EL2_LEN_MASK U(0xf) 996 997 /******************************************************************************* 998 * Definitions for system register interface to SME as needed in EL3 999 ******************************************************************************/ 1000 #define ID_AA64SMFR0_EL1 S3_0_C0_C4_5 1001 #define SMCR_EL3 S3_6_C1_C2_6 1002 1003 /* ID_AA64SMFR0_EL1 definitions */ 1004 #define ID_AA64SMFR0_EL1_FA64_BIT (UL(1) << 63) 1005 1006 /* SMCR_ELx definitions */ 1007 #define SMCR_ELX_LEN_SHIFT U(0) 1008 #define SMCR_ELX_LEN_MASK U(0x1ff) 1009 #define SMCR_ELX_FA64_BIT (U(1) << 31) 1010 1011 /******************************************************************************* 1012 * Definitions of MAIR encodings for device and normal memory 1013 ******************************************************************************/ 1014 /* 1015 * MAIR encodings for device memory attributes. 1016 */ 1017 #define MAIR_DEV_nGnRnE ULL(0x0) 1018 #define MAIR_DEV_nGnRE ULL(0x4) 1019 #define MAIR_DEV_nGRE ULL(0x8) 1020 #define MAIR_DEV_GRE ULL(0xc) 1021 1022 /* 1023 * MAIR encodings for normal memory attributes. 1024 * 1025 * Cache Policy 1026 * WT: Write Through 1027 * WB: Write Back 1028 * NC: Non-Cacheable 1029 * 1030 * Transient Hint 1031 * NTR: Non-Transient 1032 * TR: Transient 1033 * 1034 * Allocation Policy 1035 * RA: Read Allocate 1036 * WA: Write Allocate 1037 * RWA: Read and Write Allocate 1038 * NA: No Allocation 1039 */ 1040 #define MAIR_NORM_WT_TR_WA ULL(0x1) 1041 #define MAIR_NORM_WT_TR_RA ULL(0x2) 1042 #define MAIR_NORM_WT_TR_RWA ULL(0x3) 1043 #define MAIR_NORM_NC ULL(0x4) 1044 #define MAIR_NORM_WB_TR_WA ULL(0x5) 1045 #define MAIR_NORM_WB_TR_RA ULL(0x6) 1046 #define MAIR_NORM_WB_TR_RWA ULL(0x7) 1047 #define MAIR_NORM_WT_NTR_NA ULL(0x8) 1048 #define MAIR_NORM_WT_NTR_WA ULL(0x9) 1049 #define MAIR_NORM_WT_NTR_RA ULL(0xa) 1050 #define MAIR_NORM_WT_NTR_RWA ULL(0xb) 1051 #define MAIR_NORM_WB_NTR_NA ULL(0xc) 1052 #define MAIR_NORM_WB_NTR_WA ULL(0xd) 1053 #define MAIR_NORM_WB_NTR_RA ULL(0xe) 1054 #define MAIR_NORM_WB_NTR_RWA ULL(0xf) 1055 1056 #define MAIR_NORM_OUTER_SHIFT U(4) 1057 1058 #define MAKE_MAIR_NORMAL_MEMORY(inner, outer) \ 1059 ((inner) | ((outer) << MAIR_NORM_OUTER_SHIFT)) 1060 1061 /* PAR_EL1 fields */ 1062 #define PAR_F_SHIFT U(0) 1063 #define PAR_F_MASK ULL(0x1) 1064 #define PAR_ADDR_SHIFT U(12) 1065 #define PAR_ADDR_MASK (BIT(40) - ULL(1)) /* 40-bits-wide page address */ 1066 1067 /******************************************************************************* 1068 * Definitions for system register interface to SPE 1069 ******************************************************************************/ 1070 #define PMBLIMITR_EL1 S3_0_C9_C10_0 1071 1072 /******************************************************************************* 1073 * Definitions for system register interface, shifts and masks for MPAM 1074 ******************************************************************************/ 1075 #define MPAMIDR_EL1 S3_0_C10_C4_4 1076 #define MPAM2_EL2 S3_4_C10_C5_0 1077 #define MPAMHCR_EL2 S3_4_C10_C4_0 1078 #define MPAM3_EL3 S3_6_C10_C5_0 1079 1080 #define MPAMIDR_EL1_HAS_HCR_SHIFT ULL(0x11) 1081 #define MPAMIDR_EL1_VPMR_MAX_SHIFT ULL(0x12) 1082 #define MPAMIDR_EL1_VPMR_MAX_WIDTH ULL(0x3) 1083 #define MPAMIDR_EL1_VPMR_MAX_POSSIBLE ULL(0x7) 1084 /******************************************************************************* 1085 * Definitions for system register interface to AMU for FEAT_AMUv1 1086 ******************************************************************************/ 1087 #define AMCR_EL0 S3_3_C13_C2_0 1088 #define AMCFGR_EL0 S3_3_C13_C2_1 1089 #define AMCGCR_EL0 S3_3_C13_C2_2 1090 #define AMUSERENR_EL0 S3_3_C13_C2_3 1091 #define AMCNTENCLR0_EL0 S3_3_C13_C2_4 1092 #define AMCNTENSET0_EL0 S3_3_C13_C2_5 1093 #define AMCNTENCLR1_EL0 S3_3_C13_C3_0 1094 #define AMCNTENSET1_EL0 S3_3_C13_C3_1 1095 1096 /* Activity Monitor Group 0 Event Counter Registers */ 1097 #define AMEVCNTR00_EL0 S3_3_C13_C4_0 1098 #define AMEVCNTR01_EL0 S3_3_C13_C4_1 1099 #define AMEVCNTR02_EL0 S3_3_C13_C4_2 1100 #define AMEVCNTR03_EL0 S3_3_C13_C4_3 1101 1102 /* Activity Monitor Group 0 Event Type Registers */ 1103 #define AMEVTYPER00_EL0 S3_3_C13_C6_0 1104 #define AMEVTYPER01_EL0 S3_3_C13_C6_1 1105 #define AMEVTYPER02_EL0 S3_3_C13_C6_2 1106 #define AMEVTYPER03_EL0 S3_3_C13_C6_3 1107 1108 /* Activity Monitor Group 1 Event Counter Registers */ 1109 #define AMEVCNTR10_EL0 S3_3_C13_C12_0 1110 #define AMEVCNTR11_EL0 S3_3_C13_C12_1 1111 #define AMEVCNTR12_EL0 S3_3_C13_C12_2 1112 #define AMEVCNTR13_EL0 S3_3_C13_C12_3 1113 #define AMEVCNTR14_EL0 S3_3_C13_C12_4 1114 #define AMEVCNTR15_EL0 S3_3_C13_C12_5 1115 #define AMEVCNTR16_EL0 S3_3_C13_C12_6 1116 #define AMEVCNTR17_EL0 S3_3_C13_C12_7 1117 #define AMEVCNTR18_EL0 S3_3_C13_C13_0 1118 #define AMEVCNTR19_EL0 S3_3_C13_C13_1 1119 #define AMEVCNTR1A_EL0 S3_3_C13_C13_2 1120 #define AMEVCNTR1B_EL0 S3_3_C13_C13_3 1121 #define AMEVCNTR1C_EL0 S3_3_C13_C13_4 1122 #define AMEVCNTR1D_EL0 S3_3_C13_C13_5 1123 #define AMEVCNTR1E_EL0 S3_3_C13_C13_6 1124 #define AMEVCNTR1F_EL0 S3_3_C13_C13_7 1125 1126 /* Activity Monitor Group 1 Event Type Registers */ 1127 #define AMEVTYPER10_EL0 S3_3_C13_C14_0 1128 #define AMEVTYPER11_EL0 S3_3_C13_C14_1 1129 #define AMEVTYPER12_EL0 S3_3_C13_C14_2 1130 #define AMEVTYPER13_EL0 S3_3_C13_C14_3 1131 #define AMEVTYPER14_EL0 S3_3_C13_C14_4 1132 #define AMEVTYPER15_EL0 S3_3_C13_C14_5 1133 #define AMEVTYPER16_EL0 S3_3_C13_C14_6 1134 #define AMEVTYPER17_EL0 S3_3_C13_C14_7 1135 #define AMEVTYPER18_EL0 S3_3_C13_C15_0 1136 #define AMEVTYPER19_EL0 S3_3_C13_C15_1 1137 #define AMEVTYPER1A_EL0 S3_3_C13_C15_2 1138 #define AMEVTYPER1B_EL0 S3_3_C13_C15_3 1139 #define AMEVTYPER1C_EL0 S3_3_C13_C15_4 1140 #define AMEVTYPER1D_EL0 S3_3_C13_C15_5 1141 #define AMEVTYPER1E_EL0 S3_3_C13_C15_6 1142 #define AMEVTYPER1F_EL0 S3_3_C13_C15_7 1143 1144 /* AMCNTENSET0_EL0 definitions */ 1145 #define AMCNTENSET0_EL0_Pn_SHIFT U(0) 1146 #define AMCNTENSET0_EL0_Pn_MASK ULL(0xffff) 1147 1148 /* AMCNTENSET1_EL0 definitions */ 1149 #define AMCNTENSET1_EL0_Pn_SHIFT U(0) 1150 #define AMCNTENSET1_EL0_Pn_MASK ULL(0xffff) 1151 1152 /* AMCNTENCLR0_EL0 definitions */ 1153 #define AMCNTENCLR0_EL0_Pn_SHIFT U(0) 1154 #define AMCNTENCLR0_EL0_Pn_MASK ULL(0xffff) 1155 1156 /* AMCNTENCLR1_EL0 definitions */ 1157 #define AMCNTENCLR1_EL0_Pn_SHIFT U(0) 1158 #define AMCNTENCLR1_EL0_Pn_MASK ULL(0xffff) 1159 1160 /* AMCFGR_EL0 definitions */ 1161 #define AMCFGR_EL0_NCG_SHIFT U(28) 1162 #define AMCFGR_EL0_NCG_MASK U(0xf) 1163 #define AMCFGR_EL0_N_SHIFT U(0) 1164 #define AMCFGR_EL0_N_MASK U(0xff) 1165 1166 /* AMCGCR_EL0 definitions */ 1167 #define AMCGCR_EL0_CG0NC_SHIFT U(0) 1168 #define AMCGCR_EL0_CG0NC_MASK U(0xff) 1169 #define AMCGCR_EL0_CG1NC_SHIFT U(8) 1170 #define AMCGCR_EL0_CG1NC_MASK U(0xff) 1171 1172 /* MPAM register definitions */ 1173 #define MPAM3_EL3_MPAMEN_BIT (ULL(1) << 63) 1174 #define MPAMHCR_EL2_TRAP_MPAMIDR_EL1 (ULL(1) << 31) 1175 1176 #define MPAM2_EL2_TRAPMPAM0EL1 (ULL(1) << 49) 1177 #define MPAM2_EL2_TRAPMPAM1EL1 (ULL(1) << 48) 1178 1179 #define MPAMIDR_HAS_HCR_BIT (ULL(1) << 17) 1180 1181 /******************************************************************************* 1182 * Definitions for system register interface to AMU for FEAT_AMUv1p1 1183 ******************************************************************************/ 1184 1185 /* Definition for register defining which virtual offsets are implemented. */ 1186 #define AMCG1IDR_EL0 S3_3_C13_C2_6 1187 #define AMCG1IDR_CTR_MASK ULL(0xffff) 1188 #define AMCG1IDR_CTR_SHIFT U(0) 1189 #define AMCG1IDR_VOFF_MASK ULL(0xffff) 1190 #define AMCG1IDR_VOFF_SHIFT U(16) 1191 1192 /* New bit added to AMCR_EL0 */ 1193 #define AMCR_CG1RZ_SHIFT U(17) 1194 #define AMCR_CG1RZ_BIT (ULL(0x1) << AMCR_CG1RZ_SHIFT) 1195 1196 /* 1197 * Definitions for virtual offset registers for architected activity monitor 1198 * event counters. 1199 * AMEVCNTVOFF01_EL2 intentionally left undefined, as it does not exist. 1200 */ 1201 #define AMEVCNTVOFF00_EL2 S3_4_C13_C8_0 1202 #define AMEVCNTVOFF02_EL2 S3_4_C13_C8_2 1203 #define AMEVCNTVOFF03_EL2 S3_4_C13_C8_3 1204 1205 /* 1206 * Definitions for virtual offset registers for auxiliary activity monitor event 1207 * counters. 1208 */ 1209 #define AMEVCNTVOFF10_EL2 S3_4_C13_C10_0 1210 #define AMEVCNTVOFF11_EL2 S3_4_C13_C10_1 1211 #define AMEVCNTVOFF12_EL2 S3_4_C13_C10_2 1212 #define AMEVCNTVOFF13_EL2 S3_4_C13_C10_3 1213 #define AMEVCNTVOFF14_EL2 S3_4_C13_C10_4 1214 #define AMEVCNTVOFF15_EL2 S3_4_C13_C10_5 1215 #define AMEVCNTVOFF16_EL2 S3_4_C13_C10_6 1216 #define AMEVCNTVOFF17_EL2 S3_4_C13_C10_7 1217 #define AMEVCNTVOFF18_EL2 S3_4_C13_C11_0 1218 #define AMEVCNTVOFF19_EL2 S3_4_C13_C11_1 1219 #define AMEVCNTVOFF1A_EL2 S3_4_C13_C11_2 1220 #define AMEVCNTVOFF1B_EL2 S3_4_C13_C11_3 1221 #define AMEVCNTVOFF1C_EL2 S3_4_C13_C11_4 1222 #define AMEVCNTVOFF1D_EL2 S3_4_C13_C11_5 1223 #define AMEVCNTVOFF1E_EL2 S3_4_C13_C11_6 1224 #define AMEVCNTVOFF1F_EL2 S3_4_C13_C11_7 1225 1226 /******************************************************************************* 1227 * Realm management extension register definitions 1228 ******************************************************************************/ 1229 #define GPCCR_EL3 S3_6_C2_C1_6 1230 #define GPTBR_EL3 S3_6_C2_C1_4 1231 1232 /******************************************************************************* 1233 * RAS system registers 1234 ******************************************************************************/ 1235 #define DISR_EL1 S3_0_C12_C1_1 1236 #define DISR_A_BIT U(31) 1237 1238 #define ERRIDR_EL1 S3_0_C5_C3_0 1239 #define ERRIDR_MASK U(0xffff) 1240 1241 #define ERRSELR_EL1 S3_0_C5_C3_1 1242 1243 /* System register access to Standard Error Record registers */ 1244 #define ERXFR_EL1 S3_0_C5_C4_0 1245 #define ERXCTLR_EL1 S3_0_C5_C4_1 1246 #define ERXSTATUS_EL1 S3_0_C5_C4_2 1247 #define ERXADDR_EL1 S3_0_C5_C4_3 1248 #define ERXPFGF_EL1 S3_0_C5_C4_4 1249 #define ERXPFGCTL_EL1 S3_0_C5_C4_5 1250 #define ERXPFGCDN_EL1 S3_0_C5_C4_6 1251 #define ERXMISC0_EL1 S3_0_C5_C5_0 1252 #define ERXMISC1_EL1 S3_0_C5_C5_1 1253 1254 #define ERXCTLR_ED_SHIFT U(0) 1255 #define ERXCTLR_ED_BIT (U(1) << ERXCTLR_ED_SHIFT) 1256 #define ERXCTLR_UE_BIT (U(1) << 4) 1257 1258 #define ERXPFGCTL_UC_BIT (U(1) << 1) 1259 #define ERXPFGCTL_UEU_BIT (U(1) << 2) 1260 #define ERXPFGCTL_CDEN_BIT (U(1) << 31) 1261 1262 /******************************************************************************* 1263 * Armv8.3 Pointer Authentication Registers 1264 ******************************************************************************/ 1265 #define APIAKeyLo_EL1 S3_0_C2_C1_0 1266 #define APIAKeyHi_EL1 S3_0_C2_C1_1 1267 #define APIBKeyLo_EL1 S3_0_C2_C1_2 1268 #define APIBKeyHi_EL1 S3_0_C2_C1_3 1269 #define APDAKeyLo_EL1 S3_0_C2_C2_0 1270 #define APDAKeyHi_EL1 S3_0_C2_C2_1 1271 #define APDBKeyLo_EL1 S3_0_C2_C2_2 1272 #define APDBKeyHi_EL1 S3_0_C2_C2_3 1273 #define APGAKeyLo_EL1 S3_0_C2_C3_0 1274 #define APGAKeyHi_EL1 S3_0_C2_C3_1 1275 1276 /******************************************************************************* 1277 * Armv8.4 Data Independent Timing Registers 1278 ******************************************************************************/ 1279 #define DIT S3_3_C4_C2_5 1280 #define DIT_BIT BIT(24) 1281 1282 /******************************************************************************* 1283 * Armv8.5 - new MSR encoding to directly access PSTATE.SSBS field 1284 ******************************************************************************/ 1285 #define SSBS S3_3_C4_C2_6 1286 1287 /******************************************************************************* 1288 * Armv8.5 - Memory Tagging Extension Registers 1289 ******************************************************************************/ 1290 #define TFSRE0_EL1 S3_0_C5_C6_1 1291 #define TFSR_EL1 S3_0_C5_C6_0 1292 #define RGSR_EL1 S3_0_C1_C0_5 1293 #define GCR_EL1 S3_0_C1_C0_6 1294 1295 /******************************************************************************* 1296 * Armv8.5 - Random Number Generator Registers 1297 ******************************************************************************/ 1298 #define RNDR S3_3_C2_C4_0 1299 #define RNDRRS S3_3_C2_C4_1 1300 1301 /******************************************************************************* 1302 * FEAT_HCX - Extended Hypervisor Configuration Register 1303 ******************************************************************************/ 1304 #define HCRX_EL2 S3_4_C1_C2_2 1305 #define HCRX_EL2_FGTnXS_BIT (UL(1) << 4) 1306 #define HCRX_EL2_FnXS_BIT (UL(1) << 3) 1307 #define HCRX_EL2_EnASR_BIT (UL(1) << 2) 1308 #define HCRX_EL2_EnALS_BIT (UL(1) << 1) 1309 #define HCRX_EL2_EnAS0_BIT (UL(1) << 0) 1310 1311 /******************************************************************************* 1312 * FEAT_TCR2 - Extended Translation Control Register 1313 ******************************************************************************/ 1314 #define TCR2_EL2 S3_4_C2_C0_3 1315 1316 /******************************************************************************* 1317 * Definitions for DynamicIQ Shared Unit registers 1318 ******************************************************************************/ 1319 #define CLUSTERPWRDN_EL1 S3_0_c15_c3_6 1320 1321 /* CLUSTERPWRDN_EL1 register definitions */ 1322 #define DSU_CLUSTER_PWR_OFF 0 1323 #define DSU_CLUSTER_PWR_ON 1 1324 #define DSU_CLUSTER_PWR_MASK U(1) 1325 1326 /******************************************************************************* 1327 * Definitions for CPU Power/Performance Management registers 1328 ******************************************************************************/ 1329 1330 #define CPUPPMCR_EL3 S3_6_C15_C2_0 1331 #define CPUPPMCR_EL3_MPMMPINCTL_SHIFT UINT64_C(0) 1332 #define CPUPPMCR_EL3_MPMMPINCTL_MASK UINT64_C(0x1) 1333 1334 #define CPUMPMMCR_EL3 S3_6_C15_C2_1 1335 #define CPUMPMMCR_EL3_MPMM_EN_SHIFT UINT64_C(0) 1336 #define CPUMPMMCR_EL3_MPMM_EN_MASK UINT64_C(0x1) 1337 1338 #endif /* ARCH_H */ 1339