1 /* 2 * Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2020-2022, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef ARCH_H 9 #define ARCH_H 10 11 #include <lib/utils_def.h> 12 13 /******************************************************************************* 14 * MIDR bit definitions 15 ******************************************************************************/ 16 #define MIDR_IMPL_MASK U(0xff) 17 #define MIDR_IMPL_SHIFT U(0x18) 18 #define MIDR_VAR_SHIFT U(20) 19 #define MIDR_VAR_BITS U(4) 20 #define MIDR_VAR_MASK U(0xf) 21 #define MIDR_REV_SHIFT U(0) 22 #define MIDR_REV_BITS U(4) 23 #define MIDR_REV_MASK U(0xf) 24 #define MIDR_PN_MASK U(0xfff) 25 #define MIDR_PN_SHIFT U(0x4) 26 27 /******************************************************************************* 28 * MPIDR macros 29 ******************************************************************************/ 30 #define MPIDR_MT_MASK (ULL(1) << 24) 31 #define MPIDR_CPU_MASK MPIDR_AFFLVL_MASK 32 #define MPIDR_CLUSTER_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS) 33 #define MPIDR_AFFINITY_BITS U(8) 34 #define MPIDR_AFFLVL_MASK ULL(0xff) 35 #define MPIDR_AFF0_SHIFT U(0) 36 #define MPIDR_AFF1_SHIFT U(8) 37 #define MPIDR_AFF2_SHIFT U(16) 38 #define MPIDR_AFF3_SHIFT U(32) 39 #define MPIDR_AFF_SHIFT(_n) MPIDR_AFF##_n##_SHIFT 40 #define MPIDR_AFFINITY_MASK ULL(0xff00ffffff) 41 #define MPIDR_AFFLVL_SHIFT U(3) 42 #define MPIDR_AFFLVL0 ULL(0x0) 43 #define MPIDR_AFFLVL1 ULL(0x1) 44 #define MPIDR_AFFLVL2 ULL(0x2) 45 #define MPIDR_AFFLVL3 ULL(0x3) 46 #define MPIDR_AFFLVL(_n) MPIDR_AFFLVL##_n 47 #define MPIDR_AFFLVL0_VAL(mpidr) \ 48 (((mpidr) >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK) 49 #define MPIDR_AFFLVL1_VAL(mpidr) \ 50 (((mpidr) >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK) 51 #define MPIDR_AFFLVL2_VAL(mpidr) \ 52 (((mpidr) >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK) 53 #define MPIDR_AFFLVL3_VAL(mpidr) \ 54 (((mpidr) >> MPIDR_AFF3_SHIFT) & MPIDR_AFFLVL_MASK) 55 /* 56 * The MPIDR_MAX_AFFLVL count starts from 0. Take care to 57 * add one while using this macro to define array sizes. 58 * TODO: Support only the first 3 affinity levels for now. 59 */ 60 #define MPIDR_MAX_AFFLVL U(2) 61 62 #define MPID_MASK (MPIDR_MT_MASK | \ 63 (MPIDR_AFFLVL_MASK << MPIDR_AFF3_SHIFT) | \ 64 (MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT) | \ 65 (MPIDR_AFFLVL_MASK << MPIDR_AFF1_SHIFT) | \ 66 (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT)) 67 68 #define MPIDR_AFF_ID(mpid, n) \ 69 (((mpid) >> MPIDR_AFF_SHIFT(n)) & MPIDR_AFFLVL_MASK) 70 71 /* 72 * An invalid MPID. This value can be used by functions that return an MPID to 73 * indicate an error. 74 */ 75 #define INVALID_MPID U(0xFFFFFFFF) 76 77 /******************************************************************************* 78 * Definitions for Exception vector offsets 79 ******************************************************************************/ 80 #define CURRENT_EL_SP0 0x0 81 #define CURRENT_EL_SPX 0x200 82 #define LOWER_EL_AARCH64 0x400 83 #define LOWER_EL_AARCH32 0x600 84 85 #define SYNC_EXCEPTION 0x0 86 #define IRQ_EXCEPTION 0x80 87 #define FIQ_EXCEPTION 0x100 88 #define SERROR_EXCEPTION 0x180 89 90 /******************************************************************************* 91 * Definitions for CPU system register interface to GICv3 92 ******************************************************************************/ 93 #define ICC_IGRPEN1_EL1 S3_0_C12_C12_7 94 #define ICC_SGI1R S3_0_C12_C11_5 95 #define ICC_ASGI1R S3_0_C12_C11_6 96 #define ICC_SRE_EL1 S3_0_C12_C12_5 97 #define ICC_SRE_EL2 S3_4_C12_C9_5 98 #define ICC_SRE_EL3 S3_6_C12_C12_5 99 #define ICC_CTLR_EL1 S3_0_C12_C12_4 100 #define ICC_CTLR_EL3 S3_6_C12_C12_4 101 #define ICC_PMR_EL1 S3_0_C4_C6_0 102 #define ICC_RPR_EL1 S3_0_C12_C11_3 103 #define ICC_IGRPEN1_EL3 S3_6_c12_c12_7 104 #define ICC_IGRPEN0_EL1 S3_0_c12_c12_6 105 #define ICC_HPPIR0_EL1 S3_0_c12_c8_2 106 #define ICC_HPPIR1_EL1 S3_0_c12_c12_2 107 #define ICC_IAR0_EL1 S3_0_c12_c8_0 108 #define ICC_IAR1_EL1 S3_0_c12_c12_0 109 #define ICC_EOIR0_EL1 S3_0_c12_c8_1 110 #define ICC_EOIR1_EL1 S3_0_c12_c12_1 111 #define ICC_SGI0R_EL1 S3_0_c12_c11_7 112 113 /******************************************************************************* 114 * Definitions for EL2 system registers for save/restore routine 115 ******************************************************************************/ 116 #define CNTPOFF_EL2 S3_4_C14_C0_6 117 #define HAFGRTR_EL2 S3_4_C3_C1_6 118 #define HDFGRTR_EL2 S3_4_C3_C1_4 119 #define HDFGWTR_EL2 S3_4_C3_C1_5 120 #define HFGITR_EL2 S3_4_C1_C1_6 121 #define HFGRTR_EL2 S3_4_C1_C1_4 122 #define HFGWTR_EL2 S3_4_C1_C1_5 123 #define ICH_HCR_EL2 S3_4_C12_C11_0 124 #define ICH_VMCR_EL2 S3_4_C12_C11_7 125 #define MPAMVPM0_EL2 S3_4_C10_C6_0 126 #define MPAMVPM1_EL2 S3_4_C10_C6_1 127 #define MPAMVPM2_EL2 S3_4_C10_C6_2 128 #define MPAMVPM3_EL2 S3_4_C10_C6_3 129 #define MPAMVPM4_EL2 S3_4_C10_C6_4 130 #define MPAMVPM5_EL2 S3_4_C10_C6_5 131 #define MPAMVPM6_EL2 S3_4_C10_C6_6 132 #define MPAMVPM7_EL2 S3_4_C10_C6_7 133 #define MPAMVPMV_EL2 S3_4_C10_C4_1 134 #define VNCR_EL2 S3_4_C2_C2_0 135 #define PMSCR_EL2 S3_4_C9_C9_0 136 #define TFSR_EL2 S3_4_C5_C6_0 137 #define CONTEXTIDR_EL2 S3_4_C13_C0_1 138 #define TTBR1_EL2 S3_4_C2_C0_1 139 140 /******************************************************************************* 141 * Generic timer memory mapped registers & offsets 142 ******************************************************************************/ 143 #define CNTCR_OFF U(0x000) 144 #define CNTCV_OFF U(0x008) 145 #define CNTFID_OFF U(0x020) 146 147 #define CNTCR_EN (U(1) << 0) 148 #define CNTCR_HDBG (U(1) << 1) 149 #define CNTCR_FCREQ(x) ((x) << 8) 150 151 /******************************************************************************* 152 * System register bit definitions 153 ******************************************************************************/ 154 /* CLIDR definitions */ 155 #define LOUIS_SHIFT U(21) 156 #define LOC_SHIFT U(24) 157 #define CTYPE_SHIFT(n) U(3 * (n - 1)) 158 #define CLIDR_FIELD_WIDTH U(3) 159 160 /* CSSELR definitions */ 161 #define LEVEL_SHIFT U(1) 162 163 /* Data cache set/way op type defines */ 164 #define DCISW U(0x0) 165 #define DCCISW U(0x1) 166 #if ERRATA_A53_827319 167 #define DCCSW DCCISW 168 #else 169 #define DCCSW U(0x2) 170 #endif 171 172 #define ID_REG_FIELD_MASK ULL(0xf) 173 174 /* ID_AA64PFR0_EL1 definitions */ 175 #define ID_AA64PFR0_EL0_SHIFT U(0) 176 #define ID_AA64PFR0_EL1_SHIFT U(4) 177 #define ID_AA64PFR0_EL2_SHIFT U(8) 178 #define ID_AA64PFR0_EL3_SHIFT U(12) 179 180 #define ID_AA64PFR0_AMU_SHIFT U(44) 181 #define ID_AA64PFR0_AMU_MASK ULL(0xf) 182 #define ID_AA64PFR0_AMU_NOT_SUPPORTED U(0x0) 183 #define ID_AA64PFR0_AMU_V1 ULL(0x1) 184 #define ID_AA64PFR0_AMU_V1P1 U(0x2) 185 186 #define ID_AA64PFR0_ELX_MASK ULL(0xf) 187 188 #define ID_AA64PFR0_GIC_SHIFT U(24) 189 #define ID_AA64PFR0_GIC_WIDTH U(4) 190 #define ID_AA64PFR0_GIC_MASK ULL(0xf) 191 192 #define ID_AA64PFR0_SVE_SHIFT U(32) 193 #define ID_AA64PFR0_SVE_MASK ULL(0xf) 194 #define ID_AA64PFR0_SVE_SUPPORTED ULL(0x1) 195 #define ID_AA64PFR0_SVE_LENGTH U(4) 196 197 #define ID_AA64PFR0_SEL2_SHIFT U(36) 198 #define ID_AA64PFR0_SEL2_MASK ULL(0xf) 199 200 #define ID_AA64PFR0_MPAM_SHIFT U(40) 201 #define ID_AA64PFR0_MPAM_MASK ULL(0xf) 202 203 #define ID_AA64PFR0_DIT_SHIFT U(48) 204 #define ID_AA64PFR0_DIT_MASK ULL(0xf) 205 #define ID_AA64PFR0_DIT_LENGTH U(4) 206 #define ID_AA64PFR0_DIT_SUPPORTED U(1) 207 208 #define ID_AA64PFR0_CSV2_SHIFT U(56) 209 #define ID_AA64PFR0_CSV2_MASK ULL(0xf) 210 #define ID_AA64PFR0_CSV2_LENGTH U(4) 211 #define ID_AA64PFR0_CSV2_2_SUPPORTED ULL(0x2) 212 #define ID_AA64PFR0_CSV2_3_SUPPORTED ULL(0x3) 213 214 #define ID_AA64PFR0_FEAT_RME_SHIFT U(52) 215 #define ID_AA64PFR0_FEAT_RME_MASK ULL(0xf) 216 #define ID_AA64PFR0_FEAT_RME_LENGTH U(4) 217 #define ID_AA64PFR0_FEAT_RME_NOT_SUPPORTED U(0) 218 #define ID_AA64PFR0_FEAT_RME_V1 U(1) 219 220 #define ID_AA64PFR0_RAS_SHIFT U(28) 221 #define ID_AA64PFR0_RAS_MASK ULL(0xf) 222 #define ID_AA64PFR0_RAS_NOT_SUPPORTED ULL(0x0) 223 #define ID_AA64PFR0_RAS_LENGTH U(4) 224 225 /* Exception level handling */ 226 #define EL_IMPL_NONE ULL(0) 227 #define EL_IMPL_A64ONLY ULL(1) 228 #define EL_IMPL_A64_A32 ULL(2) 229 230 /* ID_AA64DFR0_EL1.TraceVer definitions */ 231 #define ID_AA64DFR0_TRACEVER_SHIFT U(4) 232 #define ID_AA64DFR0_TRACEVER_MASK ULL(0xf) 233 #define ID_AA64DFR0_TRACEVER_SUPPORTED ULL(1) 234 #define ID_AA64DFR0_TRACEVER_LENGTH U(4) 235 #define ID_AA64DFR0_TRACEFILT_SHIFT U(40) 236 #define ID_AA64DFR0_TRACEFILT_MASK U(0xf) 237 #define ID_AA64DFR0_TRACEFILT_SUPPORTED U(1) 238 #define ID_AA64DFR0_TRACEFILT_LENGTH U(4) 239 #define ID_AA64DFR0_PMUVER_LENGTH U(4) 240 #define ID_AA64DFR0_PMUVER_SHIFT U(8) 241 #define ID_AA64DFR0_PMUVER_MASK U(0xf) 242 #define ID_AA64DFR0_PMUVER_PMUV3 U(1) 243 #define ID_AA64DFR0_PMUVER_PMUV3P7 U(7) 244 #define ID_AA64DFR0_PMUVER_IMP_DEF U(0xf) 245 246 /* ID_AA64DFR0_EL1.SEBEP definitions */ 247 #define ID_AA64DFR0_SEBEP_SHIFT U(24) 248 #define ID_AA64DFR0_SEBEP_MASK ULL(0xf) 249 #define SEBEP_IMPLEMENTED ULL(1) 250 251 /* ID_AA64DFR0_EL1.PMS definitions (for ARMv8.2+) */ 252 #define ID_AA64DFR0_PMS_SHIFT U(32) 253 #define ID_AA64DFR0_PMS_MASK ULL(0xf) 254 #define ID_AA64DFR0_SPE_SUPPORTED ULL(0x1) 255 #define ID_AA64DFR0_SPE_NOT_SUPPORTED ULL(0x0) 256 257 /* ID_AA64DFR0_EL1.TraceBuffer definitions */ 258 #define ID_AA64DFR0_TRACEBUFFER_SHIFT U(44) 259 #define ID_AA64DFR0_TRACEBUFFER_MASK ULL(0xf) 260 #define ID_AA64DFR0_TRACEBUFFER_SUPPORTED ULL(1) 261 262 /* ID_AA64DFR0_EL1.MTPMU definitions (for ARMv8.6+) */ 263 #define ID_AA64DFR0_MTPMU_SHIFT U(48) 264 #define ID_AA64DFR0_MTPMU_MASK ULL(0xf) 265 #define ID_AA64DFR0_MTPMU_SUPPORTED ULL(1) 266 #define ID_AA64DFR0_MTPMU_DISABLED ULL(15) 267 268 /* ID_AA64DFR0_EL1.BRBE definitions */ 269 #define ID_AA64DFR0_BRBE_SHIFT U(52) 270 #define ID_AA64DFR0_BRBE_MASK ULL(0xf) 271 #define ID_AA64DFR0_BRBE_SUPPORTED ULL(1) 272 273 /* ID_AA64DFR1_EL1 definitions */ 274 #define ID_AA64DFR1_EBEP_SHIFT U(48) 275 #define ID_AA64DFR1_EBEP_MASK ULL(0xf) 276 #define EBEP_IMPLEMENTED ULL(1) 277 278 /* ID_AA64ISAR0_EL1 definitions */ 279 #define ID_AA64ISAR0_RNDR_SHIFT U(60) 280 #define ID_AA64ISAR0_RNDR_MASK ULL(0xf) 281 282 /* ID_AA64ISAR1_EL1 definitions */ 283 #define ID_AA64ISAR1_EL1 S3_0_C0_C6_1 284 285 #define ID_AA64ISAR1_GPI_SHIFT U(28) 286 #define ID_AA64ISAR1_GPI_MASK ULL(0xf) 287 #define ID_AA64ISAR1_GPA_SHIFT U(24) 288 #define ID_AA64ISAR1_GPA_MASK ULL(0xf) 289 290 #define ID_AA64ISAR1_API_SHIFT U(8) 291 #define ID_AA64ISAR1_API_MASK ULL(0xf) 292 #define ID_AA64ISAR1_APA_SHIFT U(4) 293 #define ID_AA64ISAR1_APA_MASK ULL(0xf) 294 295 #define ID_AA64ISAR1_SB_SHIFT U(36) 296 #define ID_AA64ISAR1_SB_MASK ULL(0xf) 297 #define ID_AA64ISAR1_SB_SUPPORTED ULL(0x1) 298 #define ID_AA64ISAR1_SB_NOT_SUPPORTED ULL(0x0) 299 300 /* ID_AA64ISAR2_EL1 definitions */ 301 #define ID_AA64ISAR2_EL1 S3_0_C0_C6_2 302 303 /* ID_AA64PFR2_EL1 definitions */ 304 #define ID_AA64PFR2_EL1 S3_0_C0_C4_2 305 306 #define ID_AA64ISAR2_GPA3_SHIFT U(8) 307 #define ID_AA64ISAR2_GPA3_MASK ULL(0xf) 308 309 #define ID_AA64ISAR2_APA3_SHIFT U(12) 310 #define ID_AA64ISAR2_APA3_MASK ULL(0xf) 311 312 /* ID_AA64MMFR0_EL1 definitions */ 313 #define ID_AA64MMFR0_EL1_PARANGE_SHIFT U(0) 314 #define ID_AA64MMFR0_EL1_PARANGE_MASK ULL(0xf) 315 316 #define PARANGE_0000 U(32) 317 #define PARANGE_0001 U(36) 318 #define PARANGE_0010 U(40) 319 #define PARANGE_0011 U(42) 320 #define PARANGE_0100 U(44) 321 #define PARANGE_0101 U(48) 322 #define PARANGE_0110 U(52) 323 324 #define ID_AA64MMFR0_EL1_ECV_SHIFT U(60) 325 #define ID_AA64MMFR0_EL1_ECV_MASK ULL(0xf) 326 #define ID_AA64MMFR0_EL1_ECV_NOT_SUPPORTED ULL(0x0) 327 #define ID_AA64MMFR0_EL1_ECV_SUPPORTED ULL(0x1) 328 #define ID_AA64MMFR0_EL1_ECV_SELF_SYNCH ULL(0x2) 329 330 #define ID_AA64MMFR0_EL1_FGT_SHIFT U(56) 331 #define ID_AA64MMFR0_EL1_FGT_MASK ULL(0xf) 332 #define ID_AA64MMFR0_EL1_FGT_SUPPORTED ULL(0x1) 333 #define ID_AA64MMFR0_EL1_FGT_NOT_SUPPORTED ULL(0x0) 334 335 #define ID_AA64MMFR0_EL1_TGRAN4_SHIFT U(28) 336 #define ID_AA64MMFR0_EL1_TGRAN4_MASK ULL(0xf) 337 #define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED ULL(0x0) 338 #define ID_AA64MMFR0_EL1_TGRAN4_52B_SUPPORTED ULL(0x1) 339 #define ID_AA64MMFR0_EL1_TGRAN4_NOT_SUPPORTED ULL(0xf) 340 341 #define ID_AA64MMFR0_EL1_TGRAN64_SHIFT U(24) 342 #define ID_AA64MMFR0_EL1_TGRAN64_MASK ULL(0xf) 343 #define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED ULL(0x0) 344 #define ID_AA64MMFR0_EL1_TGRAN64_NOT_SUPPORTED ULL(0xf) 345 346 #define ID_AA64MMFR0_EL1_TGRAN16_SHIFT U(20) 347 #define ID_AA64MMFR0_EL1_TGRAN16_MASK ULL(0xf) 348 #define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED ULL(0x1) 349 #define ID_AA64MMFR0_EL1_TGRAN16_NOT_SUPPORTED ULL(0x0) 350 #define ID_AA64MMFR0_EL1_TGRAN16_52B_SUPPORTED ULL(0x2) 351 352 /* ID_AA64MMFR1_EL1 definitions */ 353 #define ID_AA64MMFR1_EL1_TWED_SHIFT U(32) 354 #define ID_AA64MMFR1_EL1_TWED_MASK ULL(0xf) 355 #define ID_AA64MMFR1_EL1_TWED_SUPPORTED ULL(0x1) 356 #define ID_AA64MMFR1_EL1_TWED_NOT_SUPPORTED ULL(0x0) 357 358 #define ID_AA64MMFR1_EL1_PAN_SHIFT U(20) 359 #define ID_AA64MMFR1_EL1_PAN_MASK ULL(0xf) 360 #define ID_AA64MMFR1_EL1_PAN_NOT_SUPPORTED ULL(0x0) 361 #define ID_AA64MMFR1_EL1_PAN_SUPPORTED ULL(0x1) 362 #define ID_AA64MMFR1_EL1_PAN2_SUPPORTED ULL(0x2) 363 #define ID_AA64MMFR1_EL1_PAN3_SUPPORTED ULL(0x3) 364 365 #define ID_AA64MMFR1_EL1_VHE_SHIFT U(8) 366 #define ID_AA64MMFR1_EL1_VHE_MASK ULL(0xf) 367 368 #define ID_AA64MMFR1_EL1_HCX_SHIFT U(40) 369 #define ID_AA64MMFR1_EL1_HCX_MASK ULL(0xf) 370 #define ID_AA64MMFR1_EL1_HCX_SUPPORTED ULL(0x1) 371 #define ID_AA64MMFR1_EL1_HCX_NOT_SUPPORTED ULL(0x0) 372 373 /* ID_AA64MMFR2_EL1 definitions */ 374 #define ID_AA64MMFR2_EL1 S3_0_C0_C7_2 375 376 #define ID_AA64MMFR2_EL1_ST_SHIFT U(28) 377 #define ID_AA64MMFR2_EL1_ST_MASK ULL(0xf) 378 379 #define ID_AA64MMFR2_EL1_CCIDX_SHIFT U(20) 380 #define ID_AA64MMFR2_EL1_CCIDX_MASK ULL(0xf) 381 #define ID_AA64MMFR2_EL1_CCIDX_LENGTH U(4) 382 383 #define ID_AA64MMFR2_EL1_UAO_SHIFT U(4) 384 #define ID_AA64MMFR2_EL1_UAO_MASK ULL(0xf) 385 386 #define ID_AA64MMFR2_EL1_CNP_SHIFT U(0) 387 #define ID_AA64MMFR2_EL1_CNP_MASK ULL(0xf) 388 389 #define ID_AA64MMFR2_EL1_NV_SHIFT U(24) 390 #define ID_AA64MMFR2_EL1_NV_MASK ULL(0xf) 391 #define ID_AA64MMFR2_EL1_NV_NOT_SUPPORTED ULL(0x0) 392 #define ID_AA64MMFR2_EL1_NV_SUPPORTED ULL(0x1) 393 #define ID_AA64MMFR2_EL1_NV2_SUPPORTED ULL(0x2) 394 395 /* ID_AA64MMFR3_EL1 definitions */ 396 #define ID_AA64MMFR3_EL1 S3_0_C0_C7_3 397 398 #define ID_AA64MMFR3_EL1_S2POE_SHIFT U(20) 399 #define ID_AA64MMFR3_EL1_S2POE_MASK ULL(0xf) 400 401 #define ID_AA64MMFR3_EL1_S1POE_SHIFT U(16) 402 #define ID_AA64MMFR3_EL1_S1POE_MASK ULL(0xf) 403 404 #define ID_AA64MMFR3_EL1_S2PIE_SHIFT U(12) 405 #define ID_AA64MMFR3_EL1_S2PIE_MASK ULL(0xf) 406 407 #define ID_AA64MMFR3_EL1_S1PIE_SHIFT U(8) 408 #define ID_AA64MMFR3_EL1_S1PIE_MASK ULL(0xf) 409 410 #define ID_AA64MMFR3_EL1_TCRX_SHIFT U(0) 411 #define ID_AA64MMFR3_EL1_TCRX_MASK ULL(0xf) 412 413 /* ID_AA64PFR1_EL1 definitions */ 414 415 #define ID_AA64PFR1_EL1_BT_SHIFT U(0) 416 #define ID_AA64PFR1_EL1_BT_MASK ULL(0xf) 417 #define BTI_IMPLEMENTED ULL(1) /* The BTI mechanism is implemented */ 418 419 #define ID_AA64PFR1_EL1_SSBS_SHIFT U(4) 420 #define ID_AA64PFR1_EL1_SSBS_MASK ULL(0xf) 421 #define SSBS_UNAVAILABLE ULL(0) /* No architectural SSBS support */ 422 423 #define ID_AA64PFR1_EL1_MTE_SHIFT U(8) 424 #define ID_AA64PFR1_EL1_MTE_MASK ULL(0xf) 425 426 #define ID_AA64PFR1_EL1_RNDR_TRAP_SHIFT U(28) 427 #define ID_AA64PFR1_EL1_RNDR_TRAP_MASK U(0xf) 428 429 #define ID_AA64PFR1_EL1_NMI_SHIFT U(36) 430 #define ID_AA64PFR1_EL1_NMI_MASK ULL(0xf) 431 #define NMI_IMPLEMENTED ULL(1) 432 433 #define ID_AA64PFR1_EL1_GCS_SHIFT U(44) 434 #define ID_AA64PFR1_EL1_GCS_MASK ULL(0xf) 435 #define GCS_IMPLEMENTED ULL(1) 436 437 #define ID_AA64PFR1_EL1_RNG_TRAP_SUPPORTED ULL(0x1) 438 #define ID_AA64PFR1_EL1_RNG_TRAP_NOT_SUPPORTED ULL(0x0) 439 440 /* ID_AA64PFR2_EL1 definitions */ 441 #define ID_AA64PFR2_EL1_MTEPERM_SHIFT U(0) 442 #define ID_AA64PFR2_EL1_MTEPERM_MASK ULL(0xf) 443 444 #define ID_AA64PFR2_EL1_MTESTOREONLY_SHIFT U(4) 445 #define ID_AA64PFR2_EL1_MTESTOREONLY_MASK ULL(0xf) 446 447 #define ID_AA64PFR2_EL1_MTEFAR_SHIFT U(8) 448 #define ID_AA64PFR2_EL1_MTEFAR_MASK ULL(0xf) 449 450 #define VDISR_EL2 S3_4_C12_C1_1 451 #define VSESR_EL2 S3_4_C5_C2_3 452 453 /* Memory Tagging Extension is not implemented */ 454 #define MTE_UNIMPLEMENTED U(0) 455 /* FEAT_MTE: MTE instructions accessible at EL0 are implemented */ 456 #define MTE_IMPLEMENTED_EL0 U(1) 457 /* FEAT_MTE2: Full MTE is implemented */ 458 #define MTE_IMPLEMENTED_ELX U(2) 459 /* 460 * FEAT_MTE3: MTE is implemented with support for 461 * asymmetric Tag Check Fault handling 462 */ 463 #define MTE_IMPLEMENTED_ASY U(3) 464 465 #define ID_AA64PFR1_MPAM_FRAC_SHIFT ULL(16) 466 #define ID_AA64PFR1_MPAM_FRAC_MASK ULL(0xf) 467 468 #define ID_AA64PFR1_EL1_SME_SHIFT U(24) 469 #define ID_AA64PFR1_EL1_SME_MASK ULL(0xf) 470 #define ID_AA64PFR1_EL1_SME_WIDTH U(4) 471 #define ID_AA64PFR1_EL1_SME_NOT_SUPPORTED ULL(0x0) 472 #define ID_AA64PFR1_EL1_SME_SUPPORTED ULL(0x1) 473 #define ID_AA64PFR1_EL1_SME2_SUPPORTED ULL(0x2) 474 475 /* ID_PFR1_EL1 definitions */ 476 #define ID_PFR1_VIRTEXT_SHIFT U(12) 477 #define ID_PFR1_VIRTEXT_MASK U(0xf) 478 #define GET_VIRT_EXT(id) (((id) >> ID_PFR1_VIRTEXT_SHIFT) \ 479 & ID_PFR1_VIRTEXT_MASK) 480 481 /* SCTLR definitions */ 482 #define SCTLR_EL2_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ 483 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \ 484 (U(1) << 11) | (U(1) << 5) | (U(1) << 4)) 485 486 #define SCTLR_EL1_RES1 ((UL(1) << 29) | (UL(1) << 28) | (UL(1) << 23) | \ 487 (UL(1) << 22) | (UL(1) << 20) | (UL(1) << 11)) 488 489 #define SCTLR_AARCH32_EL1_RES1 \ 490 ((U(1) << 23) | (U(1) << 22) | (U(1) << 11) | \ 491 (U(1) << 4) | (U(1) << 3)) 492 493 #define SCTLR_EL3_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ 494 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \ 495 (U(1) << 11) | (U(1) << 5) | (U(1) << 4)) 496 497 #define SCTLR_M_BIT (ULL(1) << 0) 498 #define SCTLR_A_BIT (ULL(1) << 1) 499 #define SCTLR_C_BIT (ULL(1) << 2) 500 #define SCTLR_SA_BIT (ULL(1) << 3) 501 #define SCTLR_SA0_BIT (ULL(1) << 4) 502 #define SCTLR_CP15BEN_BIT (ULL(1) << 5) 503 #define SCTLR_nAA_BIT (ULL(1) << 6) 504 #define SCTLR_ITD_BIT (ULL(1) << 7) 505 #define SCTLR_SED_BIT (ULL(1) << 8) 506 #define SCTLR_UMA_BIT (ULL(1) << 9) 507 #define SCTLR_EnRCTX_BIT (ULL(1) << 10) 508 #define SCTLR_EOS_BIT (ULL(1) << 11) 509 #define SCTLR_I_BIT (ULL(1) << 12) 510 #define SCTLR_EnDB_BIT (ULL(1) << 13) 511 #define SCTLR_DZE_BIT (ULL(1) << 14) 512 #define SCTLR_UCT_BIT (ULL(1) << 15) 513 #define SCTLR_NTWI_BIT (ULL(1) << 16) 514 #define SCTLR_NTWE_BIT (ULL(1) << 18) 515 #define SCTLR_WXN_BIT (ULL(1) << 19) 516 #define SCTLR_TSCXT_BIT (ULL(1) << 20) 517 #define SCTLR_IESB_BIT (ULL(1) << 21) 518 #define SCTLR_EIS_BIT (ULL(1) << 22) 519 #define SCTLR_SPAN_BIT (ULL(1) << 23) 520 #define SCTLR_E0E_BIT (ULL(1) << 24) 521 #define SCTLR_EE_BIT (ULL(1) << 25) 522 #define SCTLR_UCI_BIT (ULL(1) << 26) 523 #define SCTLR_EnDA_BIT (ULL(1) << 27) 524 #define SCTLR_nTLSMD_BIT (ULL(1) << 28) 525 #define SCTLR_LSMAOE_BIT (ULL(1) << 29) 526 #define SCTLR_EnIB_BIT (ULL(1) << 30) 527 #define SCTLR_EnIA_BIT (ULL(1) << 31) 528 #define SCTLR_BT0_BIT (ULL(1) << 35) 529 #define SCTLR_BT1_BIT (ULL(1) << 36) 530 #define SCTLR_BT_BIT (ULL(1) << 36) 531 #define SCTLR_ITFSB_BIT (ULL(1) << 37) 532 #define SCTLR_TCF0_SHIFT U(38) 533 #define SCTLR_TCF0_MASK ULL(3) 534 #define SCTLR_ENTP2_BIT (ULL(1) << 60) 535 #define SCTLR_SPINTMASK_BIT (ULL(1) << 62) 536 537 /* Tag Check Faults in EL0 have no effect on the PE */ 538 #define SCTLR_TCF0_NO_EFFECT U(0) 539 /* Tag Check Faults in EL0 cause a synchronous exception */ 540 #define SCTLR_TCF0_SYNC U(1) 541 /* Tag Check Faults in EL0 are asynchronously accumulated */ 542 #define SCTLR_TCF0_ASYNC U(2) 543 /* 544 * Tag Check Faults in EL0 cause a synchronous exception on reads, 545 * and are asynchronously accumulated on writes 546 */ 547 #define SCTLR_TCF0_SYNCR_ASYNCW U(3) 548 549 #define SCTLR_TCF_SHIFT U(40) 550 #define SCTLR_TCF_MASK ULL(3) 551 552 /* Tag Check Faults in EL1 have no effect on the PE */ 553 #define SCTLR_TCF_NO_EFFECT U(0) 554 /* Tag Check Faults in EL1 cause a synchronous exception */ 555 #define SCTLR_TCF_SYNC U(1) 556 /* Tag Check Faults in EL1 are asynchronously accumulated */ 557 #define SCTLR_TCF_ASYNC U(2) 558 /* 559 * Tag Check Faults in EL1 cause a synchronous exception on reads, 560 * and are asynchronously accumulated on writes 561 */ 562 #define SCTLR_TCF_SYNCR_ASYNCW U(3) 563 564 #define SCTLR_ATA0_BIT (ULL(1) << 42) 565 #define SCTLR_ATA_BIT (ULL(1) << 43) 566 #define SCTLR_DSSBS_SHIFT U(44) 567 #define SCTLR_DSSBS_BIT (ULL(1) << SCTLR_DSSBS_SHIFT) 568 #define SCTLR_TWEDEn_BIT (ULL(1) << 45) 569 #define SCTLR_TWEDEL_SHIFT U(46) 570 #define SCTLR_TWEDEL_MASK ULL(0xf) 571 #define SCTLR_EnASR_BIT (ULL(1) << 54) 572 #define SCTLR_EnAS0_BIT (ULL(1) << 55) 573 #define SCTLR_EnALS_BIT (ULL(1) << 56) 574 #define SCTLR_EPAN_BIT (ULL(1) << 57) 575 #define SCTLR_RESET_VAL SCTLR_EL3_RES1 576 577 /* CPACR_EL1 definitions */ 578 #define CPACR_EL1_FPEN(x) ((x) << 20) 579 #define CPACR_EL1_FP_TRAP_EL0 UL(0x1) 580 #define CPACR_EL1_FP_TRAP_ALL UL(0x2) 581 #define CPACR_EL1_FP_TRAP_NONE UL(0x3) 582 #define CPACR_EL1_SMEN_SHIFT U(24) 583 #define CPACR_EL1_SMEN_MASK ULL(0x3) 584 585 /* SCR definitions */ 586 #define SCR_RES1_BITS ((U(1) << 4) | (U(1) << 5)) 587 #define SCR_NSE_SHIFT U(62) 588 #define SCR_NSE_BIT (ULL(1) << SCR_NSE_SHIFT) 589 #define SCR_GPF_BIT (UL(1) << 48) 590 #define SCR_TWEDEL_SHIFT U(30) 591 #define SCR_TWEDEL_MASK ULL(0xf) 592 #define SCR_PIEN_BIT (UL(1) << 45) 593 #define SCR_TCR2EN_BIT (UL(1) << 43) 594 #define SCR_TRNDR_BIT (UL(1) << 40) 595 #define SCR_GCSEn_BIT (UL(1) << 39) 596 #define SCR_HXEn_BIT (UL(1) << 38) 597 #define SCR_ENTP2_SHIFT U(41) 598 #define SCR_ENTP2_BIT (UL(1) << SCR_ENTP2_SHIFT) 599 #define SCR_AMVOFFEN_SHIFT U(35) 600 #define SCR_AMVOFFEN_BIT (UL(1) << SCR_AMVOFFEN_SHIFT) 601 #define SCR_TWEDEn_BIT (UL(1) << 29) 602 #define SCR_ECVEN_BIT (UL(1) << 28) 603 #define SCR_FGTEN_BIT (UL(1) << 27) 604 #define SCR_ATA_BIT (UL(1) << 26) 605 #define SCR_EnSCXT_BIT (UL(1) << 25) 606 #define SCR_FIEN_BIT (UL(1) << 21) 607 #define SCR_EEL2_BIT (UL(1) << 18) 608 #define SCR_API_BIT (UL(1) << 17) 609 #define SCR_APK_BIT (UL(1) << 16) 610 #define SCR_TERR_BIT (UL(1) << 15) 611 #define SCR_TWE_BIT (UL(1) << 13) 612 #define SCR_TWI_BIT (UL(1) << 12) 613 #define SCR_ST_BIT (UL(1) << 11) 614 #define SCR_RW_BIT (UL(1) << 10) 615 #define SCR_SIF_BIT (UL(1) << 9) 616 #define SCR_HCE_BIT (UL(1) << 8) 617 #define SCR_SMD_BIT (UL(1) << 7) 618 #define SCR_EA_BIT (UL(1) << 3) 619 #define SCR_FIQ_BIT (UL(1) << 2) 620 #define SCR_IRQ_BIT (UL(1) << 1) 621 #define SCR_NS_BIT (UL(1) << 0) 622 #define SCR_VALID_BIT_MASK U(0x24000002F8F) 623 #define SCR_RESET_VAL SCR_RES1_BITS 624 625 /* MDCR_EL3 definitions */ 626 #define MDCR_EnPMSN_BIT (ULL(1) << 36) 627 #define MDCR_MPMX_BIT (ULL(1) << 35) 628 #define MDCR_MCCD_BIT (ULL(1) << 34) 629 #define MDCR_SBRBE_SHIFT U(32) 630 #define MDCR_SBRBE_MASK ULL(0x3) 631 #define MDCR_NSTB(x) ((x) << 24) 632 #define MDCR_NSTB_EL1 ULL(0x3) 633 #define MDCR_NSTBE_BIT (ULL(1) << 26) 634 #define MDCR_MTPME_BIT (ULL(1) << 28) 635 #define MDCR_TDCC_BIT (ULL(1) << 27) 636 #define MDCR_SCCD_BIT (ULL(1) << 23) 637 #define MDCR_EPMAD_BIT (ULL(1) << 21) 638 #define MDCR_EDAD_BIT (ULL(1) << 20) 639 #define MDCR_TTRF_BIT (ULL(1) << 19) 640 #define MDCR_STE_BIT (ULL(1) << 18) 641 #define MDCR_SPME_BIT (ULL(1) << 17) 642 #define MDCR_SDD_BIT (ULL(1) << 16) 643 #define MDCR_SPD32(x) ((x) << 14) 644 #define MDCR_SPD32_LEGACY ULL(0x0) 645 #define MDCR_SPD32_DISABLE ULL(0x2) 646 #define MDCR_SPD32_ENABLE ULL(0x3) 647 #define MDCR_NSPB(x) ((x) << 12) 648 #define MDCR_NSPB_EL1 ULL(0x3) 649 #define MDCR_NSPBE_BIT (ULL(1) << 11) 650 #define MDCR_TDOSA_BIT (ULL(1) << 10) 651 #define MDCR_TDA_BIT (ULL(1) << 9) 652 #define MDCR_TPM_BIT (ULL(1) << 6) 653 #define MDCR_EL3_RESET_VAL MDCR_MTPME_BIT 654 655 /* MDCR_EL2 definitions */ 656 #define MDCR_EL2_MTPME (U(1) << 28) 657 #define MDCR_EL2_HLP_BIT (U(1) << 26) 658 #define MDCR_EL2_E2TB(x) ((x) << 24) 659 #define MDCR_EL2_E2TB_EL1 U(0x3) 660 #define MDCR_EL2_HCCD_BIT (U(1) << 23) 661 #define MDCR_EL2_TTRF (U(1) << 19) 662 #define MDCR_EL2_HPMD_BIT (U(1) << 17) 663 #define MDCR_EL2_TPMS (U(1) << 14) 664 #define MDCR_EL2_E2PB(x) ((x) << 12) 665 #define MDCR_EL2_E2PB_EL1 U(0x3) 666 #define MDCR_EL2_TDRA_BIT (U(1) << 11) 667 #define MDCR_EL2_TDOSA_BIT (U(1) << 10) 668 #define MDCR_EL2_TDA_BIT (U(1) << 9) 669 #define MDCR_EL2_TDE_BIT (U(1) << 8) 670 #define MDCR_EL2_HPME_BIT (U(1) << 7) 671 #define MDCR_EL2_TPM_BIT (U(1) << 6) 672 #define MDCR_EL2_TPMCR_BIT (U(1) << 5) 673 #define MDCR_EL2_HPMN_MASK U(0x1f) 674 #define MDCR_EL2_RESET_VAL U(0x0) 675 676 /* HSTR_EL2 definitions */ 677 #define HSTR_EL2_RESET_VAL U(0x0) 678 #define HSTR_EL2_T_MASK U(0xff) 679 680 /* CNTHP_CTL_EL2 definitions */ 681 #define CNTHP_CTL_ENABLE_BIT (U(1) << 0) 682 #define CNTHP_CTL_RESET_VAL U(0x0) 683 684 /* VTTBR_EL2 definitions */ 685 #define VTTBR_RESET_VAL ULL(0x0) 686 #define VTTBR_VMID_MASK ULL(0xff) 687 #define VTTBR_VMID_SHIFT U(48) 688 #define VTTBR_BADDR_MASK ULL(0xffffffffffff) 689 #define VTTBR_BADDR_SHIFT U(0) 690 691 /* HCR definitions */ 692 #define HCR_RESET_VAL ULL(0x0) 693 #define HCR_AMVOFFEN_SHIFT U(51) 694 #define HCR_AMVOFFEN_BIT (ULL(1) << HCR_AMVOFFEN_SHIFT) 695 #define HCR_TEA_BIT (ULL(1) << 47) 696 #define HCR_API_BIT (ULL(1) << 41) 697 #define HCR_APK_BIT (ULL(1) << 40) 698 #define HCR_E2H_BIT (ULL(1) << 34) 699 #define HCR_HCD_BIT (ULL(1) << 29) 700 #define HCR_TGE_BIT (ULL(1) << 27) 701 #define HCR_RW_SHIFT U(31) 702 #define HCR_RW_BIT (ULL(1) << HCR_RW_SHIFT) 703 #define HCR_TWE_BIT (ULL(1) << 14) 704 #define HCR_TWI_BIT (ULL(1) << 13) 705 #define HCR_AMO_BIT (ULL(1) << 5) 706 #define HCR_IMO_BIT (ULL(1) << 4) 707 #define HCR_FMO_BIT (ULL(1) << 3) 708 709 /* ISR definitions */ 710 #define ISR_A_SHIFT U(8) 711 #define ISR_I_SHIFT U(7) 712 #define ISR_F_SHIFT U(6) 713 714 /* CNTHCTL_EL2 definitions */ 715 #define CNTHCTL_RESET_VAL U(0x0) 716 #define EVNTEN_BIT (U(1) << 2) 717 #define EL1PCEN_BIT (U(1) << 1) 718 #define EL1PCTEN_BIT (U(1) << 0) 719 720 /* CNTKCTL_EL1 definitions */ 721 #define EL0PTEN_BIT (U(1) << 9) 722 #define EL0VTEN_BIT (U(1) << 8) 723 #define EL0PCTEN_BIT (U(1) << 0) 724 #define EL0VCTEN_BIT (U(1) << 1) 725 #define EVNTEN_BIT (U(1) << 2) 726 #define EVNTDIR_BIT (U(1) << 3) 727 #define EVNTI_SHIFT U(4) 728 #define EVNTI_MASK U(0xf) 729 730 /* CPTR_EL3 definitions */ 731 #define TCPAC_BIT (U(1) << 31) 732 #define TAM_SHIFT U(30) 733 #define TAM_BIT (U(1) << TAM_SHIFT) 734 #define TTA_BIT (U(1) << 20) 735 #define ESM_BIT (U(1) << 12) 736 #define TFP_BIT (U(1) << 10) 737 #define CPTR_EZ_BIT (U(1) << 8) 738 #define CPTR_EL3_RESET_VAL ((TCPAC_BIT | TAM_BIT | TTA_BIT | TFP_BIT) & \ 739 ~(CPTR_EZ_BIT | ESM_BIT)) 740 741 /* CPTR_EL2 definitions */ 742 #define CPTR_EL2_RES1 ((U(1) << 13) | (U(1) << 12) | (U(0x3ff))) 743 #define CPTR_EL2_TCPAC_BIT (U(1) << 31) 744 #define CPTR_EL2_TAM_SHIFT U(30) 745 #define CPTR_EL2_TAM_BIT (U(1) << CPTR_EL2_TAM_SHIFT) 746 #define CPTR_EL2_SMEN_MASK ULL(0x3) 747 #define CPTR_EL2_SMEN_SHIFT U(24) 748 #define CPTR_EL2_TTA_BIT (U(1) << 20) 749 #define CPTR_EL2_TSM_BIT (U(1) << 12) 750 #define CPTR_EL2_TFP_BIT (U(1) << 10) 751 #define CPTR_EL2_TZ_BIT (U(1) << 8) 752 #define CPTR_EL2_RESET_VAL CPTR_EL2_RES1 753 754 /* VTCR_EL2 definitions */ 755 #define VTCR_RESET_VAL U(0x0) 756 #define VTCR_EL2_MSA (U(1) << 31) 757 758 /* CPSR/SPSR definitions */ 759 #define DAIF_FIQ_BIT (U(1) << 0) 760 #define DAIF_IRQ_BIT (U(1) << 1) 761 #define DAIF_ABT_BIT (U(1) << 2) 762 #define DAIF_DBG_BIT (U(1) << 3) 763 #define SPSR_V_BIT (U(1) << 28) 764 #define SPSR_C_BIT (U(1) << 29) 765 #define SPSR_Z_BIT (U(1) << 30) 766 #define SPSR_N_BIT (U(1) << 31) 767 #define SPSR_DAIF_SHIFT U(6) 768 #define SPSR_DAIF_MASK U(0xf) 769 770 #define SPSR_AIF_SHIFT U(6) 771 #define SPSR_AIF_MASK U(0x7) 772 773 #define SPSR_E_SHIFT U(9) 774 #define SPSR_E_MASK U(0x1) 775 #define SPSR_E_LITTLE U(0x0) 776 #define SPSR_E_BIG U(0x1) 777 778 #define SPSR_T_SHIFT U(5) 779 #define SPSR_T_MASK U(0x1) 780 #define SPSR_T_ARM U(0x0) 781 #define SPSR_T_THUMB U(0x1) 782 783 #define SPSR_M_SHIFT U(4) 784 #define SPSR_M_MASK U(0x1) 785 #define SPSR_M_AARCH64 U(0x0) 786 #define SPSR_M_AARCH32 U(0x1) 787 #define SPSR_M_EL1H U(0x5) 788 #define SPSR_M_EL2H U(0x9) 789 790 #define SPSR_EL_SHIFT U(2) 791 #define SPSR_EL_WIDTH U(2) 792 793 #define SPSR_BTYPE_SHIFT_AARCH64 U(10) 794 #define SPSR_BTYPE_MASK_AARCH64 U(0x3) 795 #define SPSR_SSBS_SHIFT_AARCH64 U(12) 796 #define SPSR_SSBS_BIT_AARCH64 (ULL(1) << SPSR_SSBS_SHIFT_AARCH64) 797 #define SPSR_SSBS_SHIFT_AARCH32 U(23) 798 #define SPSR_SSBS_BIT_AARCH32 (ULL(1) << SPSR_SSBS_SHIFT_AARCH32) 799 #define SPSR_ALLINT_BIT_AARCH64 BIT_64(13) 800 #define SPSR_IL_BIT BIT_64(20) 801 #define SPSR_SS_BIT BIT_64(21) 802 #define SPSR_PAN_BIT BIT_64(22) 803 #define SPSR_UAO_BIT_AARCH64 BIT_64(23) 804 #define SPSR_DIT_BIT BIT(24) 805 #define SPSR_TCO_BIT_AARCH64 BIT_64(25) 806 #define SPSR_PM_BIT_AARCH64 BIT_64(32) 807 #define SPSR_PPEND_BIT BIT(33) 808 #define SPSR_EXLOCK_BIT_AARCH64 BIT_64(34) 809 #define SPSR_NZCV (SPSR_V_BIT | SPSR_C_BIT | SPSR_Z_BIT | SPSR_N_BIT) 810 811 #define DISABLE_ALL_EXCEPTIONS \ 812 (DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT | DAIF_DBG_BIT) 813 #define DISABLE_INTERRUPTS (DAIF_FIQ_BIT | DAIF_IRQ_BIT) 814 815 /* 816 * RMR_EL3 definitions 817 */ 818 #define RMR_EL3_RR_BIT (U(1) << 1) 819 #define RMR_EL3_AA64_BIT (U(1) << 0) 820 821 /* 822 * HI-VECTOR address for AArch32 state 823 */ 824 #define HI_VECTOR_BASE U(0xFFFF0000) 825 826 /* 827 * TCR definitions 828 */ 829 #define TCR_EL3_RES1 ((ULL(1) << 31) | (ULL(1) << 23)) 830 #define TCR_EL2_RES1 ((ULL(1) << 31) | (ULL(1) << 23)) 831 #define TCR_EL1_IPS_SHIFT U(32) 832 #define TCR_EL2_PS_SHIFT U(16) 833 #define TCR_EL3_PS_SHIFT U(16) 834 835 #define TCR_TxSZ_MIN ULL(16) 836 #define TCR_TxSZ_MAX ULL(39) 837 #define TCR_TxSZ_MAX_TTST ULL(48) 838 839 #define TCR_T0SZ_SHIFT U(0) 840 #define TCR_T1SZ_SHIFT U(16) 841 842 /* (internal) physical address size bits in EL3/EL1 */ 843 #define TCR_PS_BITS_4GB ULL(0x0) 844 #define TCR_PS_BITS_64GB ULL(0x1) 845 #define TCR_PS_BITS_1TB ULL(0x2) 846 #define TCR_PS_BITS_4TB ULL(0x3) 847 #define TCR_PS_BITS_16TB ULL(0x4) 848 #define TCR_PS_BITS_256TB ULL(0x5) 849 850 #define ADDR_MASK_48_TO_63 ULL(0xFFFF000000000000) 851 #define ADDR_MASK_44_TO_47 ULL(0x0000F00000000000) 852 #define ADDR_MASK_42_TO_43 ULL(0x00000C0000000000) 853 #define ADDR_MASK_40_TO_41 ULL(0x0000030000000000) 854 #define ADDR_MASK_36_TO_39 ULL(0x000000F000000000) 855 #define ADDR_MASK_32_TO_35 ULL(0x0000000F00000000) 856 857 #define TCR_RGN_INNER_NC (ULL(0x0) << 8) 858 #define TCR_RGN_INNER_WBA (ULL(0x1) << 8) 859 #define TCR_RGN_INNER_WT (ULL(0x2) << 8) 860 #define TCR_RGN_INNER_WBNA (ULL(0x3) << 8) 861 862 #define TCR_RGN_OUTER_NC (ULL(0x0) << 10) 863 #define TCR_RGN_OUTER_WBA (ULL(0x1) << 10) 864 #define TCR_RGN_OUTER_WT (ULL(0x2) << 10) 865 #define TCR_RGN_OUTER_WBNA (ULL(0x3) << 10) 866 867 #define TCR_SH_NON_SHAREABLE (ULL(0x0) << 12) 868 #define TCR_SH_OUTER_SHAREABLE (ULL(0x2) << 12) 869 #define TCR_SH_INNER_SHAREABLE (ULL(0x3) << 12) 870 871 #define TCR_RGN1_INNER_NC (ULL(0x0) << 24) 872 #define TCR_RGN1_INNER_WBA (ULL(0x1) << 24) 873 #define TCR_RGN1_INNER_WT (ULL(0x2) << 24) 874 #define TCR_RGN1_INNER_WBNA (ULL(0x3) << 24) 875 876 #define TCR_RGN1_OUTER_NC (ULL(0x0) << 26) 877 #define TCR_RGN1_OUTER_WBA (ULL(0x1) << 26) 878 #define TCR_RGN1_OUTER_WT (ULL(0x2) << 26) 879 #define TCR_RGN1_OUTER_WBNA (ULL(0x3) << 26) 880 881 #define TCR_SH1_NON_SHAREABLE (ULL(0x0) << 28) 882 #define TCR_SH1_OUTER_SHAREABLE (ULL(0x2) << 28) 883 #define TCR_SH1_INNER_SHAREABLE (ULL(0x3) << 28) 884 885 #define TCR_TG0_SHIFT U(14) 886 #define TCR_TG0_MASK ULL(3) 887 #define TCR_TG0_4K (ULL(0) << TCR_TG0_SHIFT) 888 #define TCR_TG0_64K (ULL(1) << TCR_TG0_SHIFT) 889 #define TCR_TG0_16K (ULL(2) << TCR_TG0_SHIFT) 890 891 #define TCR_TG1_SHIFT U(30) 892 #define TCR_TG1_MASK ULL(3) 893 #define TCR_TG1_16K (ULL(1) << TCR_TG1_SHIFT) 894 #define TCR_TG1_4K (ULL(2) << TCR_TG1_SHIFT) 895 #define TCR_TG1_64K (ULL(3) << TCR_TG1_SHIFT) 896 897 #define TCR_EPD0_BIT (ULL(1) << 7) 898 #define TCR_EPD1_BIT (ULL(1) << 23) 899 900 #define MODE_SP_SHIFT U(0x0) 901 #define MODE_SP_MASK U(0x1) 902 #define MODE_SP_EL0 U(0x0) 903 #define MODE_SP_ELX U(0x1) 904 905 #define MODE_RW_SHIFT U(0x4) 906 #define MODE_RW_MASK U(0x1) 907 #define MODE_RW_64 U(0x0) 908 #define MODE_RW_32 U(0x1) 909 910 #define MODE_EL_SHIFT U(0x2) 911 #define MODE_EL_MASK U(0x3) 912 #define MODE_EL_WIDTH U(0x2) 913 #define MODE_EL3 U(0x3) 914 #define MODE_EL2 U(0x2) 915 #define MODE_EL1 U(0x1) 916 #define MODE_EL0 U(0x0) 917 918 #define MODE32_SHIFT U(0) 919 #define MODE32_MASK U(0xf) 920 #define MODE32_usr U(0x0) 921 #define MODE32_fiq U(0x1) 922 #define MODE32_irq U(0x2) 923 #define MODE32_svc U(0x3) 924 #define MODE32_mon U(0x6) 925 #define MODE32_abt U(0x7) 926 #define MODE32_hyp U(0xa) 927 #define MODE32_und U(0xb) 928 #define MODE32_sys U(0xf) 929 930 #define GET_RW(mode) (((mode) >> MODE_RW_SHIFT) & MODE_RW_MASK) 931 #define GET_EL(mode) (((mode) >> MODE_EL_SHIFT) & MODE_EL_MASK) 932 #define GET_SP(mode) (((mode) >> MODE_SP_SHIFT) & MODE_SP_MASK) 933 #define GET_M32(mode) (((mode) >> MODE32_SHIFT) & MODE32_MASK) 934 935 #define SPSR_64(el, sp, daif) \ 936 (((MODE_RW_64 << MODE_RW_SHIFT) | \ 937 (((el) & MODE_EL_MASK) << MODE_EL_SHIFT) | \ 938 (((sp) & MODE_SP_MASK) << MODE_SP_SHIFT) | \ 939 (((daif) & SPSR_DAIF_MASK) << SPSR_DAIF_SHIFT)) & \ 940 (~(SPSR_SSBS_BIT_AARCH64))) 941 942 #define SPSR_MODE32(mode, isa, endian, aif) \ 943 (((MODE_RW_32 << MODE_RW_SHIFT) | \ 944 (((mode) & MODE32_MASK) << MODE32_SHIFT) | \ 945 (((isa) & SPSR_T_MASK) << SPSR_T_SHIFT) | \ 946 (((endian) & SPSR_E_MASK) << SPSR_E_SHIFT) | \ 947 (((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT)) & \ 948 (~(SPSR_SSBS_BIT_AARCH32))) 949 950 /* 951 * TTBR Definitions 952 */ 953 #define TTBR_CNP_BIT ULL(0x1) 954 955 /* 956 * CTR_EL0 definitions 957 */ 958 #define CTR_CWG_SHIFT U(24) 959 #define CTR_CWG_MASK U(0xf) 960 #define CTR_ERG_SHIFT U(20) 961 #define CTR_ERG_MASK U(0xf) 962 #define CTR_DMINLINE_SHIFT U(16) 963 #define CTR_DMINLINE_MASK U(0xf) 964 #define CTR_L1IP_SHIFT U(14) 965 #define CTR_L1IP_MASK U(0x3) 966 #define CTR_IMINLINE_SHIFT U(0) 967 #define CTR_IMINLINE_MASK U(0xf) 968 969 #define MAX_CACHE_LINE_SIZE U(0x800) /* 2KB */ 970 971 /* Physical timer control register bit fields shifts and masks */ 972 #define CNTP_CTL_ENABLE_SHIFT U(0) 973 #define CNTP_CTL_IMASK_SHIFT U(1) 974 #define CNTP_CTL_ISTATUS_SHIFT U(2) 975 976 #define CNTP_CTL_ENABLE_MASK U(1) 977 #define CNTP_CTL_IMASK_MASK U(1) 978 #define CNTP_CTL_ISTATUS_MASK U(1) 979 980 /* Physical timer control macros */ 981 #define CNTP_CTL_ENABLE_BIT (U(1) << CNTP_CTL_ENABLE_SHIFT) 982 #define CNTP_CTL_IMASK_BIT (U(1) << CNTP_CTL_IMASK_SHIFT) 983 984 /* Exception Syndrome register bits and bobs */ 985 #define ESR_EC_SHIFT U(26) 986 #define ESR_EC_MASK U(0x3f) 987 #define ESR_EC_LENGTH U(6) 988 #define ESR_ISS_SHIFT U(0) 989 #define ESR_ISS_LENGTH U(25) 990 #define ESR_IL_BIT (U(1) << 25) 991 #define EC_UNKNOWN U(0x0) 992 #define EC_WFE_WFI U(0x1) 993 #define EC_AARCH32_CP15_MRC_MCR U(0x3) 994 #define EC_AARCH32_CP15_MRRC_MCRR U(0x4) 995 #define EC_AARCH32_CP14_MRC_MCR U(0x5) 996 #define EC_AARCH32_CP14_LDC_STC U(0x6) 997 #define EC_FP_SIMD U(0x7) 998 #define EC_AARCH32_CP10_MRC U(0x8) 999 #define EC_AARCH32_CP14_MRRC_MCRR U(0xc) 1000 #define EC_ILLEGAL U(0xe) 1001 #define EC_AARCH32_SVC U(0x11) 1002 #define EC_AARCH32_HVC U(0x12) 1003 #define EC_AARCH32_SMC U(0x13) 1004 #define EC_AARCH64_SVC U(0x15) 1005 #define EC_AARCH64_HVC U(0x16) 1006 #define EC_AARCH64_SMC U(0x17) 1007 #define EC_AARCH64_SYS U(0x18) 1008 #define EC_IMP_DEF_EL3 U(0x1f) 1009 #define EC_IABORT_LOWER_EL U(0x20) 1010 #define EC_IABORT_CUR_EL U(0x21) 1011 #define EC_PC_ALIGN U(0x22) 1012 #define EC_DABORT_LOWER_EL U(0x24) 1013 #define EC_DABORT_CUR_EL U(0x25) 1014 #define EC_SP_ALIGN U(0x26) 1015 #define EC_AARCH32_FP U(0x28) 1016 #define EC_AARCH64_FP U(0x2c) 1017 #define EC_SERROR U(0x2f) 1018 #define EC_BRK U(0x3c) 1019 1020 /* 1021 * External Abort bit in Instruction and Data Aborts synchronous exception 1022 * syndromes. 1023 */ 1024 #define ESR_ISS_EABORT_EA_BIT U(9) 1025 1026 #define EC_BITS(x) (((x) >> ESR_EC_SHIFT) & ESR_EC_MASK) 1027 1028 /* Reset bit inside the Reset management register for EL3 (RMR_EL3) */ 1029 #define RMR_RESET_REQUEST_SHIFT U(0x1) 1030 #define RMR_WARM_RESET_CPU (U(1) << RMR_RESET_REQUEST_SHIFT) 1031 1032 /******************************************************************************* 1033 * Definitions of register offsets, fields and macros for CPU system 1034 * instructions. 1035 ******************************************************************************/ 1036 1037 #define TLBI_ADDR_SHIFT U(12) 1038 #define TLBI_ADDR_MASK ULL(0x00000FFFFFFFFFFF) 1039 #define TLBI_ADDR(x) (((x) >> TLBI_ADDR_SHIFT) & TLBI_ADDR_MASK) 1040 1041 /******************************************************************************* 1042 * Definitions of register offsets and fields in the CNTCTLBase Frame of the 1043 * system level implementation of the Generic Timer. 1044 ******************************************************************************/ 1045 #define CNTCTLBASE_CNTFRQ U(0x0) 1046 #define CNTNSAR U(0x4) 1047 #define CNTNSAR_NS_SHIFT(x) (x) 1048 1049 #define CNTACR_BASE(x) (U(0x40) + ((x) << 2)) 1050 #define CNTACR_RPCT_SHIFT U(0x0) 1051 #define CNTACR_RVCT_SHIFT U(0x1) 1052 #define CNTACR_RFRQ_SHIFT U(0x2) 1053 #define CNTACR_RVOFF_SHIFT U(0x3) 1054 #define CNTACR_RWVT_SHIFT U(0x4) 1055 #define CNTACR_RWPT_SHIFT U(0x5) 1056 1057 /******************************************************************************* 1058 * Definitions of register offsets and fields in the CNTBaseN Frame of the 1059 * system level implementation of the Generic Timer. 1060 ******************************************************************************/ 1061 /* Physical Count register. */ 1062 #define CNTPCT_LO U(0x0) 1063 /* Counter Frequency register. */ 1064 #define CNTBASEN_CNTFRQ U(0x10) 1065 /* Physical Timer CompareValue register. */ 1066 #define CNTP_CVAL_LO U(0x20) 1067 /* Physical Timer Control register. */ 1068 #define CNTP_CTL U(0x2c) 1069 1070 /* PMCR_EL0 definitions */ 1071 #define PMCR_EL0_RESET_VAL U(0x0) 1072 #define PMCR_EL0_N_SHIFT U(11) 1073 #define PMCR_EL0_N_MASK U(0x1f) 1074 #define PMCR_EL0_N_BITS (PMCR_EL0_N_MASK << PMCR_EL0_N_SHIFT) 1075 #define PMCR_EL0_LP_BIT (U(1) << 7) 1076 #define PMCR_EL0_LC_BIT (U(1) << 6) 1077 #define PMCR_EL0_DP_BIT (U(1) << 5) 1078 #define PMCR_EL0_X_BIT (U(1) << 4) 1079 #define PMCR_EL0_D_BIT (U(1) << 3) 1080 #define PMCR_EL0_C_BIT (U(1) << 2) 1081 #define PMCR_EL0_P_BIT (U(1) << 1) 1082 #define PMCR_EL0_E_BIT (U(1) << 0) 1083 1084 /******************************************************************************* 1085 * Definitions for system register interface to SVE 1086 ******************************************************************************/ 1087 #define ZCR_EL3 S3_6_C1_C2_0 1088 #define ZCR_EL2 S3_4_C1_C2_0 1089 1090 /* ZCR_EL3 definitions */ 1091 #define ZCR_EL3_LEN_MASK U(0xf) 1092 1093 /* ZCR_EL2 definitions */ 1094 #define ZCR_EL2_LEN_MASK U(0xf) 1095 1096 /******************************************************************************* 1097 * Definitions for system register interface to SME as needed in EL3 1098 ******************************************************************************/ 1099 #define ID_AA64SMFR0_EL1 S3_0_C0_C4_5 1100 #define SMCR_EL3 S3_6_C1_C2_6 1101 1102 /* ID_AA64SMFR0_EL1 definitions */ 1103 #define ID_AA64SMFR0_EL1_SME_FA64_SHIFT U(63) 1104 #define ID_AA64SMFR0_EL1_SME_FA64_MASK U(0x1) 1105 #define ID_AA64SMFR0_EL1_SME_FA64_SUPPORTED U(0x1) 1106 #define ID_AA64SMFR0_EL1_SME_VER_SHIFT U(55) 1107 #define ID_AA64SMFR0_EL1_SME_VER_MASK ULL(0xf) 1108 #define ID_AA64SMFR0_EL1_SME_INST_SUPPORTED ULL(0x0) 1109 #define ID_AA64SMFR0_EL1_SME2_INST_SUPPORTED ULL(0x1) 1110 1111 /* SMCR_ELx definitions */ 1112 #define SMCR_ELX_LEN_SHIFT U(0) 1113 #define SMCR_ELX_LEN_MAX U(0x1ff) 1114 #define SMCR_ELX_FA64_BIT (U(1) << 31) 1115 #define SMCR_ELX_EZT0_BIT (U(1) << 30) 1116 1117 /******************************************************************************* 1118 * Definitions of MAIR encodings for device and normal memory 1119 ******************************************************************************/ 1120 /* 1121 * MAIR encodings for device memory attributes. 1122 */ 1123 #define MAIR_DEV_nGnRnE ULL(0x0) 1124 #define MAIR_DEV_nGnRE ULL(0x4) 1125 #define MAIR_DEV_nGRE ULL(0x8) 1126 #define MAIR_DEV_GRE ULL(0xc) 1127 1128 /* 1129 * MAIR encodings for normal memory attributes. 1130 * 1131 * Cache Policy 1132 * WT: Write Through 1133 * WB: Write Back 1134 * NC: Non-Cacheable 1135 * 1136 * Transient Hint 1137 * NTR: Non-Transient 1138 * TR: Transient 1139 * 1140 * Allocation Policy 1141 * RA: Read Allocate 1142 * WA: Write Allocate 1143 * RWA: Read and Write Allocate 1144 * NA: No Allocation 1145 */ 1146 #define MAIR_NORM_WT_TR_WA ULL(0x1) 1147 #define MAIR_NORM_WT_TR_RA ULL(0x2) 1148 #define MAIR_NORM_WT_TR_RWA ULL(0x3) 1149 #define MAIR_NORM_NC ULL(0x4) 1150 #define MAIR_NORM_WB_TR_WA ULL(0x5) 1151 #define MAIR_NORM_WB_TR_RA ULL(0x6) 1152 #define MAIR_NORM_WB_TR_RWA ULL(0x7) 1153 #define MAIR_NORM_WT_NTR_NA ULL(0x8) 1154 #define MAIR_NORM_WT_NTR_WA ULL(0x9) 1155 #define MAIR_NORM_WT_NTR_RA ULL(0xa) 1156 #define MAIR_NORM_WT_NTR_RWA ULL(0xb) 1157 #define MAIR_NORM_WB_NTR_NA ULL(0xc) 1158 #define MAIR_NORM_WB_NTR_WA ULL(0xd) 1159 #define MAIR_NORM_WB_NTR_RA ULL(0xe) 1160 #define MAIR_NORM_WB_NTR_RWA ULL(0xf) 1161 1162 #define MAIR_NORM_OUTER_SHIFT U(4) 1163 1164 #define MAKE_MAIR_NORMAL_MEMORY(inner, outer) \ 1165 ((inner) | ((outer) << MAIR_NORM_OUTER_SHIFT)) 1166 1167 /* PAR_EL1 fields */ 1168 #define PAR_F_SHIFT U(0) 1169 #define PAR_F_MASK ULL(0x1) 1170 #define PAR_ADDR_SHIFT U(12) 1171 #define PAR_ADDR_MASK (BIT(40) - ULL(1)) /* 40-bits-wide page address */ 1172 1173 /******************************************************************************* 1174 * Definitions for system register interface to SPE 1175 ******************************************************************************/ 1176 #define PMBLIMITR_EL1 S3_0_C9_C10_0 1177 1178 /******************************************************************************* 1179 * Definitions for system register interface, shifts and masks for MPAM 1180 ******************************************************************************/ 1181 #define MPAMIDR_EL1 S3_0_C10_C4_4 1182 #define MPAM2_EL2 S3_4_C10_C5_0 1183 #define MPAMHCR_EL2 S3_4_C10_C4_0 1184 #define MPAM3_EL3 S3_6_C10_C5_0 1185 1186 #define MPAMIDR_EL1_VPMR_MAX_SHIFT ULL(18) 1187 #define MPAMIDR_EL1_VPMR_MAX_MASK ULL(0x7) 1188 /******************************************************************************* 1189 * Definitions for system register interface to AMU for FEAT_AMUv1 1190 ******************************************************************************/ 1191 #define AMCR_EL0 S3_3_C13_C2_0 1192 #define AMCFGR_EL0 S3_3_C13_C2_1 1193 #define AMCGCR_EL0 S3_3_C13_C2_2 1194 #define AMUSERENR_EL0 S3_3_C13_C2_3 1195 #define AMCNTENCLR0_EL0 S3_3_C13_C2_4 1196 #define AMCNTENSET0_EL0 S3_3_C13_C2_5 1197 #define AMCNTENCLR1_EL0 S3_3_C13_C3_0 1198 #define AMCNTENSET1_EL0 S3_3_C13_C3_1 1199 1200 /* Activity Monitor Group 0 Event Counter Registers */ 1201 #define AMEVCNTR00_EL0 S3_3_C13_C4_0 1202 #define AMEVCNTR01_EL0 S3_3_C13_C4_1 1203 #define AMEVCNTR02_EL0 S3_3_C13_C4_2 1204 #define AMEVCNTR03_EL0 S3_3_C13_C4_3 1205 1206 /* Activity Monitor Group 0 Event Type Registers */ 1207 #define AMEVTYPER00_EL0 S3_3_C13_C6_0 1208 #define AMEVTYPER01_EL0 S3_3_C13_C6_1 1209 #define AMEVTYPER02_EL0 S3_3_C13_C6_2 1210 #define AMEVTYPER03_EL0 S3_3_C13_C6_3 1211 1212 /* Activity Monitor Group 1 Event Counter Registers */ 1213 #define AMEVCNTR10_EL0 S3_3_C13_C12_0 1214 #define AMEVCNTR11_EL0 S3_3_C13_C12_1 1215 #define AMEVCNTR12_EL0 S3_3_C13_C12_2 1216 #define AMEVCNTR13_EL0 S3_3_C13_C12_3 1217 #define AMEVCNTR14_EL0 S3_3_C13_C12_4 1218 #define AMEVCNTR15_EL0 S3_3_C13_C12_5 1219 #define AMEVCNTR16_EL0 S3_3_C13_C12_6 1220 #define AMEVCNTR17_EL0 S3_3_C13_C12_7 1221 #define AMEVCNTR18_EL0 S3_3_C13_C13_0 1222 #define AMEVCNTR19_EL0 S3_3_C13_C13_1 1223 #define AMEVCNTR1A_EL0 S3_3_C13_C13_2 1224 #define AMEVCNTR1B_EL0 S3_3_C13_C13_3 1225 #define AMEVCNTR1C_EL0 S3_3_C13_C13_4 1226 #define AMEVCNTR1D_EL0 S3_3_C13_C13_5 1227 #define AMEVCNTR1E_EL0 S3_3_C13_C13_6 1228 #define AMEVCNTR1F_EL0 S3_3_C13_C13_7 1229 1230 /* Activity Monitor Group 1 Event Type Registers */ 1231 #define AMEVTYPER10_EL0 S3_3_C13_C14_0 1232 #define AMEVTYPER11_EL0 S3_3_C13_C14_1 1233 #define AMEVTYPER12_EL0 S3_3_C13_C14_2 1234 #define AMEVTYPER13_EL0 S3_3_C13_C14_3 1235 #define AMEVTYPER14_EL0 S3_3_C13_C14_4 1236 #define AMEVTYPER15_EL0 S3_3_C13_C14_5 1237 #define AMEVTYPER16_EL0 S3_3_C13_C14_6 1238 #define AMEVTYPER17_EL0 S3_3_C13_C14_7 1239 #define AMEVTYPER18_EL0 S3_3_C13_C15_0 1240 #define AMEVTYPER19_EL0 S3_3_C13_C15_1 1241 #define AMEVTYPER1A_EL0 S3_3_C13_C15_2 1242 #define AMEVTYPER1B_EL0 S3_3_C13_C15_3 1243 #define AMEVTYPER1C_EL0 S3_3_C13_C15_4 1244 #define AMEVTYPER1D_EL0 S3_3_C13_C15_5 1245 #define AMEVTYPER1E_EL0 S3_3_C13_C15_6 1246 #define AMEVTYPER1F_EL0 S3_3_C13_C15_7 1247 1248 /* AMCNTENSET0_EL0 definitions */ 1249 #define AMCNTENSET0_EL0_Pn_SHIFT U(0) 1250 #define AMCNTENSET0_EL0_Pn_MASK ULL(0xffff) 1251 1252 /* AMCNTENSET1_EL0 definitions */ 1253 #define AMCNTENSET1_EL0_Pn_SHIFT U(0) 1254 #define AMCNTENSET1_EL0_Pn_MASK ULL(0xffff) 1255 1256 /* AMCNTENCLR0_EL0 definitions */ 1257 #define AMCNTENCLR0_EL0_Pn_SHIFT U(0) 1258 #define AMCNTENCLR0_EL0_Pn_MASK ULL(0xffff) 1259 1260 /* AMCNTENCLR1_EL0 definitions */ 1261 #define AMCNTENCLR1_EL0_Pn_SHIFT U(0) 1262 #define AMCNTENCLR1_EL0_Pn_MASK ULL(0xffff) 1263 1264 /* AMCFGR_EL0 definitions */ 1265 #define AMCFGR_EL0_NCG_SHIFT U(28) 1266 #define AMCFGR_EL0_NCG_MASK U(0xf) 1267 #define AMCFGR_EL0_N_SHIFT U(0) 1268 #define AMCFGR_EL0_N_MASK U(0xff) 1269 1270 /* AMCGCR_EL0 definitions */ 1271 #define AMCGCR_EL0_CG0NC_SHIFT U(0) 1272 #define AMCGCR_EL0_CG0NC_MASK U(0xff) 1273 #define AMCGCR_EL0_CG1NC_SHIFT U(8) 1274 #define AMCGCR_EL0_CG1NC_MASK U(0xff) 1275 1276 /* MPAM register definitions */ 1277 #define MPAM3_EL3_MPAMEN_BIT (ULL(1) << 63) 1278 #define MPAM3_EL3_TRAPLOWER_BIT (ULL(1) << 62) 1279 #define MPAMHCR_EL2_TRAP_MPAMIDR_EL1 (ULL(1) << 31) 1280 #define MPAM3_EL3_RESET_VAL MPAM3_EL3_TRAPLOWER_BIT 1281 1282 #define MPAM2_EL2_TRAPMPAM0EL1 (ULL(1) << 49) 1283 #define MPAM2_EL2_TRAPMPAM1EL1 (ULL(1) << 48) 1284 1285 #define MPAMIDR_HAS_HCR_BIT (ULL(1) << 17) 1286 1287 /******************************************************************************* 1288 * Definitions for system register interface to AMU for FEAT_AMUv1p1 1289 ******************************************************************************/ 1290 1291 /* Definition for register defining which virtual offsets are implemented. */ 1292 #define AMCG1IDR_EL0 S3_3_C13_C2_6 1293 #define AMCG1IDR_CTR_MASK ULL(0xffff) 1294 #define AMCG1IDR_CTR_SHIFT U(0) 1295 #define AMCG1IDR_VOFF_MASK ULL(0xffff) 1296 #define AMCG1IDR_VOFF_SHIFT U(16) 1297 1298 /* New bit added to AMCR_EL0 */ 1299 #define AMCR_CG1RZ_SHIFT U(17) 1300 #define AMCR_CG1RZ_BIT (ULL(0x1) << AMCR_CG1RZ_SHIFT) 1301 1302 /* 1303 * Definitions for virtual offset registers for architected activity monitor 1304 * event counters. 1305 * AMEVCNTVOFF01_EL2 intentionally left undefined, as it does not exist. 1306 */ 1307 #define AMEVCNTVOFF00_EL2 S3_4_C13_C8_0 1308 #define AMEVCNTVOFF02_EL2 S3_4_C13_C8_2 1309 #define AMEVCNTVOFF03_EL2 S3_4_C13_C8_3 1310 1311 /* 1312 * Definitions for virtual offset registers for auxiliary activity monitor event 1313 * counters. 1314 */ 1315 #define AMEVCNTVOFF10_EL2 S3_4_C13_C10_0 1316 #define AMEVCNTVOFF11_EL2 S3_4_C13_C10_1 1317 #define AMEVCNTVOFF12_EL2 S3_4_C13_C10_2 1318 #define AMEVCNTVOFF13_EL2 S3_4_C13_C10_3 1319 #define AMEVCNTVOFF14_EL2 S3_4_C13_C10_4 1320 #define AMEVCNTVOFF15_EL2 S3_4_C13_C10_5 1321 #define AMEVCNTVOFF16_EL2 S3_4_C13_C10_6 1322 #define AMEVCNTVOFF17_EL2 S3_4_C13_C10_7 1323 #define AMEVCNTVOFF18_EL2 S3_4_C13_C11_0 1324 #define AMEVCNTVOFF19_EL2 S3_4_C13_C11_1 1325 #define AMEVCNTVOFF1A_EL2 S3_4_C13_C11_2 1326 #define AMEVCNTVOFF1B_EL2 S3_4_C13_C11_3 1327 #define AMEVCNTVOFF1C_EL2 S3_4_C13_C11_4 1328 #define AMEVCNTVOFF1D_EL2 S3_4_C13_C11_5 1329 #define AMEVCNTVOFF1E_EL2 S3_4_C13_C11_6 1330 #define AMEVCNTVOFF1F_EL2 S3_4_C13_C11_7 1331 1332 /******************************************************************************* 1333 * Realm management extension register definitions 1334 ******************************************************************************/ 1335 #define GPCCR_EL3 S3_6_C2_C1_6 1336 #define GPTBR_EL3 S3_6_C2_C1_4 1337 1338 #define SCXTNUM_EL2 S3_4_C13_C0_7 1339 #define SCXTNUM_EL1 S3_0_C13_C0_7 1340 #define SCXTNUM_EL0 S3_3_C13_C0_7 1341 1342 /******************************************************************************* 1343 * RAS system registers 1344 ******************************************************************************/ 1345 #define DISR_EL1 S3_0_C12_C1_1 1346 #define DISR_A_BIT U(31) 1347 1348 #define ERRIDR_EL1 S3_0_C5_C3_0 1349 #define ERRIDR_MASK U(0xffff) 1350 1351 #define ERRSELR_EL1 S3_0_C5_C3_1 1352 1353 /* System register access to Standard Error Record registers */ 1354 #define ERXFR_EL1 S3_0_C5_C4_0 1355 #define ERXCTLR_EL1 S3_0_C5_C4_1 1356 #define ERXSTATUS_EL1 S3_0_C5_C4_2 1357 #define ERXADDR_EL1 S3_0_C5_C4_3 1358 #define ERXPFGF_EL1 S3_0_C5_C4_4 1359 #define ERXPFGCTL_EL1 S3_0_C5_C4_5 1360 #define ERXPFGCDN_EL1 S3_0_C5_C4_6 1361 #define ERXMISC0_EL1 S3_0_C5_C5_0 1362 #define ERXMISC1_EL1 S3_0_C5_C5_1 1363 1364 #define ERXCTLR_ED_SHIFT U(0) 1365 #define ERXCTLR_ED_BIT (U(1) << ERXCTLR_ED_SHIFT) 1366 #define ERXCTLR_UE_BIT (U(1) << 4) 1367 1368 #define ERXPFGCTL_UC_BIT (U(1) << 1) 1369 #define ERXPFGCTL_UEU_BIT (U(1) << 2) 1370 #define ERXPFGCTL_CDEN_BIT (U(1) << 31) 1371 1372 /******************************************************************************* 1373 * Armv8.3 Pointer Authentication Registers 1374 ******************************************************************************/ 1375 #define APIAKeyLo_EL1 S3_0_C2_C1_0 1376 #define APIAKeyHi_EL1 S3_0_C2_C1_1 1377 #define APIBKeyLo_EL1 S3_0_C2_C1_2 1378 #define APIBKeyHi_EL1 S3_0_C2_C1_3 1379 #define APDAKeyLo_EL1 S3_0_C2_C2_0 1380 #define APDAKeyHi_EL1 S3_0_C2_C2_1 1381 #define APDBKeyLo_EL1 S3_0_C2_C2_2 1382 #define APDBKeyHi_EL1 S3_0_C2_C2_3 1383 #define APGAKeyLo_EL1 S3_0_C2_C3_0 1384 #define APGAKeyHi_EL1 S3_0_C2_C3_1 1385 1386 /******************************************************************************* 1387 * Armv8.4 Data Independent Timing Registers 1388 ******************************************************************************/ 1389 #define DIT S3_3_C4_C2_5 1390 #define DIT_BIT BIT(24) 1391 1392 /******************************************************************************* 1393 * Armv8.5 - new MSR encoding to directly access PSTATE.SSBS field 1394 ******************************************************************************/ 1395 #define SSBS S3_3_C4_C2_6 1396 1397 /******************************************************************************* 1398 * Armv8.5 - Memory Tagging Extension Registers 1399 ******************************************************************************/ 1400 #define TFSRE0_EL1 S3_0_C5_C6_1 1401 #define TFSR_EL1 S3_0_C5_C6_0 1402 #define RGSR_EL1 S3_0_C1_C0_5 1403 #define GCR_EL1 S3_0_C1_C0_6 1404 1405 #define GCR_EL1_RRND_BIT (UL(1) << 16) 1406 1407 /******************************************************************************* 1408 * Armv8.5 - Random Number Generator Registers 1409 ******************************************************************************/ 1410 #define RNDR S3_3_C2_C4_0 1411 #define RNDRRS S3_3_C2_C4_1 1412 1413 /******************************************************************************* 1414 * FEAT_HCX - Extended Hypervisor Configuration Register 1415 ******************************************************************************/ 1416 #define HCRX_EL2 S3_4_C1_C2_2 1417 #define HCRX_EL2_MSCEn_BIT (UL(1) << 11) 1418 #define HCRX_EL2_MCE2_BIT (UL(1) << 10) 1419 #define HCRX_EL2_CMOW_BIT (UL(1) << 9) 1420 #define HCRX_EL2_VFNMI_BIT (UL(1) << 8) 1421 #define HCRX_EL2_VINMI_BIT (UL(1) << 7) 1422 #define HCRX_EL2_TALLINT_BIT (UL(1) << 6) 1423 #define HCRX_EL2_SMPME_BIT (UL(1) << 5) 1424 #define HCRX_EL2_FGTnXS_BIT (UL(1) << 4) 1425 #define HCRX_EL2_FnXS_BIT (UL(1) << 3) 1426 #define HCRX_EL2_EnASR_BIT (UL(1) << 2) 1427 #define HCRX_EL2_EnALS_BIT (UL(1) << 1) 1428 #define HCRX_EL2_EnAS0_BIT (UL(1) << 0) 1429 #define HCRX_EL2_INIT_VAL ULL(0x0) 1430 1431 /******************************************************************************* 1432 * FEAT_FGT - Definitions for Fine-Grained Trap registers 1433 ******************************************************************************/ 1434 #define HFGITR_EL2_INIT_VAL ULL(0x180000000000000) 1435 #define HFGRTR_EL2_INIT_VAL ULL(0xC4000000000000) 1436 #define HFGWTR_EL2_INIT_VAL ULL(0xC4000000000000) 1437 1438 /******************************************************************************* 1439 * FEAT_TCR2 - Extended Translation Control Registers 1440 ******************************************************************************/ 1441 #define TCR2_EL1 S3_0_C2_C0_3 1442 #define TCR2_EL2 S3_4_C2_C0_3 1443 1444 /******************************************************************************* 1445 * Permission indirection and overlay Registers 1446 ******************************************************************************/ 1447 1448 #define PIRE0_EL1 S3_0_C10_C2_2 1449 #define PIRE0_EL2 S3_4_C10_C2_2 1450 #define PIR_EL1 S3_0_C10_C2_3 1451 #define PIR_EL2 S3_4_C10_C2_3 1452 #define POR_EL1 S3_0_C10_C2_4 1453 #define POR_EL2 S3_4_C10_C2_4 1454 #define S2PIR_EL2 S3_4_C10_C2_5 1455 #define S2POR_EL1 S3_0_C10_C2_5 1456 1457 /******************************************************************************* 1458 * FEAT_GCS - Guarded Control Stack Registers 1459 ******************************************************************************/ 1460 #define GCSCR_EL2 S3_4_C2_C5_0 1461 #define GCSPR_EL2 S3_4_C2_C5_1 1462 #define GCSCR_EL1 S3_0_C2_C5_0 1463 #define GCSCRE0_EL1 S3_0_C2_C5_2 1464 #define GCSPR_EL1 S3_0_C2_C5_1 1465 #define GCSPR_EL0 S3_3_C2_C5_1 1466 1467 #define GCSCR_EXLOCK_EN_BIT (UL(1) << 6) 1468 1469 /******************************************************************************* 1470 * FEAT_TRF - Trace Filter Control Registers 1471 ******************************************************************************/ 1472 #define TRFCR_EL2 S3_4_C1_C2_1 1473 #define TRFCR_EL1 S3_0_C1_C2_1 1474 1475 /******************************************************************************* 1476 * Definitions for DynamicIQ Shared Unit registers 1477 ******************************************************************************/ 1478 #define CLUSTERPWRDN_EL1 S3_0_c15_c3_6 1479 1480 /* CLUSTERPWRDN_EL1 register definitions */ 1481 #define DSU_CLUSTER_PWR_OFF 0 1482 #define DSU_CLUSTER_PWR_ON 1 1483 #define DSU_CLUSTER_PWR_MASK U(1) 1484 #define DSU_CLUSTER_MEM_RET BIT(1) 1485 1486 /******************************************************************************* 1487 * Definitions for CPU Power/Performance Management registers 1488 ******************************************************************************/ 1489 1490 #define CPUPPMCR_EL3 S3_6_C15_C2_0 1491 #define CPUPPMCR_EL3_MPMMPINCTL_SHIFT UINT64_C(0) 1492 #define CPUPPMCR_EL3_MPMMPINCTL_MASK UINT64_C(0x1) 1493 1494 #define CPUMPMMCR_EL3 S3_6_C15_C2_1 1495 #define CPUMPMMCR_EL3_MPMM_EN_SHIFT UINT64_C(0) 1496 #define CPUMPMMCR_EL3_MPMM_EN_MASK UINT64_C(0x1) 1497 1498 /* alternative system register encoding for the "sb" speculation barrier */ 1499 #define SYSREG_SB S0_3_C3_C0_7 1500 1501 #endif /* ARCH_H */ 1502