1 /* 2 * Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2020-2022, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef ARCH_H 9 #define ARCH_H 10 11 #include <lib/utils_def.h> 12 13 /******************************************************************************* 14 * MIDR bit definitions 15 ******************************************************************************/ 16 #define MIDR_IMPL_MASK U(0xff) 17 #define MIDR_IMPL_SHIFT U(0x18) 18 #define MIDR_VAR_SHIFT U(20) 19 #define MIDR_VAR_BITS U(4) 20 #define MIDR_VAR_MASK U(0xf) 21 #define MIDR_REV_SHIFT U(0) 22 #define MIDR_REV_BITS U(4) 23 #define MIDR_REV_MASK U(0xf) 24 #define MIDR_PN_MASK U(0xfff) 25 #define MIDR_PN_SHIFT U(0x4) 26 27 /******************************************************************************* 28 * MPIDR macros 29 ******************************************************************************/ 30 #define MPIDR_MT_MASK (ULL(1) << 24) 31 #define MPIDR_CPU_MASK MPIDR_AFFLVL_MASK 32 #define MPIDR_CLUSTER_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS) 33 #define MPIDR_AFFINITY_BITS U(8) 34 #define MPIDR_AFFLVL_MASK ULL(0xff) 35 #define MPIDR_AFF0_SHIFT U(0) 36 #define MPIDR_AFF1_SHIFT U(8) 37 #define MPIDR_AFF2_SHIFT U(16) 38 #define MPIDR_AFF3_SHIFT U(32) 39 #define MPIDR_AFF_SHIFT(_n) MPIDR_AFF##_n##_SHIFT 40 #define MPIDR_AFFINITY_MASK ULL(0xff00ffffff) 41 #define MPIDR_AFFLVL_SHIFT U(3) 42 #define MPIDR_AFFLVL0 ULL(0x0) 43 #define MPIDR_AFFLVL1 ULL(0x1) 44 #define MPIDR_AFFLVL2 ULL(0x2) 45 #define MPIDR_AFFLVL3 ULL(0x3) 46 #define MPIDR_AFFLVL(_n) MPIDR_AFFLVL##_n 47 #define MPIDR_AFFLVL0_VAL(mpidr) \ 48 (((mpidr) >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK) 49 #define MPIDR_AFFLVL1_VAL(mpidr) \ 50 (((mpidr) >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK) 51 #define MPIDR_AFFLVL2_VAL(mpidr) \ 52 (((mpidr) >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK) 53 #define MPIDR_AFFLVL3_VAL(mpidr) \ 54 (((mpidr) >> MPIDR_AFF3_SHIFT) & MPIDR_AFFLVL_MASK) 55 /* 56 * The MPIDR_MAX_AFFLVL count starts from 0. Take care to 57 * add one while using this macro to define array sizes. 58 * TODO: Support only the first 3 affinity levels for now. 59 */ 60 #define MPIDR_MAX_AFFLVL U(2) 61 62 #define MPID_MASK (MPIDR_MT_MASK | \ 63 (MPIDR_AFFLVL_MASK << MPIDR_AFF3_SHIFT) | \ 64 (MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT) | \ 65 (MPIDR_AFFLVL_MASK << MPIDR_AFF1_SHIFT) | \ 66 (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT)) 67 68 #define MPIDR_AFF_ID(mpid, n) \ 69 (((mpid) >> MPIDR_AFF_SHIFT(n)) & MPIDR_AFFLVL_MASK) 70 71 /* 72 * An invalid MPID. This value can be used by functions that return an MPID to 73 * indicate an error. 74 */ 75 #define INVALID_MPID U(0xFFFFFFFF) 76 77 /******************************************************************************* 78 * Definitions for CPU system register interface to GICv3 79 ******************************************************************************/ 80 #define ICC_IGRPEN1_EL1 S3_0_C12_C12_7 81 #define ICC_SGI1R S3_0_C12_C11_5 82 #define ICC_SRE_EL1 S3_0_C12_C12_5 83 #define ICC_SRE_EL2 S3_4_C12_C9_5 84 #define ICC_SRE_EL3 S3_6_C12_C12_5 85 #define ICC_CTLR_EL1 S3_0_C12_C12_4 86 #define ICC_CTLR_EL3 S3_6_C12_C12_4 87 #define ICC_PMR_EL1 S3_0_C4_C6_0 88 #define ICC_RPR_EL1 S3_0_C12_C11_3 89 #define ICC_IGRPEN1_EL3 S3_6_c12_c12_7 90 #define ICC_IGRPEN0_EL1 S3_0_c12_c12_6 91 #define ICC_HPPIR0_EL1 S3_0_c12_c8_2 92 #define ICC_HPPIR1_EL1 S3_0_c12_c12_2 93 #define ICC_IAR0_EL1 S3_0_c12_c8_0 94 #define ICC_IAR1_EL1 S3_0_c12_c12_0 95 #define ICC_EOIR0_EL1 S3_0_c12_c8_1 96 #define ICC_EOIR1_EL1 S3_0_c12_c12_1 97 #define ICC_SGI0R_EL1 S3_0_c12_c11_7 98 99 /******************************************************************************* 100 * Definitions for EL2 system registers for save/restore routine 101 ******************************************************************************/ 102 #define CNTPOFF_EL2 S3_4_C14_C0_6 103 #define HAFGRTR_EL2 S3_4_C3_C1_6 104 #define HDFGRTR_EL2 S3_4_C3_C1_4 105 #define HDFGWTR_EL2 S3_4_C3_C1_5 106 #define HFGITR_EL2 S3_4_C1_C1_6 107 #define HFGRTR_EL2 S3_4_C1_C1_4 108 #define HFGWTR_EL2 S3_4_C1_C1_5 109 #define ICH_HCR_EL2 S3_4_C12_C11_0 110 #define ICH_VMCR_EL2 S3_4_C12_C11_7 111 #define MPAMVPM0_EL2 S3_4_C10_C6_0 112 #define MPAMVPM1_EL2 S3_4_C10_C6_1 113 #define MPAMVPM2_EL2 S3_4_C10_C6_2 114 #define MPAMVPM3_EL2 S3_4_C10_C6_3 115 #define MPAMVPM4_EL2 S3_4_C10_C6_4 116 #define MPAMVPM5_EL2 S3_4_C10_C6_5 117 #define MPAMVPM6_EL2 S3_4_C10_C6_6 118 #define MPAMVPM7_EL2 S3_4_C10_C6_7 119 #define MPAMVPMV_EL2 S3_4_C10_C4_1 120 #define TRFCR_EL2 S3_4_C1_C2_1 121 #define PMSCR_EL2 S3_4_C9_C9_0 122 #define TFSR_EL2 S3_4_C5_C6_0 123 124 /******************************************************************************* 125 * Generic timer memory mapped registers & offsets 126 ******************************************************************************/ 127 #define CNTCR_OFF U(0x000) 128 #define CNTCV_OFF U(0x008) 129 #define CNTFID_OFF U(0x020) 130 131 #define CNTCR_EN (U(1) << 0) 132 #define CNTCR_HDBG (U(1) << 1) 133 #define CNTCR_FCREQ(x) ((x) << 8) 134 135 /******************************************************************************* 136 * System register bit definitions 137 ******************************************************************************/ 138 /* CLIDR definitions */ 139 #define LOUIS_SHIFT U(21) 140 #define LOC_SHIFT U(24) 141 #define CTYPE_SHIFT(n) U(3 * (n - 1)) 142 #define CLIDR_FIELD_WIDTH U(3) 143 144 /* CSSELR definitions */ 145 #define LEVEL_SHIFT U(1) 146 147 /* Data cache set/way op type defines */ 148 #define DCISW U(0x0) 149 #define DCCISW U(0x1) 150 #if ERRATA_A53_827319 151 #define DCCSW DCCISW 152 #else 153 #define DCCSW U(0x2) 154 #endif 155 156 /* ID_AA64PFR0_EL1 definitions */ 157 #define ID_AA64PFR0_EL0_SHIFT U(0) 158 #define ID_AA64PFR0_EL1_SHIFT U(4) 159 #define ID_AA64PFR0_EL2_SHIFT U(8) 160 #define ID_AA64PFR0_EL3_SHIFT U(12) 161 162 #define ID_AA64PFR0_AMU_SHIFT U(44) 163 #define ID_AA64PFR0_AMU_MASK ULL(0xf) 164 #define ID_AA64PFR0_AMU_NOT_SUPPORTED U(0x0) 165 #define ID_AA64PFR0_AMU_V1 ULL(0x1) 166 #define ID_AA64PFR0_AMU_V1P1 U(0x2) 167 168 #define ID_AA64PFR0_ELX_MASK ULL(0xf) 169 170 #define ID_AA64PFR0_GIC_SHIFT U(24) 171 #define ID_AA64PFR0_GIC_WIDTH U(4) 172 #define ID_AA64PFR0_GIC_MASK ULL(0xf) 173 174 #define ID_AA64PFR0_SVE_SHIFT U(32) 175 #define ID_AA64PFR0_SVE_MASK ULL(0xf) 176 #define ID_AA64PFR0_SVE_SUPPORTED ULL(0x1) 177 #define ID_AA64PFR0_SVE_LENGTH U(4) 178 179 #define ID_AA64PFR0_SEL2_SHIFT U(36) 180 #define ID_AA64PFR0_SEL2_MASK ULL(0xf) 181 182 #define ID_AA64PFR0_MPAM_SHIFT U(40) 183 #define ID_AA64PFR0_MPAM_MASK ULL(0xf) 184 185 #define ID_AA64PFR0_DIT_SHIFT U(48) 186 #define ID_AA64PFR0_DIT_MASK ULL(0xf) 187 #define ID_AA64PFR0_DIT_LENGTH U(4) 188 #define ID_AA64PFR0_DIT_SUPPORTED U(1) 189 190 #define ID_AA64PFR0_CSV2_SHIFT U(56) 191 #define ID_AA64PFR0_CSV2_MASK ULL(0xf) 192 #define ID_AA64PFR0_CSV2_LENGTH U(4) 193 #define ID_AA64PFR0_CSV2_2_SUPPORTED ULL(0x2) 194 195 #define ID_AA64PFR0_FEAT_RME_SHIFT U(52) 196 #define ID_AA64PFR0_FEAT_RME_MASK ULL(0xf) 197 #define ID_AA64PFR0_FEAT_RME_LENGTH U(4) 198 #define ID_AA64PFR0_FEAT_RME_NOT_SUPPORTED U(0) 199 #define ID_AA64PFR0_FEAT_RME_V1 U(1) 200 201 #define ID_AA64PFR0_RAS_SHIFT U(28) 202 #define ID_AA64PFR0_RAS_MASK ULL(0xf) 203 #define ID_AA64PFR0_RAS_NOT_SUPPORTED ULL(0x0) 204 #define ID_AA64PFR0_RAS_LENGTH U(4) 205 206 /* Exception level handling */ 207 #define EL_IMPL_NONE ULL(0) 208 #define EL_IMPL_A64ONLY ULL(1) 209 #define EL_IMPL_A64_A32 ULL(2) 210 211 /* ID_AA64DFR0_EL1.TraceVer definitions */ 212 #define ID_AA64DFR0_TRACEVER_SHIFT U(4) 213 #define ID_AA64DFR0_TRACEVER_MASK ULL(0xf) 214 #define ID_AA64DFR0_TRACEVER_SUPPORTED ULL(1) 215 #define ID_AA64DFR0_TRACEVER_LENGTH U(4) 216 #define ID_AA64DFR0_TRACEFILT_SHIFT U(40) 217 #define ID_AA64DFR0_TRACEFILT_MASK U(0xf) 218 #define ID_AA64DFR0_TRACEFILT_SUPPORTED U(1) 219 #define ID_AA64DFR0_TRACEFILT_LENGTH U(4) 220 221 /* ID_AA64DFR0_EL1.PMS definitions (for ARMv8.2+) */ 222 #define ID_AA64DFR0_PMS_SHIFT U(32) 223 #define ID_AA64DFR0_PMS_MASK ULL(0xf) 224 #define ID_AA64DFR0_SPE_SUPPORTED ULL(0x1) 225 #define ID_AA64DFR0_SPE_NOT_SUPPORTED ULL(0x0) 226 227 /* ID_AA64DFR0_EL1.TraceBuffer definitions */ 228 #define ID_AA64DFR0_TRACEBUFFER_SHIFT U(44) 229 #define ID_AA64DFR0_TRACEBUFFER_MASK ULL(0xf) 230 #define ID_AA64DFR0_TRACEBUFFER_SUPPORTED ULL(1) 231 232 /* ID_AA64DFR0_EL1.MTPMU definitions (for ARMv8.6+) */ 233 #define ID_AA64DFR0_MTPMU_SHIFT U(48) 234 #define ID_AA64DFR0_MTPMU_MASK ULL(0xf) 235 #define ID_AA64DFR0_MTPMU_SUPPORTED ULL(1) 236 237 /* ID_AA64DFR0_EL1.BRBE definitions */ 238 #define ID_AA64DFR0_BRBE_SHIFT U(52) 239 #define ID_AA64DFR0_BRBE_MASK ULL(0xf) 240 #define ID_AA64DFR0_BRBE_SUPPORTED ULL(1) 241 242 /* ID_AA64ISAR0_EL1 definitions */ 243 #define ID_AA64ISAR0_RNDR_SHIFT U(60) 244 #define ID_AA64ISAR0_RNDR_MASK ULL(0xf) 245 246 /* ID_AA64ISAR1_EL1 definitions */ 247 #define ID_AA64ISAR1_EL1 S3_0_C0_C6_1 248 249 #define ID_AA64ISAR1_GPI_SHIFT U(28) 250 #define ID_AA64ISAR1_GPI_MASK ULL(0xf) 251 #define ID_AA64ISAR1_GPA_SHIFT U(24) 252 #define ID_AA64ISAR1_GPA_MASK ULL(0xf) 253 254 #define ID_AA64ISAR1_API_SHIFT U(8) 255 #define ID_AA64ISAR1_API_MASK ULL(0xf) 256 #define ID_AA64ISAR1_APA_SHIFT U(4) 257 #define ID_AA64ISAR1_APA_MASK ULL(0xf) 258 259 #define ID_AA64ISAR1_SB_SHIFT U(36) 260 #define ID_AA64ISAR1_SB_MASK ULL(0xf) 261 #define ID_AA64ISAR1_SB_SUPPORTED ULL(0x1) 262 #define ID_AA64ISAR1_SB_NOT_SUPPORTED ULL(0x0) 263 264 /* ID_AA64ISAR2_EL1 definitions */ 265 #define ID_AA64ISAR2_EL1 S3_0_C0_C6_2 266 267 #define ID_AA64ISAR2_GPA3_SHIFT U(8) 268 #define ID_AA64ISAR2_GPA3_MASK ULL(0xf) 269 270 #define ID_AA64ISAR2_APA3_SHIFT U(12) 271 #define ID_AA64ISAR2_APA3_MASK ULL(0xf) 272 273 /* ID_AA64MMFR0_EL1 definitions */ 274 #define ID_AA64MMFR0_EL1_PARANGE_SHIFT U(0) 275 #define ID_AA64MMFR0_EL1_PARANGE_MASK ULL(0xf) 276 277 #define PARANGE_0000 U(32) 278 #define PARANGE_0001 U(36) 279 #define PARANGE_0010 U(40) 280 #define PARANGE_0011 U(42) 281 #define PARANGE_0100 U(44) 282 #define PARANGE_0101 U(48) 283 #define PARANGE_0110 U(52) 284 285 #define ID_AA64MMFR0_EL1_ECV_SHIFT U(60) 286 #define ID_AA64MMFR0_EL1_ECV_MASK ULL(0xf) 287 #define ID_AA64MMFR0_EL1_ECV_NOT_SUPPORTED ULL(0x0) 288 #define ID_AA64MMFR0_EL1_ECV_SUPPORTED ULL(0x1) 289 #define ID_AA64MMFR0_EL1_ECV_SELF_SYNCH ULL(0x2) 290 291 #define ID_AA64MMFR0_EL1_FGT_SHIFT U(56) 292 #define ID_AA64MMFR0_EL1_FGT_MASK ULL(0xf) 293 #define ID_AA64MMFR0_EL1_FGT_SUPPORTED ULL(0x1) 294 #define ID_AA64MMFR0_EL1_FGT_NOT_SUPPORTED ULL(0x0) 295 296 #define ID_AA64MMFR0_EL1_TGRAN4_SHIFT U(28) 297 #define ID_AA64MMFR0_EL1_TGRAN4_MASK ULL(0xf) 298 #define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED ULL(0x0) 299 #define ID_AA64MMFR0_EL1_TGRAN4_NOT_SUPPORTED ULL(0xf) 300 301 #define ID_AA64MMFR0_EL1_TGRAN64_SHIFT U(24) 302 #define ID_AA64MMFR0_EL1_TGRAN64_MASK ULL(0xf) 303 #define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED ULL(0x0) 304 #define ID_AA64MMFR0_EL1_TGRAN64_NOT_SUPPORTED ULL(0xf) 305 306 #define ID_AA64MMFR0_EL1_TGRAN16_SHIFT U(20) 307 #define ID_AA64MMFR0_EL1_TGRAN16_MASK ULL(0xf) 308 #define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED ULL(0x1) 309 #define ID_AA64MMFR0_EL1_TGRAN16_NOT_SUPPORTED ULL(0x0) 310 311 /* ID_AA64MMFR1_EL1 definitions */ 312 #define ID_AA64MMFR1_EL1_TWED_SHIFT U(32) 313 #define ID_AA64MMFR1_EL1_TWED_MASK ULL(0xf) 314 #define ID_AA64MMFR1_EL1_TWED_SUPPORTED ULL(0x1) 315 #define ID_AA64MMFR1_EL1_TWED_NOT_SUPPORTED ULL(0x0) 316 317 #define ID_AA64MMFR1_EL1_PAN_SHIFT U(20) 318 #define ID_AA64MMFR1_EL1_PAN_MASK ULL(0xf) 319 #define ID_AA64MMFR1_EL1_PAN_NOT_SUPPORTED ULL(0x0) 320 #define ID_AA64MMFR1_EL1_PAN_SUPPORTED ULL(0x1) 321 #define ID_AA64MMFR1_EL1_PAN2_SUPPORTED ULL(0x2) 322 #define ID_AA64MMFR1_EL1_PAN3_SUPPORTED ULL(0x3) 323 324 #define ID_AA64MMFR1_EL1_VHE_SHIFT U(8) 325 #define ID_AA64MMFR1_EL1_VHE_MASK ULL(0xf) 326 327 #define ID_AA64MMFR1_EL1_HCX_SHIFT U(40) 328 #define ID_AA64MMFR1_EL1_HCX_MASK ULL(0xf) 329 #define ID_AA64MMFR1_EL1_HCX_SUPPORTED ULL(0x1) 330 #define ID_AA64MMFR1_EL1_HCX_NOT_SUPPORTED ULL(0x0) 331 332 /* ID_AA64MMFR2_EL1 definitions */ 333 #define ID_AA64MMFR2_EL1 S3_0_C0_C7_2 334 335 #define ID_AA64MMFR2_EL1_ST_SHIFT U(28) 336 #define ID_AA64MMFR2_EL1_ST_MASK ULL(0xf) 337 338 #define ID_AA64MMFR2_EL1_CCIDX_SHIFT U(20) 339 #define ID_AA64MMFR2_EL1_CCIDX_MASK ULL(0xf) 340 #define ID_AA64MMFR2_EL1_CCIDX_LENGTH U(4) 341 342 #define ID_AA64MMFR2_EL1_CNP_SHIFT U(0) 343 #define ID_AA64MMFR2_EL1_CNP_MASK ULL(0xf) 344 345 #define ID_AA64MMFR2_EL1_NV_SHIFT U(24) 346 #define ID_AA64MMFR2_EL1_NV_MASK ULL(0xf) 347 #define ID_AA64MMFR2_EL1_NV_NOT_SUPPORTED ULL(0x0) 348 #define ID_AA64MMFR2_EL1_NV_SUPPORTED ULL(0x1) 349 #define ID_AA64MMFR2_EL1_NV2_SUPPORTED ULL(0x2) 350 351 /* ID_AA64PFR1_EL1 definitions */ 352 #define ID_AA64PFR1_EL1_SSBS_SHIFT U(4) 353 #define ID_AA64PFR1_EL1_SSBS_MASK ULL(0xf) 354 355 #define SSBS_UNAVAILABLE ULL(0) /* No architectural SSBS support */ 356 357 #define ID_AA64PFR1_EL1_BT_SHIFT U(0) 358 #define ID_AA64PFR1_EL1_BT_MASK ULL(0xf) 359 360 #define BTI_IMPLEMENTED ULL(1) /* The BTI mechanism is implemented */ 361 362 #define ID_AA64PFR1_EL1_MTE_SHIFT U(8) 363 #define ID_AA64PFR1_EL1_MTE_MASK ULL(0xf) 364 365 /* Memory Tagging Extension is not implemented */ 366 #define MTE_UNIMPLEMENTED U(0) 367 /* FEAT_MTE: MTE instructions accessible at EL0 are implemented */ 368 #define MTE_IMPLEMENTED_EL0 U(1) 369 /* FEAT_MTE2: Full MTE is implemented */ 370 #define MTE_IMPLEMENTED_ELX U(2) 371 /* 372 * FEAT_MTE3: MTE is implemented with support for 373 * asymmetric Tag Check Fault handling 374 */ 375 #define MTE_IMPLEMENTED_ASY U(3) 376 377 #define ID_AA64PFR1_MPAM_FRAC_SHIFT ULL(16) 378 #define ID_AA64PFR1_MPAM_FRAC_MASK ULL(0xf) 379 380 #define ID_AA64PFR1_EL1_SME_SHIFT U(24) 381 #define ID_AA64PFR1_EL1_SME_MASK ULL(0xf) 382 383 /* ID_PFR1_EL1 definitions */ 384 #define ID_PFR1_VIRTEXT_SHIFT U(12) 385 #define ID_PFR1_VIRTEXT_MASK U(0xf) 386 #define GET_VIRT_EXT(id) (((id) >> ID_PFR1_VIRTEXT_SHIFT) \ 387 & ID_PFR1_VIRTEXT_MASK) 388 389 /* SCTLR definitions */ 390 #define SCTLR_EL2_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ 391 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \ 392 (U(1) << 11) | (U(1) << 5) | (U(1) << 4)) 393 394 #define SCTLR_EL1_RES1 ((UL(1) << 29) | (UL(1) << 28) | (UL(1) << 23) | \ 395 (UL(1) << 22) | (UL(1) << 20) | (UL(1) << 11)) 396 397 #define SCTLR_AARCH32_EL1_RES1 \ 398 ((U(1) << 23) | (U(1) << 22) | (U(1) << 11) | \ 399 (U(1) << 4) | (U(1) << 3)) 400 401 #define SCTLR_EL3_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ 402 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \ 403 (U(1) << 11) | (U(1) << 5) | (U(1) << 4)) 404 405 #define SCTLR_M_BIT (ULL(1) << 0) 406 #define SCTLR_A_BIT (ULL(1) << 1) 407 #define SCTLR_C_BIT (ULL(1) << 2) 408 #define SCTLR_SA_BIT (ULL(1) << 3) 409 #define SCTLR_SA0_BIT (ULL(1) << 4) 410 #define SCTLR_CP15BEN_BIT (ULL(1) << 5) 411 #define SCTLR_nAA_BIT (ULL(1) << 6) 412 #define SCTLR_ITD_BIT (ULL(1) << 7) 413 #define SCTLR_SED_BIT (ULL(1) << 8) 414 #define SCTLR_UMA_BIT (ULL(1) << 9) 415 #define SCTLR_EnRCTX_BIT (ULL(1) << 10) 416 #define SCTLR_EOS_BIT (ULL(1) << 11) 417 #define SCTLR_I_BIT (ULL(1) << 12) 418 #define SCTLR_EnDB_BIT (ULL(1) << 13) 419 #define SCTLR_DZE_BIT (ULL(1) << 14) 420 #define SCTLR_UCT_BIT (ULL(1) << 15) 421 #define SCTLR_NTWI_BIT (ULL(1) << 16) 422 #define SCTLR_NTWE_BIT (ULL(1) << 18) 423 #define SCTLR_WXN_BIT (ULL(1) << 19) 424 #define SCTLR_TSCXT_BIT (ULL(1) << 20) 425 #define SCTLR_IESB_BIT (ULL(1) << 21) 426 #define SCTLR_EIS_BIT (ULL(1) << 22) 427 #define SCTLR_SPAN_BIT (ULL(1) << 23) 428 #define SCTLR_E0E_BIT (ULL(1) << 24) 429 #define SCTLR_EE_BIT (ULL(1) << 25) 430 #define SCTLR_UCI_BIT (ULL(1) << 26) 431 #define SCTLR_EnDA_BIT (ULL(1) << 27) 432 #define SCTLR_nTLSMD_BIT (ULL(1) << 28) 433 #define SCTLR_LSMAOE_BIT (ULL(1) << 29) 434 #define SCTLR_EnIB_BIT (ULL(1) << 30) 435 #define SCTLR_EnIA_BIT (ULL(1) << 31) 436 #define SCTLR_BT0_BIT (ULL(1) << 35) 437 #define SCTLR_BT1_BIT (ULL(1) << 36) 438 #define SCTLR_BT_BIT (ULL(1) << 36) 439 #define SCTLR_ITFSB_BIT (ULL(1) << 37) 440 #define SCTLR_TCF0_SHIFT U(38) 441 #define SCTLR_TCF0_MASK ULL(3) 442 #define SCTLR_ENTP2_BIT (ULL(1) << 60) 443 444 /* Tag Check Faults in EL0 have no effect on the PE */ 445 #define SCTLR_TCF0_NO_EFFECT U(0) 446 /* Tag Check Faults in EL0 cause a synchronous exception */ 447 #define SCTLR_TCF0_SYNC U(1) 448 /* Tag Check Faults in EL0 are asynchronously accumulated */ 449 #define SCTLR_TCF0_ASYNC U(2) 450 /* 451 * Tag Check Faults in EL0 cause a synchronous exception on reads, 452 * and are asynchronously accumulated on writes 453 */ 454 #define SCTLR_TCF0_SYNCR_ASYNCW U(3) 455 456 #define SCTLR_TCF_SHIFT U(40) 457 #define SCTLR_TCF_MASK ULL(3) 458 459 /* Tag Check Faults in EL1 have no effect on the PE */ 460 #define SCTLR_TCF_NO_EFFECT U(0) 461 /* Tag Check Faults in EL1 cause a synchronous exception */ 462 #define SCTLR_TCF_SYNC U(1) 463 /* Tag Check Faults in EL1 are asynchronously accumulated */ 464 #define SCTLR_TCF_ASYNC U(2) 465 /* 466 * Tag Check Faults in EL1 cause a synchronous exception on reads, 467 * and are asynchronously accumulated on writes 468 */ 469 #define SCTLR_TCF_SYNCR_ASYNCW U(3) 470 471 #define SCTLR_ATA0_BIT (ULL(1) << 42) 472 #define SCTLR_ATA_BIT (ULL(1) << 43) 473 #define SCTLR_DSSBS_SHIFT U(44) 474 #define SCTLR_DSSBS_BIT (ULL(1) << SCTLR_DSSBS_SHIFT) 475 #define SCTLR_TWEDEn_BIT (ULL(1) << 45) 476 #define SCTLR_TWEDEL_SHIFT U(46) 477 #define SCTLR_TWEDEL_MASK ULL(0xf) 478 #define SCTLR_EnASR_BIT (ULL(1) << 54) 479 #define SCTLR_EnAS0_BIT (ULL(1) << 55) 480 #define SCTLR_EnALS_BIT (ULL(1) << 56) 481 #define SCTLR_EPAN_BIT (ULL(1) << 57) 482 #define SCTLR_RESET_VAL SCTLR_EL3_RES1 483 484 /* CPACR_EL1 definitions */ 485 #define CPACR_EL1_FPEN(x) ((x) << 20) 486 #define CPACR_EL1_FP_TRAP_EL0 UL(0x1) 487 #define CPACR_EL1_FP_TRAP_ALL UL(0x2) 488 #define CPACR_EL1_FP_TRAP_NONE UL(0x3) 489 490 /* SCR definitions */ 491 #define SCR_RES1_BITS ((U(1) << 4) | (U(1) << 5)) 492 #define SCR_NSE_SHIFT U(62) 493 #define SCR_NSE_BIT (ULL(1) << SCR_NSE_SHIFT) 494 #define SCR_GPF_BIT (UL(1) << 48) 495 #define SCR_TWEDEL_SHIFT U(30) 496 #define SCR_TWEDEL_MASK ULL(0xf) 497 #define SCR_HXEn_BIT (UL(1) << 38) 498 #define SCR_ENTP2_SHIFT U(41) 499 #define SCR_ENTP2_BIT (UL(1) << SCR_ENTP2_SHIFT) 500 #define SCR_AMVOFFEN_SHIFT U(35) 501 #define SCR_AMVOFFEN_BIT (UL(1) << SCR_AMVOFFEN_SHIFT) 502 #define SCR_TWEDEn_BIT (UL(1) << 29) 503 #define SCR_ECVEN_BIT (UL(1) << 28) 504 #define SCR_FGTEN_BIT (UL(1) << 27) 505 #define SCR_ATA_BIT (UL(1) << 26) 506 #define SCR_EnSCXT_BIT (UL(1) << 25) 507 #define SCR_FIEN_BIT (UL(1) << 21) 508 #define SCR_EEL2_BIT (UL(1) << 18) 509 #define SCR_API_BIT (UL(1) << 17) 510 #define SCR_APK_BIT (UL(1) << 16) 511 #define SCR_TERR_BIT (UL(1) << 15) 512 #define SCR_TWE_BIT (UL(1) << 13) 513 #define SCR_TWI_BIT (UL(1) << 12) 514 #define SCR_ST_BIT (UL(1) << 11) 515 #define SCR_RW_BIT (UL(1) << 10) 516 #define SCR_SIF_BIT (UL(1) << 9) 517 #define SCR_HCE_BIT (UL(1) << 8) 518 #define SCR_SMD_BIT (UL(1) << 7) 519 #define SCR_EA_BIT (UL(1) << 3) 520 #define SCR_FIQ_BIT (UL(1) << 2) 521 #define SCR_IRQ_BIT (UL(1) << 1) 522 #define SCR_NS_BIT (UL(1) << 0) 523 #define SCR_VALID_BIT_MASK U(0x24000002F8F) 524 #define SCR_RESET_VAL SCR_RES1_BITS 525 526 /* MDCR_EL3 definitions */ 527 #define MDCR_EnPMSN_BIT (ULL(1) << 36) 528 #define MDCR_MPMX_BIT (ULL(1) << 35) 529 #define MDCR_MCCD_BIT (ULL(1) << 34) 530 #define MDCR_SBRBE_SHIFT U(32) 531 #define MDCR_SBRBE_MASK ULL(0x3) 532 #define MDCR_NSTB(x) ((x) << 24) 533 #define MDCR_NSTB_EL1 ULL(0x3) 534 #define MDCR_NSTBE (ULL(1) << 26) 535 #define MDCR_MTPME_BIT (ULL(1) << 28) 536 #define MDCR_TDCC_BIT (ULL(1) << 27) 537 #define MDCR_SCCD_BIT (ULL(1) << 23) 538 #define MDCR_EPMAD_BIT (ULL(1) << 21) 539 #define MDCR_EDAD_BIT (ULL(1) << 20) 540 #define MDCR_TTRF_BIT (ULL(1) << 19) 541 #define MDCR_STE_BIT (ULL(1) << 18) 542 #define MDCR_SPME_BIT (ULL(1) << 17) 543 #define MDCR_SDD_BIT (ULL(1) << 16) 544 #define MDCR_SPD32(x) ((x) << 14) 545 #define MDCR_SPD32_LEGACY ULL(0x0) 546 #define MDCR_SPD32_DISABLE ULL(0x2) 547 #define MDCR_SPD32_ENABLE ULL(0x3) 548 #define MDCR_NSPB(x) ((x) << 12) 549 #define MDCR_NSPB_EL1 ULL(0x3) 550 #define MDCR_TDOSA_BIT (ULL(1) << 10) 551 #define MDCR_TDA_BIT (ULL(1) << 9) 552 #define MDCR_TPM_BIT (ULL(1) << 6) 553 #define MDCR_EL3_RESET_VAL ULL(0x0) 554 555 /* MDCR_EL2 definitions */ 556 #define MDCR_EL2_MTPME (U(1) << 28) 557 #define MDCR_EL2_HLP (U(1) << 26) 558 #define MDCR_EL2_E2TB(x) ((x) << 24) 559 #define MDCR_EL2_E2TB_EL1 U(0x3) 560 #define MDCR_EL2_HCCD (U(1) << 23) 561 #define MDCR_EL2_TTRF (U(1) << 19) 562 #define MDCR_EL2_HPMD (U(1) << 17) 563 #define MDCR_EL2_TPMS (U(1) << 14) 564 #define MDCR_EL2_E2PB(x) ((x) << 12) 565 #define MDCR_EL2_E2PB_EL1 U(0x3) 566 #define MDCR_EL2_TDRA_BIT (U(1) << 11) 567 #define MDCR_EL2_TDOSA_BIT (U(1) << 10) 568 #define MDCR_EL2_TDA_BIT (U(1) << 9) 569 #define MDCR_EL2_TDE_BIT (U(1) << 8) 570 #define MDCR_EL2_HPME_BIT (U(1) << 7) 571 #define MDCR_EL2_TPM_BIT (U(1) << 6) 572 #define MDCR_EL2_TPMCR_BIT (U(1) << 5) 573 #define MDCR_EL2_RESET_VAL U(0x0) 574 575 /* HSTR_EL2 definitions */ 576 #define HSTR_EL2_RESET_VAL U(0x0) 577 #define HSTR_EL2_T_MASK U(0xff) 578 579 /* CNTHP_CTL_EL2 definitions */ 580 #define CNTHP_CTL_ENABLE_BIT (U(1) << 0) 581 #define CNTHP_CTL_RESET_VAL U(0x0) 582 583 /* VTTBR_EL2 definitions */ 584 #define VTTBR_RESET_VAL ULL(0x0) 585 #define VTTBR_VMID_MASK ULL(0xff) 586 #define VTTBR_VMID_SHIFT U(48) 587 #define VTTBR_BADDR_MASK ULL(0xffffffffffff) 588 #define VTTBR_BADDR_SHIFT U(0) 589 590 /* HCR definitions */ 591 #define HCR_RESET_VAL ULL(0x0) 592 #define HCR_AMVOFFEN_SHIFT U(51) 593 #define HCR_AMVOFFEN_BIT (ULL(1) << HCR_AMVOFFEN_SHIFT) 594 #define HCR_TEA_BIT (ULL(1) << 47) 595 #define HCR_API_BIT (ULL(1) << 41) 596 #define HCR_APK_BIT (ULL(1) << 40) 597 #define HCR_E2H_BIT (ULL(1) << 34) 598 #define HCR_HCD_BIT (ULL(1) << 29) 599 #define HCR_TGE_BIT (ULL(1) << 27) 600 #define HCR_RW_SHIFT U(31) 601 #define HCR_RW_BIT (ULL(1) << HCR_RW_SHIFT) 602 #define HCR_TWE_BIT (ULL(1) << 14) 603 #define HCR_TWI_BIT (ULL(1) << 13) 604 #define HCR_AMO_BIT (ULL(1) << 5) 605 #define HCR_IMO_BIT (ULL(1) << 4) 606 #define HCR_FMO_BIT (ULL(1) << 3) 607 608 /* ISR definitions */ 609 #define ISR_A_SHIFT U(8) 610 #define ISR_I_SHIFT U(7) 611 #define ISR_F_SHIFT U(6) 612 613 /* CNTHCTL_EL2 definitions */ 614 #define CNTHCTL_RESET_VAL U(0x0) 615 #define EVNTEN_BIT (U(1) << 2) 616 #define EL1PCEN_BIT (U(1) << 1) 617 #define EL1PCTEN_BIT (U(1) << 0) 618 619 /* CNTKCTL_EL1 definitions */ 620 #define EL0PTEN_BIT (U(1) << 9) 621 #define EL0VTEN_BIT (U(1) << 8) 622 #define EL0PCTEN_BIT (U(1) << 0) 623 #define EL0VCTEN_BIT (U(1) << 1) 624 #define EVNTEN_BIT (U(1) << 2) 625 #define EVNTDIR_BIT (U(1) << 3) 626 #define EVNTI_SHIFT U(4) 627 #define EVNTI_MASK U(0xf) 628 629 /* CPTR_EL3 definitions */ 630 #define TCPAC_BIT (U(1) << 31) 631 #define TAM_SHIFT U(30) 632 #define TAM_BIT (U(1) << TAM_SHIFT) 633 #define TTA_BIT (U(1) << 20) 634 #define ESM_BIT (U(1) << 12) 635 #define TFP_BIT (U(1) << 10) 636 #define CPTR_EZ_BIT (U(1) << 8) 637 #define CPTR_EL3_RESET_VAL ((TCPAC_BIT | TAM_BIT | TTA_BIT | TFP_BIT) & \ 638 ~(CPTR_EZ_BIT | ESM_BIT)) 639 640 /* CPTR_EL2 definitions */ 641 #define CPTR_EL2_RES1 ((U(1) << 13) | (U(1) << 12) | (U(0x3ff))) 642 #define CPTR_EL2_TCPAC_BIT (U(1) << 31) 643 #define CPTR_EL2_TAM_SHIFT U(30) 644 #define CPTR_EL2_TAM_BIT (U(1) << CPTR_EL2_TAM_SHIFT) 645 #define CPTR_EL2_SMEN_MASK ULL(0x3) 646 #define CPTR_EL2_SMEN_SHIFT U(24) 647 #define CPTR_EL2_TTA_BIT (U(1) << 20) 648 #define CPTR_EL2_TSM_BIT (U(1) << 12) 649 #define CPTR_EL2_TFP_BIT (U(1) << 10) 650 #define CPTR_EL2_TZ_BIT (U(1) << 8) 651 #define CPTR_EL2_RESET_VAL CPTR_EL2_RES1 652 653 /* VTCR_EL2 definitions */ 654 #define VTCR_RESET_VAL U(0x0) 655 #define VTCR_EL2_MSA (U(1) << 31) 656 657 /* CPSR/SPSR definitions */ 658 #define DAIF_FIQ_BIT (U(1) << 0) 659 #define DAIF_IRQ_BIT (U(1) << 1) 660 #define DAIF_ABT_BIT (U(1) << 2) 661 #define DAIF_DBG_BIT (U(1) << 3) 662 #define SPSR_DAIF_SHIFT U(6) 663 #define SPSR_DAIF_MASK U(0xf) 664 665 #define SPSR_AIF_SHIFT U(6) 666 #define SPSR_AIF_MASK U(0x7) 667 668 #define SPSR_E_SHIFT U(9) 669 #define SPSR_E_MASK U(0x1) 670 #define SPSR_E_LITTLE U(0x0) 671 #define SPSR_E_BIG U(0x1) 672 673 #define SPSR_T_SHIFT U(5) 674 #define SPSR_T_MASK U(0x1) 675 #define SPSR_T_ARM U(0x0) 676 #define SPSR_T_THUMB U(0x1) 677 678 #define SPSR_M_SHIFT U(4) 679 #define SPSR_M_MASK U(0x1) 680 #define SPSR_M_AARCH64 U(0x0) 681 #define SPSR_M_AARCH32 U(0x1) 682 #define SPSR_M_EL2H U(0x9) 683 684 #define SPSR_EL_SHIFT U(2) 685 #define SPSR_EL_WIDTH U(2) 686 687 #define SPSR_SSBS_SHIFT_AARCH64 U(12) 688 #define SPSR_SSBS_BIT_AARCH64 (ULL(1) << SPSR_SSBS_SHIFT_AARCH64) 689 #define SPSR_SSBS_SHIFT_AARCH32 U(23) 690 #define SPSR_SSBS_BIT_AARCH32 (ULL(1) << SPSR_SSBS_SHIFT_AARCH32) 691 692 #define SPSR_PAN_BIT BIT_64(22) 693 694 #define SPSR_DIT_BIT BIT(24) 695 696 #define SPSR_TCO_BIT_AARCH64 BIT_64(25) 697 698 #define DISABLE_ALL_EXCEPTIONS \ 699 (DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT | DAIF_DBG_BIT) 700 701 #define DISABLE_INTERRUPTS (DAIF_FIQ_BIT | DAIF_IRQ_BIT) 702 703 /* 704 * RMR_EL3 definitions 705 */ 706 #define RMR_EL3_RR_BIT (U(1) << 1) 707 #define RMR_EL3_AA64_BIT (U(1) << 0) 708 709 /* 710 * HI-VECTOR address for AArch32 state 711 */ 712 #define HI_VECTOR_BASE U(0xFFFF0000) 713 714 /* 715 * TCR defintions 716 */ 717 #define TCR_EL3_RES1 ((ULL(1) << 31) | (ULL(1) << 23)) 718 #define TCR_EL2_RES1 ((ULL(1) << 31) | (ULL(1) << 23)) 719 #define TCR_EL1_IPS_SHIFT U(32) 720 #define TCR_EL2_PS_SHIFT U(16) 721 #define TCR_EL3_PS_SHIFT U(16) 722 723 #define TCR_TxSZ_MIN ULL(16) 724 #define TCR_TxSZ_MAX ULL(39) 725 #define TCR_TxSZ_MAX_TTST ULL(48) 726 727 #define TCR_T0SZ_SHIFT U(0) 728 #define TCR_T1SZ_SHIFT U(16) 729 730 /* (internal) physical address size bits in EL3/EL1 */ 731 #define TCR_PS_BITS_4GB ULL(0x0) 732 #define TCR_PS_BITS_64GB ULL(0x1) 733 #define TCR_PS_BITS_1TB ULL(0x2) 734 #define TCR_PS_BITS_4TB ULL(0x3) 735 #define TCR_PS_BITS_16TB ULL(0x4) 736 #define TCR_PS_BITS_256TB ULL(0x5) 737 738 #define ADDR_MASK_48_TO_63 ULL(0xFFFF000000000000) 739 #define ADDR_MASK_44_TO_47 ULL(0x0000F00000000000) 740 #define ADDR_MASK_42_TO_43 ULL(0x00000C0000000000) 741 #define ADDR_MASK_40_TO_41 ULL(0x0000030000000000) 742 #define ADDR_MASK_36_TO_39 ULL(0x000000F000000000) 743 #define ADDR_MASK_32_TO_35 ULL(0x0000000F00000000) 744 745 #define TCR_RGN_INNER_NC (ULL(0x0) << 8) 746 #define TCR_RGN_INNER_WBA (ULL(0x1) << 8) 747 #define TCR_RGN_INNER_WT (ULL(0x2) << 8) 748 #define TCR_RGN_INNER_WBNA (ULL(0x3) << 8) 749 750 #define TCR_RGN_OUTER_NC (ULL(0x0) << 10) 751 #define TCR_RGN_OUTER_WBA (ULL(0x1) << 10) 752 #define TCR_RGN_OUTER_WT (ULL(0x2) << 10) 753 #define TCR_RGN_OUTER_WBNA (ULL(0x3) << 10) 754 755 #define TCR_SH_NON_SHAREABLE (ULL(0x0) << 12) 756 #define TCR_SH_OUTER_SHAREABLE (ULL(0x2) << 12) 757 #define TCR_SH_INNER_SHAREABLE (ULL(0x3) << 12) 758 759 #define TCR_RGN1_INNER_NC (ULL(0x0) << 24) 760 #define TCR_RGN1_INNER_WBA (ULL(0x1) << 24) 761 #define TCR_RGN1_INNER_WT (ULL(0x2) << 24) 762 #define TCR_RGN1_INNER_WBNA (ULL(0x3) << 24) 763 764 #define TCR_RGN1_OUTER_NC (ULL(0x0) << 26) 765 #define TCR_RGN1_OUTER_WBA (ULL(0x1) << 26) 766 #define TCR_RGN1_OUTER_WT (ULL(0x2) << 26) 767 #define TCR_RGN1_OUTER_WBNA (ULL(0x3) << 26) 768 769 #define TCR_SH1_NON_SHAREABLE (ULL(0x0) << 28) 770 #define TCR_SH1_OUTER_SHAREABLE (ULL(0x2) << 28) 771 #define TCR_SH1_INNER_SHAREABLE (ULL(0x3) << 28) 772 773 #define TCR_TG0_SHIFT U(14) 774 #define TCR_TG0_MASK ULL(3) 775 #define TCR_TG0_4K (ULL(0) << TCR_TG0_SHIFT) 776 #define TCR_TG0_64K (ULL(1) << TCR_TG0_SHIFT) 777 #define TCR_TG0_16K (ULL(2) << TCR_TG0_SHIFT) 778 779 #define TCR_TG1_SHIFT U(30) 780 #define TCR_TG1_MASK ULL(3) 781 #define TCR_TG1_16K (ULL(1) << TCR_TG1_SHIFT) 782 #define TCR_TG1_4K (ULL(2) << TCR_TG1_SHIFT) 783 #define TCR_TG1_64K (ULL(3) << TCR_TG1_SHIFT) 784 785 #define TCR_EPD0_BIT (ULL(1) << 7) 786 #define TCR_EPD1_BIT (ULL(1) << 23) 787 788 #define MODE_SP_SHIFT U(0x0) 789 #define MODE_SP_MASK U(0x1) 790 #define MODE_SP_EL0 U(0x0) 791 #define MODE_SP_ELX U(0x1) 792 793 #define MODE_RW_SHIFT U(0x4) 794 #define MODE_RW_MASK U(0x1) 795 #define MODE_RW_64 U(0x0) 796 #define MODE_RW_32 U(0x1) 797 798 #define MODE_EL_SHIFT U(0x2) 799 #define MODE_EL_MASK U(0x3) 800 #define MODE_EL_WIDTH U(0x2) 801 #define MODE_EL3 U(0x3) 802 #define MODE_EL2 U(0x2) 803 #define MODE_EL1 U(0x1) 804 #define MODE_EL0 U(0x0) 805 806 #define MODE32_SHIFT U(0) 807 #define MODE32_MASK U(0xf) 808 #define MODE32_usr U(0x0) 809 #define MODE32_fiq U(0x1) 810 #define MODE32_irq U(0x2) 811 #define MODE32_svc U(0x3) 812 #define MODE32_mon U(0x6) 813 #define MODE32_abt U(0x7) 814 #define MODE32_hyp U(0xa) 815 #define MODE32_und U(0xb) 816 #define MODE32_sys U(0xf) 817 818 #define GET_RW(mode) (((mode) >> MODE_RW_SHIFT) & MODE_RW_MASK) 819 #define GET_EL(mode) (((mode) >> MODE_EL_SHIFT) & MODE_EL_MASK) 820 #define GET_SP(mode) (((mode) >> MODE_SP_SHIFT) & MODE_SP_MASK) 821 #define GET_M32(mode) (((mode) >> MODE32_SHIFT) & MODE32_MASK) 822 823 #define SPSR_64(el, sp, daif) \ 824 (((MODE_RW_64 << MODE_RW_SHIFT) | \ 825 (((el) & MODE_EL_MASK) << MODE_EL_SHIFT) | \ 826 (((sp) & MODE_SP_MASK) << MODE_SP_SHIFT) | \ 827 (((daif) & SPSR_DAIF_MASK) << SPSR_DAIF_SHIFT)) & \ 828 (~(SPSR_SSBS_BIT_AARCH64))) 829 830 #define SPSR_MODE32(mode, isa, endian, aif) \ 831 (((MODE_RW_32 << MODE_RW_SHIFT) | \ 832 (((mode) & MODE32_MASK) << MODE32_SHIFT) | \ 833 (((isa) & SPSR_T_MASK) << SPSR_T_SHIFT) | \ 834 (((endian) & SPSR_E_MASK) << SPSR_E_SHIFT) | \ 835 (((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT)) & \ 836 (~(SPSR_SSBS_BIT_AARCH32))) 837 838 /* 839 * TTBR Definitions 840 */ 841 #define TTBR_CNP_BIT ULL(0x1) 842 843 /* 844 * CTR_EL0 definitions 845 */ 846 #define CTR_CWG_SHIFT U(24) 847 #define CTR_CWG_MASK U(0xf) 848 #define CTR_ERG_SHIFT U(20) 849 #define CTR_ERG_MASK U(0xf) 850 #define CTR_DMINLINE_SHIFT U(16) 851 #define CTR_DMINLINE_MASK U(0xf) 852 #define CTR_L1IP_SHIFT U(14) 853 #define CTR_L1IP_MASK U(0x3) 854 #define CTR_IMINLINE_SHIFT U(0) 855 #define CTR_IMINLINE_MASK U(0xf) 856 857 #define MAX_CACHE_LINE_SIZE U(0x800) /* 2KB */ 858 859 /* Physical timer control register bit fields shifts and masks */ 860 #define CNTP_CTL_ENABLE_SHIFT U(0) 861 #define CNTP_CTL_IMASK_SHIFT U(1) 862 #define CNTP_CTL_ISTATUS_SHIFT U(2) 863 864 #define CNTP_CTL_ENABLE_MASK U(1) 865 #define CNTP_CTL_IMASK_MASK U(1) 866 #define CNTP_CTL_ISTATUS_MASK U(1) 867 868 /* Physical timer control macros */ 869 #define CNTP_CTL_ENABLE_BIT (U(1) << CNTP_CTL_ENABLE_SHIFT) 870 #define CNTP_CTL_IMASK_BIT (U(1) << CNTP_CTL_IMASK_SHIFT) 871 872 /* Exception Syndrome register bits and bobs */ 873 #define ESR_EC_SHIFT U(26) 874 #define ESR_EC_MASK U(0x3f) 875 #define ESR_EC_LENGTH U(6) 876 #define ESR_ISS_SHIFT U(0) 877 #define ESR_ISS_LENGTH U(25) 878 #define EC_UNKNOWN U(0x0) 879 #define EC_WFE_WFI U(0x1) 880 #define EC_AARCH32_CP15_MRC_MCR U(0x3) 881 #define EC_AARCH32_CP15_MRRC_MCRR U(0x4) 882 #define EC_AARCH32_CP14_MRC_MCR U(0x5) 883 #define EC_AARCH32_CP14_LDC_STC U(0x6) 884 #define EC_FP_SIMD U(0x7) 885 #define EC_AARCH32_CP10_MRC U(0x8) 886 #define EC_AARCH32_CP14_MRRC_MCRR U(0xc) 887 #define EC_ILLEGAL U(0xe) 888 #define EC_AARCH32_SVC U(0x11) 889 #define EC_AARCH32_HVC U(0x12) 890 #define EC_AARCH32_SMC U(0x13) 891 #define EC_AARCH64_SVC U(0x15) 892 #define EC_AARCH64_HVC U(0x16) 893 #define EC_AARCH64_SMC U(0x17) 894 #define EC_AARCH64_SYS U(0x18) 895 #define EC_IABORT_LOWER_EL U(0x20) 896 #define EC_IABORT_CUR_EL U(0x21) 897 #define EC_PC_ALIGN U(0x22) 898 #define EC_DABORT_LOWER_EL U(0x24) 899 #define EC_DABORT_CUR_EL U(0x25) 900 #define EC_SP_ALIGN U(0x26) 901 #define EC_AARCH32_FP U(0x28) 902 #define EC_AARCH64_FP U(0x2c) 903 #define EC_SERROR U(0x2f) 904 #define EC_BRK U(0x3c) 905 906 /* 907 * External Abort bit in Instruction and Data Aborts synchronous exception 908 * syndromes. 909 */ 910 #define ESR_ISS_EABORT_EA_BIT U(9) 911 912 #define EC_BITS(x) (((x) >> ESR_EC_SHIFT) & ESR_EC_MASK) 913 914 /* Reset bit inside the Reset management register for EL3 (RMR_EL3) */ 915 #define RMR_RESET_REQUEST_SHIFT U(0x1) 916 #define RMR_WARM_RESET_CPU (U(1) << RMR_RESET_REQUEST_SHIFT) 917 918 /******************************************************************************* 919 * Definitions of register offsets, fields and macros for CPU system 920 * instructions. 921 ******************************************************************************/ 922 923 #define TLBI_ADDR_SHIFT U(12) 924 #define TLBI_ADDR_MASK ULL(0x00000FFFFFFFFFFF) 925 #define TLBI_ADDR(x) (((x) >> TLBI_ADDR_SHIFT) & TLBI_ADDR_MASK) 926 927 /******************************************************************************* 928 * Definitions of register offsets and fields in the CNTCTLBase Frame of the 929 * system level implementation of the Generic Timer. 930 ******************************************************************************/ 931 #define CNTCTLBASE_CNTFRQ U(0x0) 932 #define CNTNSAR U(0x4) 933 #define CNTNSAR_NS_SHIFT(x) (x) 934 935 #define CNTACR_BASE(x) (U(0x40) + ((x) << 2)) 936 #define CNTACR_RPCT_SHIFT U(0x0) 937 #define CNTACR_RVCT_SHIFT U(0x1) 938 #define CNTACR_RFRQ_SHIFT U(0x2) 939 #define CNTACR_RVOFF_SHIFT U(0x3) 940 #define CNTACR_RWVT_SHIFT U(0x4) 941 #define CNTACR_RWPT_SHIFT U(0x5) 942 943 /******************************************************************************* 944 * Definitions of register offsets and fields in the CNTBaseN Frame of the 945 * system level implementation of the Generic Timer. 946 ******************************************************************************/ 947 /* Physical Count register. */ 948 #define CNTPCT_LO U(0x0) 949 /* Counter Frequency register. */ 950 #define CNTBASEN_CNTFRQ U(0x10) 951 /* Physical Timer CompareValue register. */ 952 #define CNTP_CVAL_LO U(0x20) 953 /* Physical Timer Control register. */ 954 #define CNTP_CTL U(0x2c) 955 956 /* PMCR_EL0 definitions */ 957 #define PMCR_EL0_RESET_VAL U(0x0) 958 #define PMCR_EL0_N_SHIFT U(11) 959 #define PMCR_EL0_N_MASK U(0x1f) 960 #define PMCR_EL0_N_BITS (PMCR_EL0_N_MASK << PMCR_EL0_N_SHIFT) 961 #define PMCR_EL0_LP_BIT (U(1) << 7) 962 #define PMCR_EL0_LC_BIT (U(1) << 6) 963 #define PMCR_EL0_DP_BIT (U(1) << 5) 964 #define PMCR_EL0_X_BIT (U(1) << 4) 965 #define PMCR_EL0_D_BIT (U(1) << 3) 966 #define PMCR_EL0_C_BIT (U(1) << 2) 967 #define PMCR_EL0_P_BIT (U(1) << 1) 968 #define PMCR_EL0_E_BIT (U(1) << 0) 969 970 /******************************************************************************* 971 * Definitions for system register interface to SVE 972 ******************************************************************************/ 973 #define ZCR_EL3 S3_6_C1_C2_0 974 #define ZCR_EL2 S3_4_C1_C2_0 975 976 /* ZCR_EL3 definitions */ 977 #define ZCR_EL3_LEN_MASK U(0xf) 978 979 /* ZCR_EL2 definitions */ 980 #define ZCR_EL2_LEN_MASK U(0xf) 981 982 /******************************************************************************* 983 * Definitions for system register interface to SME as needed in EL3 984 ******************************************************************************/ 985 #define ID_AA64SMFR0_EL1 S3_0_C0_C4_5 986 #define SMCR_EL3 S3_6_C1_C2_6 987 988 /* ID_AA64SMFR0_EL1 definitions */ 989 #define ID_AA64SMFR0_EL1_FA64_BIT (UL(1) << 63) 990 991 /* SMCR_ELx definitions */ 992 #define SMCR_ELX_LEN_SHIFT U(0) 993 #define SMCR_ELX_LEN_MASK U(0x1ff) 994 #define SMCR_ELX_FA64_BIT (U(1) << 31) 995 996 /******************************************************************************* 997 * Definitions of MAIR encodings for device and normal memory 998 ******************************************************************************/ 999 /* 1000 * MAIR encodings for device memory attributes. 1001 */ 1002 #define MAIR_DEV_nGnRnE ULL(0x0) 1003 #define MAIR_DEV_nGnRE ULL(0x4) 1004 #define MAIR_DEV_nGRE ULL(0x8) 1005 #define MAIR_DEV_GRE ULL(0xc) 1006 1007 /* 1008 * MAIR encodings for normal memory attributes. 1009 * 1010 * Cache Policy 1011 * WT: Write Through 1012 * WB: Write Back 1013 * NC: Non-Cacheable 1014 * 1015 * Transient Hint 1016 * NTR: Non-Transient 1017 * TR: Transient 1018 * 1019 * Allocation Policy 1020 * RA: Read Allocate 1021 * WA: Write Allocate 1022 * RWA: Read and Write Allocate 1023 * NA: No Allocation 1024 */ 1025 #define MAIR_NORM_WT_TR_WA ULL(0x1) 1026 #define MAIR_NORM_WT_TR_RA ULL(0x2) 1027 #define MAIR_NORM_WT_TR_RWA ULL(0x3) 1028 #define MAIR_NORM_NC ULL(0x4) 1029 #define MAIR_NORM_WB_TR_WA ULL(0x5) 1030 #define MAIR_NORM_WB_TR_RA ULL(0x6) 1031 #define MAIR_NORM_WB_TR_RWA ULL(0x7) 1032 #define MAIR_NORM_WT_NTR_NA ULL(0x8) 1033 #define MAIR_NORM_WT_NTR_WA ULL(0x9) 1034 #define MAIR_NORM_WT_NTR_RA ULL(0xa) 1035 #define MAIR_NORM_WT_NTR_RWA ULL(0xb) 1036 #define MAIR_NORM_WB_NTR_NA ULL(0xc) 1037 #define MAIR_NORM_WB_NTR_WA ULL(0xd) 1038 #define MAIR_NORM_WB_NTR_RA ULL(0xe) 1039 #define MAIR_NORM_WB_NTR_RWA ULL(0xf) 1040 1041 #define MAIR_NORM_OUTER_SHIFT U(4) 1042 1043 #define MAKE_MAIR_NORMAL_MEMORY(inner, outer) \ 1044 ((inner) | ((outer) << MAIR_NORM_OUTER_SHIFT)) 1045 1046 /* PAR_EL1 fields */ 1047 #define PAR_F_SHIFT U(0) 1048 #define PAR_F_MASK ULL(0x1) 1049 #define PAR_ADDR_SHIFT U(12) 1050 #define PAR_ADDR_MASK (BIT(40) - ULL(1)) /* 40-bits-wide page address */ 1051 1052 /******************************************************************************* 1053 * Definitions for system register interface to SPE 1054 ******************************************************************************/ 1055 #define PMBLIMITR_EL1 S3_0_C9_C10_0 1056 1057 /******************************************************************************* 1058 * Definitions for system register interface to MPAM 1059 ******************************************************************************/ 1060 #define MPAMIDR_EL1 S3_0_C10_C4_4 1061 #define MPAM2_EL2 S3_4_C10_C5_0 1062 #define MPAMHCR_EL2 S3_4_C10_C4_0 1063 #define MPAM3_EL3 S3_6_C10_C5_0 1064 1065 /******************************************************************************* 1066 * Definitions for system register interface to AMU for FEAT_AMUv1 1067 ******************************************************************************/ 1068 #define AMCR_EL0 S3_3_C13_C2_0 1069 #define AMCFGR_EL0 S3_3_C13_C2_1 1070 #define AMCGCR_EL0 S3_3_C13_C2_2 1071 #define AMUSERENR_EL0 S3_3_C13_C2_3 1072 #define AMCNTENCLR0_EL0 S3_3_C13_C2_4 1073 #define AMCNTENSET0_EL0 S3_3_C13_C2_5 1074 #define AMCNTENCLR1_EL0 S3_3_C13_C3_0 1075 #define AMCNTENSET1_EL0 S3_3_C13_C3_1 1076 1077 /* Activity Monitor Group 0 Event Counter Registers */ 1078 #define AMEVCNTR00_EL0 S3_3_C13_C4_0 1079 #define AMEVCNTR01_EL0 S3_3_C13_C4_1 1080 #define AMEVCNTR02_EL0 S3_3_C13_C4_2 1081 #define AMEVCNTR03_EL0 S3_3_C13_C4_3 1082 1083 /* Activity Monitor Group 0 Event Type Registers */ 1084 #define AMEVTYPER00_EL0 S3_3_C13_C6_0 1085 #define AMEVTYPER01_EL0 S3_3_C13_C6_1 1086 #define AMEVTYPER02_EL0 S3_3_C13_C6_2 1087 #define AMEVTYPER03_EL0 S3_3_C13_C6_3 1088 1089 /* Activity Monitor Group 1 Event Counter Registers */ 1090 #define AMEVCNTR10_EL0 S3_3_C13_C12_0 1091 #define AMEVCNTR11_EL0 S3_3_C13_C12_1 1092 #define AMEVCNTR12_EL0 S3_3_C13_C12_2 1093 #define AMEVCNTR13_EL0 S3_3_C13_C12_3 1094 #define AMEVCNTR14_EL0 S3_3_C13_C12_4 1095 #define AMEVCNTR15_EL0 S3_3_C13_C12_5 1096 #define AMEVCNTR16_EL0 S3_3_C13_C12_6 1097 #define AMEVCNTR17_EL0 S3_3_C13_C12_7 1098 #define AMEVCNTR18_EL0 S3_3_C13_C13_0 1099 #define AMEVCNTR19_EL0 S3_3_C13_C13_1 1100 #define AMEVCNTR1A_EL0 S3_3_C13_C13_2 1101 #define AMEVCNTR1B_EL0 S3_3_C13_C13_3 1102 #define AMEVCNTR1C_EL0 S3_3_C13_C13_4 1103 #define AMEVCNTR1D_EL0 S3_3_C13_C13_5 1104 #define AMEVCNTR1E_EL0 S3_3_C13_C13_6 1105 #define AMEVCNTR1F_EL0 S3_3_C13_C13_7 1106 1107 /* Activity Monitor Group 1 Event Type Registers */ 1108 #define AMEVTYPER10_EL0 S3_3_C13_C14_0 1109 #define AMEVTYPER11_EL0 S3_3_C13_C14_1 1110 #define AMEVTYPER12_EL0 S3_3_C13_C14_2 1111 #define AMEVTYPER13_EL0 S3_3_C13_C14_3 1112 #define AMEVTYPER14_EL0 S3_3_C13_C14_4 1113 #define AMEVTYPER15_EL0 S3_3_C13_C14_5 1114 #define AMEVTYPER16_EL0 S3_3_C13_C14_6 1115 #define AMEVTYPER17_EL0 S3_3_C13_C14_7 1116 #define AMEVTYPER18_EL0 S3_3_C13_C15_0 1117 #define AMEVTYPER19_EL0 S3_3_C13_C15_1 1118 #define AMEVTYPER1A_EL0 S3_3_C13_C15_2 1119 #define AMEVTYPER1B_EL0 S3_3_C13_C15_3 1120 #define AMEVTYPER1C_EL0 S3_3_C13_C15_4 1121 #define AMEVTYPER1D_EL0 S3_3_C13_C15_5 1122 #define AMEVTYPER1E_EL0 S3_3_C13_C15_6 1123 #define AMEVTYPER1F_EL0 S3_3_C13_C15_7 1124 1125 /* AMCNTENSET0_EL0 definitions */ 1126 #define AMCNTENSET0_EL0_Pn_SHIFT U(0) 1127 #define AMCNTENSET0_EL0_Pn_MASK ULL(0xffff) 1128 1129 /* AMCNTENSET1_EL0 definitions */ 1130 #define AMCNTENSET1_EL0_Pn_SHIFT U(0) 1131 #define AMCNTENSET1_EL0_Pn_MASK ULL(0xffff) 1132 1133 /* AMCNTENCLR0_EL0 definitions */ 1134 #define AMCNTENCLR0_EL0_Pn_SHIFT U(0) 1135 #define AMCNTENCLR0_EL0_Pn_MASK ULL(0xffff) 1136 1137 /* AMCNTENCLR1_EL0 definitions */ 1138 #define AMCNTENCLR1_EL0_Pn_SHIFT U(0) 1139 #define AMCNTENCLR1_EL0_Pn_MASK ULL(0xffff) 1140 1141 /* AMCFGR_EL0 definitions */ 1142 #define AMCFGR_EL0_NCG_SHIFT U(28) 1143 #define AMCFGR_EL0_NCG_MASK U(0xf) 1144 #define AMCFGR_EL0_N_SHIFT U(0) 1145 #define AMCFGR_EL0_N_MASK U(0xff) 1146 1147 /* AMCGCR_EL0 definitions */ 1148 #define AMCGCR_EL0_CG0NC_SHIFT U(0) 1149 #define AMCGCR_EL0_CG0NC_MASK U(0xff) 1150 #define AMCGCR_EL0_CG1NC_SHIFT U(8) 1151 #define AMCGCR_EL0_CG1NC_MASK U(0xff) 1152 1153 /* MPAM register definitions */ 1154 #define MPAM3_EL3_MPAMEN_BIT (ULL(1) << 63) 1155 #define MPAMHCR_EL2_TRAP_MPAMIDR_EL1 (ULL(1) << 31) 1156 1157 #define MPAM2_EL2_TRAPMPAM0EL1 (ULL(1) << 49) 1158 #define MPAM2_EL2_TRAPMPAM1EL1 (ULL(1) << 48) 1159 1160 #define MPAMIDR_HAS_HCR_BIT (ULL(1) << 17) 1161 1162 /******************************************************************************* 1163 * Definitions for system register interface to AMU for FEAT_AMUv1p1 1164 ******************************************************************************/ 1165 1166 /* Definition for register defining which virtual offsets are implemented. */ 1167 #define AMCG1IDR_EL0 S3_3_C13_C2_6 1168 #define AMCG1IDR_CTR_MASK ULL(0xffff) 1169 #define AMCG1IDR_CTR_SHIFT U(0) 1170 #define AMCG1IDR_VOFF_MASK ULL(0xffff) 1171 #define AMCG1IDR_VOFF_SHIFT U(16) 1172 1173 /* New bit added to AMCR_EL0 */ 1174 #define AMCR_CG1RZ_SHIFT U(17) 1175 #define AMCR_CG1RZ_BIT (ULL(0x1) << AMCR_CG1RZ_SHIFT) 1176 1177 /* 1178 * Definitions for virtual offset registers for architected activity monitor 1179 * event counters. 1180 * AMEVCNTVOFF01_EL2 intentionally left undefined, as it does not exist. 1181 */ 1182 #define AMEVCNTVOFF00_EL2 S3_4_C13_C8_0 1183 #define AMEVCNTVOFF02_EL2 S3_4_C13_C8_2 1184 #define AMEVCNTVOFF03_EL2 S3_4_C13_C8_3 1185 1186 /* 1187 * Definitions for virtual offset registers for auxiliary activity monitor event 1188 * counters. 1189 */ 1190 #define AMEVCNTVOFF10_EL2 S3_4_C13_C10_0 1191 #define AMEVCNTVOFF11_EL2 S3_4_C13_C10_1 1192 #define AMEVCNTVOFF12_EL2 S3_4_C13_C10_2 1193 #define AMEVCNTVOFF13_EL2 S3_4_C13_C10_3 1194 #define AMEVCNTVOFF14_EL2 S3_4_C13_C10_4 1195 #define AMEVCNTVOFF15_EL2 S3_4_C13_C10_5 1196 #define AMEVCNTVOFF16_EL2 S3_4_C13_C10_6 1197 #define AMEVCNTVOFF17_EL2 S3_4_C13_C10_7 1198 #define AMEVCNTVOFF18_EL2 S3_4_C13_C11_0 1199 #define AMEVCNTVOFF19_EL2 S3_4_C13_C11_1 1200 #define AMEVCNTVOFF1A_EL2 S3_4_C13_C11_2 1201 #define AMEVCNTVOFF1B_EL2 S3_4_C13_C11_3 1202 #define AMEVCNTVOFF1C_EL2 S3_4_C13_C11_4 1203 #define AMEVCNTVOFF1D_EL2 S3_4_C13_C11_5 1204 #define AMEVCNTVOFF1E_EL2 S3_4_C13_C11_6 1205 #define AMEVCNTVOFF1F_EL2 S3_4_C13_C11_7 1206 1207 /******************************************************************************* 1208 * Realm management extension register definitions 1209 ******************************************************************************/ 1210 #define GPCCR_EL3 S3_6_C2_C1_6 1211 #define GPTBR_EL3 S3_6_C2_C1_4 1212 1213 /******************************************************************************* 1214 * RAS system registers 1215 ******************************************************************************/ 1216 #define DISR_EL1 S3_0_C12_C1_1 1217 #define DISR_A_BIT U(31) 1218 1219 #define ERRIDR_EL1 S3_0_C5_C3_0 1220 #define ERRIDR_MASK U(0xffff) 1221 1222 #define ERRSELR_EL1 S3_0_C5_C3_1 1223 1224 /* System register access to Standard Error Record registers */ 1225 #define ERXFR_EL1 S3_0_C5_C4_0 1226 #define ERXCTLR_EL1 S3_0_C5_C4_1 1227 #define ERXSTATUS_EL1 S3_0_C5_C4_2 1228 #define ERXADDR_EL1 S3_0_C5_C4_3 1229 #define ERXPFGF_EL1 S3_0_C5_C4_4 1230 #define ERXPFGCTL_EL1 S3_0_C5_C4_5 1231 #define ERXPFGCDN_EL1 S3_0_C5_C4_6 1232 #define ERXMISC0_EL1 S3_0_C5_C5_0 1233 #define ERXMISC1_EL1 S3_0_C5_C5_1 1234 1235 #define ERXCTLR_ED_SHIFT U(0) 1236 #define ERXCTLR_ED_BIT (U(1) << ERXCTLR_ED_SHIFT) 1237 #define ERXCTLR_UE_BIT (U(1) << 4) 1238 1239 #define ERXPFGCTL_UC_BIT (U(1) << 1) 1240 #define ERXPFGCTL_UEU_BIT (U(1) << 2) 1241 #define ERXPFGCTL_CDEN_BIT (U(1) << 31) 1242 1243 /******************************************************************************* 1244 * Armv8.3 Pointer Authentication Registers 1245 ******************************************************************************/ 1246 #define APIAKeyLo_EL1 S3_0_C2_C1_0 1247 #define APIAKeyHi_EL1 S3_0_C2_C1_1 1248 #define APIBKeyLo_EL1 S3_0_C2_C1_2 1249 #define APIBKeyHi_EL1 S3_0_C2_C1_3 1250 #define APDAKeyLo_EL1 S3_0_C2_C2_0 1251 #define APDAKeyHi_EL1 S3_0_C2_C2_1 1252 #define APDBKeyLo_EL1 S3_0_C2_C2_2 1253 #define APDBKeyHi_EL1 S3_0_C2_C2_3 1254 #define APGAKeyLo_EL1 S3_0_C2_C3_0 1255 #define APGAKeyHi_EL1 S3_0_C2_C3_1 1256 1257 /******************************************************************************* 1258 * Armv8.4 Data Independent Timing Registers 1259 ******************************************************************************/ 1260 #define DIT S3_3_C4_C2_5 1261 #define DIT_BIT BIT(24) 1262 1263 /******************************************************************************* 1264 * Armv8.5 - new MSR encoding to directly access PSTATE.SSBS field 1265 ******************************************************************************/ 1266 #define SSBS S3_3_C4_C2_6 1267 1268 /******************************************************************************* 1269 * Armv8.5 - Memory Tagging Extension Registers 1270 ******************************************************************************/ 1271 #define TFSRE0_EL1 S3_0_C5_C6_1 1272 #define TFSR_EL1 S3_0_C5_C6_0 1273 #define RGSR_EL1 S3_0_C1_C0_5 1274 #define GCR_EL1 S3_0_C1_C0_6 1275 1276 /******************************************************************************* 1277 * FEAT_HCX - Extended Hypervisor Configuration Register 1278 ******************************************************************************/ 1279 #define HCRX_EL2 S3_4_C1_C2_2 1280 #define HCRX_EL2_FGTnXS_BIT (UL(1) << 4) 1281 #define HCRX_EL2_FnXS_BIT (UL(1) << 3) 1282 #define HCRX_EL2_EnASR_BIT (UL(1) << 2) 1283 #define HCRX_EL2_EnALS_BIT (UL(1) << 1) 1284 #define HCRX_EL2_EnAS0_BIT (UL(1) << 0) 1285 1286 /******************************************************************************* 1287 * Definitions for DynamicIQ Shared Unit registers 1288 ******************************************************************************/ 1289 #define CLUSTERPWRDN_EL1 S3_0_c15_c3_6 1290 1291 /* CLUSTERPWRDN_EL1 register definitions */ 1292 #define DSU_CLUSTER_PWR_OFF 0 1293 #define DSU_CLUSTER_PWR_ON 1 1294 #define DSU_CLUSTER_PWR_MASK U(1) 1295 1296 /******************************************************************************* 1297 * Definitions for CPU Power/Performance Management registers 1298 ******************************************************************************/ 1299 1300 #define CPUPPMCR_EL3 S3_6_C15_C2_0 1301 #define CPUPPMCR_EL3_MPMMPINCTL_SHIFT UINT64_C(0) 1302 #define CPUPPMCR_EL3_MPMMPINCTL_MASK UINT64_C(0x1) 1303 1304 #define CPUMPMMCR_EL3 S3_6_C15_C2_1 1305 #define CPUMPMMCR_EL3_MPMM_EN_SHIFT UINT64_C(0) 1306 #define CPUMPMMCR_EL3_MPMM_EN_MASK UINT64_C(0x1) 1307 1308 #endif /* ARCH_H */ 1309