1 /* 2 * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2020-2022, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef ARCH_H 9 #define ARCH_H 10 11 #include <lib/utils_def.h> 12 13 /******************************************************************************* 14 * MIDR bit definitions 15 ******************************************************************************/ 16 #define MIDR_IMPL_MASK U(0xff) 17 #define MIDR_IMPL_SHIFT U(0x18) 18 #define MIDR_VAR_SHIFT U(20) 19 #define MIDR_VAR_BITS U(4) 20 #define MIDR_VAR_MASK U(0xf) 21 #define MIDR_REV_SHIFT U(0) 22 #define MIDR_REV_BITS U(4) 23 #define MIDR_REV_MASK U(0xf) 24 #define MIDR_PN_MASK U(0xfff) 25 #define MIDR_PN_SHIFT U(0x4) 26 27 /* Extracts the CPU part number from MIDR for checking CPU match */ 28 #define EXTRACT_PARTNUM(x) ((x >> MIDR_PN_SHIFT) & MIDR_PN_MASK) 29 30 /******************************************************************************* 31 * MPIDR macros 32 ******************************************************************************/ 33 #define MPIDR_MT_MASK (ULL(1) << 24) 34 #define MPIDR_CPU_MASK MPIDR_AFFLVL_MASK 35 #define MPIDR_CLUSTER_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS) 36 #define MPIDR_AFFINITY_BITS U(8) 37 #define MPIDR_AFFLVL_MASK ULL(0xff) 38 #define MPIDR_AFF0_SHIFT U(0) 39 #define MPIDR_AFF1_SHIFT U(8) 40 #define MPIDR_AFF2_SHIFT U(16) 41 #define MPIDR_AFF3_SHIFT U(32) 42 #define MPIDR_AFF_SHIFT(_n) MPIDR_AFF##_n##_SHIFT 43 #define MPIDR_AFFINITY_MASK ULL(0xff00ffffff) 44 #define MPIDR_AFFLVL_SHIFT U(3) 45 #define MPIDR_AFFLVL0 ULL(0x0) 46 #define MPIDR_AFFLVL1 ULL(0x1) 47 #define MPIDR_AFFLVL2 ULL(0x2) 48 #define MPIDR_AFFLVL3 ULL(0x3) 49 #define MPIDR_AFFLVL(_n) MPIDR_AFFLVL##_n 50 #define MPIDR_AFFLVL0_VAL(mpidr) \ 51 (((mpidr) >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK) 52 #define MPIDR_AFFLVL1_VAL(mpidr) \ 53 (((mpidr) >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK) 54 #define MPIDR_AFFLVL2_VAL(mpidr) \ 55 (((mpidr) >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK) 56 #define MPIDR_AFFLVL3_VAL(mpidr) \ 57 (((mpidr) >> MPIDR_AFF3_SHIFT) & MPIDR_AFFLVL_MASK) 58 /* 59 * The MPIDR_MAX_AFFLVL count starts from 0. Take care to 60 * add one while using this macro to define array sizes. 61 * TODO: Support only the first 3 affinity levels for now. 62 */ 63 #define MPIDR_MAX_AFFLVL U(2) 64 65 #define MPID_MASK (MPIDR_MT_MASK | \ 66 (MPIDR_AFFLVL_MASK << MPIDR_AFF3_SHIFT) | \ 67 (MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT) | \ 68 (MPIDR_AFFLVL_MASK << MPIDR_AFF1_SHIFT) | \ 69 (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT)) 70 71 #define MPIDR_AFF_ID(mpid, n) \ 72 (((mpid) >> MPIDR_AFF_SHIFT(n)) & MPIDR_AFFLVL_MASK) 73 74 /* 75 * An invalid MPID. This value can be used by functions that return an MPID to 76 * indicate an error. 77 */ 78 #define INVALID_MPID U(0xFFFFFFFF) 79 80 /******************************************************************************* 81 * Definitions for Exception vector offsets 82 ******************************************************************************/ 83 #define CURRENT_EL_SP0 0x0 84 #define CURRENT_EL_SPX 0x200 85 #define LOWER_EL_AARCH64 0x400 86 #define LOWER_EL_AARCH32 0x600 87 88 #define SYNC_EXCEPTION 0x0 89 #define IRQ_EXCEPTION 0x80 90 #define FIQ_EXCEPTION 0x100 91 #define SERROR_EXCEPTION 0x180 92 93 /******************************************************************************* 94 * Definitions for CPU system register interface to GICv3 95 ******************************************************************************/ 96 #define ICC_IGRPEN1_EL1 S3_0_C12_C12_7 97 #define ICC_SGI1R S3_0_C12_C11_5 98 #define ICC_ASGI1R S3_0_C12_C11_6 99 #define ICC_SRE_EL1 S3_0_C12_C12_5 100 #define ICC_SRE_EL2 S3_4_C12_C9_5 101 #define ICC_SRE_EL3 S3_6_C12_C12_5 102 #define ICC_CTLR_EL1 S3_0_C12_C12_4 103 #define ICC_CTLR_EL3 S3_6_C12_C12_4 104 #define ICC_PMR_EL1 S3_0_C4_C6_0 105 #define ICC_RPR_EL1 S3_0_C12_C11_3 106 #define ICC_IGRPEN1_EL3 S3_6_c12_c12_7 107 #define ICC_IGRPEN0_EL1 S3_0_c12_c12_6 108 #define ICC_HPPIR0_EL1 S3_0_c12_c8_2 109 #define ICC_HPPIR1_EL1 S3_0_c12_c12_2 110 #define ICC_IAR0_EL1 S3_0_c12_c8_0 111 #define ICC_IAR1_EL1 S3_0_c12_c12_0 112 #define ICC_EOIR0_EL1 S3_0_c12_c8_1 113 #define ICC_EOIR1_EL1 S3_0_c12_c12_1 114 #define ICC_SGI0R_EL1 S3_0_c12_c11_7 115 116 /******************************************************************************* 117 * Definitions for EL2 system registers for save/restore routine 118 ******************************************************************************/ 119 #define CNTPOFF_EL2 S3_4_C14_C0_6 120 #define HDFGRTR2_EL2 S3_4_C3_C1_0 121 #define HDFGWTR2_EL2 S3_4_C3_C1_1 122 #define HFGRTR2_EL2 S3_4_C3_C1_2 123 #define HFGWTR2_EL2 S3_4_C3_C1_3 124 #define HDFGRTR_EL2 S3_4_C3_C1_4 125 #define HDFGWTR_EL2 S3_4_C3_C1_5 126 #define HAFGRTR_EL2 S3_4_C3_C1_6 127 #define HFGITR2_EL2 S3_4_C3_C1_7 128 #define HFGITR_EL2 S3_4_C1_C1_6 129 #define HFGRTR_EL2 S3_4_C1_C1_4 130 #define HFGWTR_EL2 S3_4_C1_C1_5 131 #define ICH_HCR_EL2 S3_4_C12_C11_0 132 #define ICH_VMCR_EL2 S3_4_C12_C11_7 133 #define MPAMVPM0_EL2 S3_4_C10_C6_0 134 #define MPAMVPM1_EL2 S3_4_C10_C6_1 135 #define MPAMVPM2_EL2 S3_4_C10_C6_2 136 #define MPAMVPM3_EL2 S3_4_C10_C6_3 137 #define MPAMVPM4_EL2 S3_4_C10_C6_4 138 #define MPAMVPM5_EL2 S3_4_C10_C6_5 139 #define MPAMVPM6_EL2 S3_4_C10_C6_6 140 #define MPAMVPM7_EL2 S3_4_C10_C6_7 141 #define MPAMVPMV_EL2 S3_4_C10_C4_1 142 #define VNCR_EL2 S3_4_C2_C2_0 143 #define PMSCR_EL2 S3_4_C9_C9_0 144 #define TFSR_EL2 S3_4_C5_C6_0 145 #define CONTEXTIDR_EL2 S3_4_C13_C0_1 146 #define TTBR1_EL2 S3_4_C2_C0_1 147 148 /******************************************************************************* 149 * Generic timer memory mapped registers & offsets 150 ******************************************************************************/ 151 #define CNTCR_OFF U(0x000) 152 #define CNTCV_OFF U(0x008) 153 #define CNTFID_OFF U(0x020) 154 155 #define CNTCR_EN (U(1) << 0) 156 #define CNTCR_HDBG (U(1) << 1) 157 #define CNTCR_FCREQ(x) ((x) << 8) 158 159 /******************************************************************************* 160 * System register bit definitions 161 ******************************************************************************/ 162 /* CLIDR definitions */ 163 #define LOUIS_SHIFT U(21) 164 #define LOC_SHIFT U(24) 165 #define CTYPE_SHIFT(n) U(3 * (n - 1)) 166 #define CLIDR_FIELD_WIDTH U(3) 167 168 /* CSSELR definitions */ 169 #define LEVEL_SHIFT U(1) 170 171 /* Data cache set/way op type defines */ 172 #define DCISW U(0x0) 173 #define DCCISW U(0x1) 174 #if ERRATA_A53_827319 175 #define DCCSW DCCISW 176 #else 177 #define DCCSW U(0x2) 178 #endif 179 180 #define ID_REG_FIELD_MASK ULL(0xf) 181 182 /* ID_AA64PFR0_EL1 definitions */ 183 #define ID_AA64PFR0_EL0_SHIFT U(0) 184 #define ID_AA64PFR0_EL1_SHIFT U(4) 185 #define ID_AA64PFR0_EL2_SHIFT U(8) 186 #define ID_AA64PFR0_EL3_SHIFT U(12) 187 188 #define ID_AA64PFR0_AMU_SHIFT U(44) 189 #define ID_AA64PFR0_AMU_MASK ULL(0xf) 190 #define ID_AA64PFR0_AMU_V1 ULL(0x1) 191 #define ID_AA64PFR0_AMU_V1P1 U(0x2) 192 193 #define ID_AA64PFR0_ELX_MASK ULL(0xf) 194 195 #define ID_AA64PFR0_GIC_SHIFT U(24) 196 #define ID_AA64PFR0_GIC_WIDTH U(4) 197 #define ID_AA64PFR0_GIC_MASK ULL(0xf) 198 199 #define ID_AA64PFR0_SVE_SHIFT U(32) 200 #define ID_AA64PFR0_SVE_MASK ULL(0xf) 201 #define ID_AA64PFR0_SVE_LENGTH U(4) 202 #define SVE_IMPLEMENTED ULL(0x1) 203 204 #define ID_AA64PFR0_SEL2_SHIFT U(36) 205 #define ID_AA64PFR0_SEL2_MASK ULL(0xf) 206 207 #define ID_AA64PFR0_MPAM_SHIFT U(40) 208 #define ID_AA64PFR0_MPAM_MASK ULL(0xf) 209 210 #define ID_AA64PFR0_DIT_SHIFT U(48) 211 #define ID_AA64PFR0_DIT_MASK ULL(0xf) 212 #define ID_AA64PFR0_DIT_LENGTH U(4) 213 #define DIT_IMPLEMENTED ULL(1) 214 215 #define ID_AA64PFR0_CSV2_SHIFT U(56) 216 #define ID_AA64PFR0_CSV2_MASK ULL(0xf) 217 #define ID_AA64PFR0_CSV2_LENGTH U(4) 218 #define CSV2_2_IMPLEMENTED ULL(0x2) 219 #define CSV2_3_IMPLEMENTED ULL(0x3) 220 221 #define ID_AA64PFR0_FEAT_RME_SHIFT U(52) 222 #define ID_AA64PFR0_FEAT_RME_MASK ULL(0xf) 223 #define ID_AA64PFR0_FEAT_RME_LENGTH U(4) 224 #define RME_NOT_IMPLEMENTED ULL(0) 225 226 #define ID_AA64PFR0_RAS_SHIFT U(28) 227 #define ID_AA64PFR0_RAS_MASK ULL(0xf) 228 #define ID_AA64PFR0_RAS_LENGTH U(4) 229 230 /* Exception level handling */ 231 #define EL_IMPL_NONE ULL(0) 232 #define EL_IMPL_A64ONLY ULL(1) 233 #define EL_IMPL_A64_A32 ULL(2) 234 235 /* ID_AA64DFR0_EL1.DebugVer definitions */ 236 #define ID_AA64DFR0_DEBUGVER_SHIFT U(0) 237 #define ID_AA64DFR0_DEBUGVER_MASK ULL(0xf) 238 #define DEBUGVER_V8P9_IMPLEMENTED ULL(0xb) 239 240 /* ID_AA64DFR0_EL1.TraceVer definitions */ 241 #define ID_AA64DFR0_TRACEVER_SHIFT U(4) 242 #define ID_AA64DFR0_TRACEVER_MASK ULL(0xf) 243 #define ID_AA64DFR0_TRACEVER_LENGTH U(4) 244 245 #define ID_AA64DFR0_TRACEFILT_SHIFT U(40) 246 #define ID_AA64DFR0_TRACEFILT_MASK U(0xf) 247 #define ID_AA64DFR0_TRACEFILT_LENGTH U(4) 248 #define TRACEFILT_IMPLEMENTED ULL(1) 249 250 #define ID_AA64DFR0_PMUVER_LENGTH U(4) 251 #define ID_AA64DFR0_PMUVER_SHIFT U(8) 252 #define ID_AA64DFR0_PMUVER_MASK U(0xf) 253 #define ID_AA64DFR0_PMUVER_PMUV3 U(1) 254 #define ID_AA64DFR0_PMUVER_PMUV3P8 U(8) 255 #define ID_AA64DFR0_PMUVER_IMP_DEF U(0xf) 256 257 /* ID_AA64DFR0_EL1.SEBEP definitions */ 258 #define ID_AA64DFR0_SEBEP_SHIFT U(24) 259 #define ID_AA64DFR0_SEBEP_MASK ULL(0xf) 260 #define SEBEP_IMPLEMENTED ULL(1) 261 262 /* ID_AA64DFR0_EL1.PMS definitions (for ARMv8.2+) */ 263 #define ID_AA64DFR0_PMS_SHIFT U(32) 264 #define ID_AA64DFR0_PMS_MASK ULL(0xf) 265 #define SPE_IMPLEMENTED ULL(0x1) 266 #define SPE_NOT_IMPLEMENTED ULL(0x0) 267 268 /* ID_AA64DFR0_EL1.TraceBuffer definitions */ 269 #define ID_AA64DFR0_TRACEBUFFER_SHIFT U(44) 270 #define ID_AA64DFR0_TRACEBUFFER_MASK ULL(0xf) 271 #define TRACEBUFFER_IMPLEMENTED ULL(1) 272 273 /* ID_AA64DFR0_EL1.MTPMU definitions (for ARMv8.6+) */ 274 #define ID_AA64DFR0_MTPMU_SHIFT U(48) 275 #define ID_AA64DFR0_MTPMU_MASK ULL(0xf) 276 #define MTPMU_IMPLEMENTED ULL(1) 277 #define MTPMU_NOT_IMPLEMENTED ULL(15) 278 279 /* ID_AA64DFR0_EL1.BRBE definitions */ 280 #define ID_AA64DFR0_BRBE_SHIFT U(52) 281 #define ID_AA64DFR0_BRBE_MASK ULL(0xf) 282 #define BRBE_IMPLEMENTED ULL(1) 283 284 /* ID_AA64DFR1_EL1 definitions */ 285 #define ID_AA64DFR1_EBEP_SHIFT U(48) 286 #define ID_AA64DFR1_EBEP_MASK ULL(0xf) 287 #define EBEP_IMPLEMENTED ULL(1) 288 289 /* ID_AA64ISAR0_EL1 definitions */ 290 #define ID_AA64ISAR0_RNDR_SHIFT U(60) 291 #define ID_AA64ISAR0_RNDR_MASK ULL(0xf) 292 293 /* ID_AA64ISAR1_EL1 definitions */ 294 #define ID_AA64ISAR1_EL1 S3_0_C0_C6_1 295 296 #define ID_AA64ISAR1_LS64_SHIFT U(60) 297 #define ID_AA64ISAR1_LS64_MASK ULL(0xf) 298 #define LS64_ACCDATA_IMPLEMENTED ULL(0x3) 299 #define LS64_V_IMPLEMENTED ULL(0x2) 300 #define LS64_IMPLEMENTED ULL(0x1) 301 #define LS64_NOT_IMPLEMENTED ULL(0x0) 302 303 #define ID_AA64ISAR1_SB_SHIFT U(36) 304 #define ID_AA64ISAR1_SB_MASK ULL(0xf) 305 #define SB_IMPLEMENTED ULL(0x1) 306 #define SB_NOT_IMPLEMENTED ULL(0x0) 307 308 #define ID_AA64ISAR1_GPI_SHIFT U(28) 309 #define ID_AA64ISAR1_GPI_MASK ULL(0xf) 310 #define ID_AA64ISAR1_GPA_SHIFT U(24) 311 #define ID_AA64ISAR1_GPA_MASK ULL(0xf) 312 313 #define ID_AA64ISAR1_API_SHIFT U(8) 314 #define ID_AA64ISAR1_API_MASK ULL(0xf) 315 #define ID_AA64ISAR1_APA_SHIFT U(4) 316 #define ID_AA64ISAR1_APA_MASK ULL(0xf) 317 318 /* ID_AA64ISAR2_EL1 definitions */ 319 #define ID_AA64ISAR2_EL1 S3_0_C0_C6_2 320 #define ID_AA64ISAR2_EL1_MOPS_SHIFT U(16) 321 #define ID_AA64ISAR2_EL1_MOPS_MASK ULL(0xf) 322 323 #define MOPS_IMPLEMENTED ULL(0x1) 324 325 #define ID_AA64ISAR2_GPA3_SHIFT U(8) 326 #define ID_AA64ISAR2_GPA3_MASK ULL(0xf) 327 328 #define ID_AA64ISAR2_APA3_SHIFT U(12) 329 #define ID_AA64ISAR2_APA3_MASK ULL(0xf) 330 331 #define ID_AA64ISAR2_SYSREG128_SHIFT U(32) 332 #define ID_AA64ISAR2_SYSREG128_MASK ULL(0xf) 333 334 /* ID_AA64MMFR0_EL1 definitions */ 335 #define ID_AA64MMFR0_EL1_PARANGE_SHIFT U(0) 336 #define ID_AA64MMFR0_EL1_PARANGE_MASK ULL(0xf) 337 338 #define PARANGE_0000 U(32) 339 #define PARANGE_0001 U(36) 340 #define PARANGE_0010 U(40) 341 #define PARANGE_0011 U(42) 342 #define PARANGE_0100 U(44) 343 #define PARANGE_0101 U(48) 344 #define PARANGE_0110 U(52) 345 #define PARANGE_0111 U(56) 346 347 #define ID_AA64MMFR0_EL1_ECV_SHIFT U(60) 348 #define ID_AA64MMFR0_EL1_ECV_MASK ULL(0xf) 349 #define ID_AA64MMFR0_EL1_ECV_SELF_SYNCH ULL(0x2) 350 #define ECV_IMPLEMENTED ULL(0x1) 351 352 #define ID_AA64MMFR0_EL1_FGT_SHIFT U(56) 353 #define ID_AA64MMFR0_EL1_FGT_MASK ULL(0xf) 354 #define FGT2_IMPLEMENTED ULL(0x2) 355 #define FGT_IMPLEMENTED ULL(0x1) 356 #define FGT_NOT_IMPLEMENTED ULL(0x0) 357 358 #define ID_AA64MMFR0_EL1_TGRAN4_SHIFT U(28) 359 #define ID_AA64MMFR0_EL1_TGRAN4_MASK ULL(0xf) 360 361 #define ID_AA64MMFR0_EL1_TGRAN64_SHIFT U(24) 362 #define ID_AA64MMFR0_EL1_TGRAN64_MASK ULL(0xf) 363 364 #define ID_AA64MMFR0_EL1_TGRAN16_SHIFT U(20) 365 #define ID_AA64MMFR0_EL1_TGRAN16_MASK ULL(0xf) 366 #define TGRAN16_IMPLEMENTED ULL(0x1) 367 368 /* ID_AA64MMFR1_EL1 definitions */ 369 #define ID_AA64MMFR1_EL1_TWED_SHIFT U(32) 370 #define ID_AA64MMFR1_EL1_TWED_MASK ULL(0xf) 371 #define TWED_IMPLEMENTED ULL(0x1) 372 373 #define ID_AA64MMFR1_EL1_PAN_SHIFT U(20) 374 #define ID_AA64MMFR1_EL1_PAN_MASK ULL(0xf) 375 #define PAN_IMPLEMENTED ULL(0x1) 376 #define PAN2_IMPLEMENTED ULL(0x2) 377 #define PAN3_IMPLEMENTED ULL(0x3) 378 379 #define ID_AA64MMFR1_EL1_VHE_SHIFT U(8) 380 #define ID_AA64MMFR1_EL1_VHE_MASK ULL(0xf) 381 382 #define ID_AA64MMFR1_EL1_HCX_SHIFT U(40) 383 #define ID_AA64MMFR1_EL1_HCX_MASK ULL(0xf) 384 #define HCX_IMPLEMENTED ULL(0x1) 385 386 /* ID_AA64MMFR2_EL1 definitions */ 387 #define ID_AA64MMFR2_EL1 S3_0_C0_C7_2 388 389 #define ID_AA64MMFR2_EL1_ST_SHIFT U(28) 390 #define ID_AA64MMFR2_EL1_ST_MASK ULL(0xf) 391 392 #define ID_AA64MMFR2_EL1_CCIDX_SHIFT U(20) 393 #define ID_AA64MMFR2_EL1_CCIDX_MASK ULL(0xf) 394 #define ID_AA64MMFR2_EL1_CCIDX_LENGTH U(4) 395 396 #define ID_AA64MMFR2_EL1_UAO_SHIFT U(4) 397 #define ID_AA64MMFR2_EL1_UAO_MASK ULL(0xf) 398 399 #define ID_AA64MMFR2_EL1_CNP_SHIFT U(0) 400 #define ID_AA64MMFR2_EL1_CNP_MASK ULL(0xf) 401 402 #define ID_AA64MMFR2_EL1_NV_SHIFT U(24) 403 #define ID_AA64MMFR2_EL1_NV_MASK ULL(0xf) 404 #define NV2_IMPLEMENTED ULL(0x2) 405 406 /* ID_AA64MMFR3_EL1 definitions */ 407 #define ID_AA64MMFR3_EL1 S3_0_C0_C7_3 408 409 #define ID_AA64MMFR3_EL1_D128_SHIFT U(32) 410 #define ID_AA64MMFR3_EL1_D128_MASK ULL(0xf) 411 #define D128_IMPLEMENTED ULL(0x1) 412 413 #define ID_AA64MMFR3_EL1_S2POE_SHIFT U(20) 414 #define ID_AA64MMFR3_EL1_S2POE_MASK ULL(0xf) 415 416 #define ID_AA64MMFR3_EL1_S1POE_SHIFT U(16) 417 #define ID_AA64MMFR3_EL1_S1POE_MASK ULL(0xf) 418 419 #define ID_AA64MMFR3_EL1_S2PIE_SHIFT U(12) 420 #define ID_AA64MMFR3_EL1_S2PIE_MASK ULL(0xf) 421 422 #define ID_AA64MMFR3_EL1_S1PIE_SHIFT U(8) 423 #define ID_AA64MMFR3_EL1_S1PIE_MASK ULL(0xf) 424 425 #define ID_AA64MMFR3_EL1_SCTLR2_SHIFT U(4) 426 #define ID_AA64MMFR3_EL1_SCTLR2_MASK ULL(0xf) 427 #define SCTLR2_IMPLEMENTED ULL(1) 428 429 #define ID_AA64MMFR3_EL1_TCRX_SHIFT U(0) 430 #define ID_AA64MMFR3_EL1_TCRX_MASK ULL(0xf) 431 432 /* ID_AA64PFR1_EL1 definitions */ 433 434 #define ID_AA64PFR1_EL1_BT_SHIFT U(0) 435 #define ID_AA64PFR1_EL1_BT_MASK ULL(0xf) 436 #define BTI_IMPLEMENTED ULL(1) /* The BTI mechanism is implemented */ 437 438 #define ID_AA64PFR1_EL1_SSBS_SHIFT U(4) 439 #define ID_AA64PFR1_EL1_SSBS_MASK ULL(0xf) 440 #define SSBS_NOT_IMPLEMENTED ULL(0) /* No architectural SSBS support */ 441 442 #define ID_AA64PFR1_EL1_MTE_SHIFT U(8) 443 #define ID_AA64PFR1_EL1_MTE_MASK ULL(0xf) 444 445 #define ID_AA64PFR1_EL1_RNDR_TRAP_SHIFT U(28) 446 #define ID_AA64PFR1_EL1_RNDR_TRAP_MASK U(0xf) 447 448 #define ID_AA64PFR1_EL1_NMI_SHIFT U(36) 449 #define ID_AA64PFR1_EL1_NMI_MASK ULL(0xf) 450 #define NMI_IMPLEMENTED ULL(1) 451 452 #define ID_AA64PFR1_EL1_GCS_SHIFT U(44) 453 #define ID_AA64PFR1_EL1_GCS_MASK ULL(0xf) 454 #define GCS_IMPLEMENTED ULL(1) 455 456 #define ID_AA64PFR1_EL1_THE_SHIFT U(48) 457 #define ID_AA64PFR1_EL1_THE_MASK ULL(0xf) 458 #define THE_IMPLEMENTED ULL(1) 459 460 #define RNG_TRAP_IMPLEMENTED ULL(0x1) 461 462 /* ID_AA64PFR2_EL1 definitions */ 463 #define ID_AA64PFR2_EL1 S3_0_C0_C4_2 464 465 #define ID_AA64PFR2_EL1_MTEPERM_SHIFT U(0) 466 #define ID_AA64PFR2_EL1_MTEPERM_MASK ULL(0xf) 467 468 #define ID_AA64PFR2_EL1_MTESTOREONLY_SHIFT U(4) 469 #define ID_AA64PFR2_EL1_MTESTOREONLY_MASK ULL(0xf) 470 471 #define ID_AA64PFR2_EL1_MTEFAR_SHIFT U(8) 472 #define ID_AA64PFR2_EL1_MTEFAR_MASK ULL(0xf) 473 474 #define ID_AA64PFR2_EL1_FPMR_SHIFT U(32) 475 #define ID_AA64PFR2_EL1_FPMR_MASK ULL(0xf) 476 477 #define FPMR_IMPLEMENTED ULL(0x1) 478 479 #define VDISR_EL2 S3_4_C12_C1_1 480 #define VSESR_EL2 S3_4_C5_C2_3 481 482 /* Memory Tagging Extension is not implemented */ 483 #define MTE_UNIMPLEMENTED U(0) 484 /* FEAT_MTE: MTE instructions accessible at EL0 are implemented */ 485 #define MTE_IMPLEMENTED_EL0 U(1) 486 /* FEAT_MTE2: Full MTE is implemented */ 487 #define MTE_IMPLEMENTED_ELX U(2) 488 /* 489 * FEAT_MTE3: MTE is implemented with support for 490 * asymmetric Tag Check Fault handling 491 */ 492 #define MTE_IMPLEMENTED_ASY U(3) 493 494 #define ID_AA64PFR1_MPAM_FRAC_SHIFT ULL(16) 495 #define ID_AA64PFR1_MPAM_FRAC_MASK ULL(0xf) 496 497 #define ID_AA64PFR1_EL1_SME_SHIFT U(24) 498 #define ID_AA64PFR1_EL1_SME_MASK ULL(0xf) 499 #define ID_AA64PFR1_EL1_SME_WIDTH U(4) 500 #define SME_IMPLEMENTED ULL(0x1) 501 #define SME2_IMPLEMENTED ULL(0x2) 502 #define SME_NOT_IMPLEMENTED ULL(0x0) 503 504 /* ID_PFR1_EL1 definitions */ 505 #define ID_PFR1_VIRTEXT_SHIFT U(12) 506 #define ID_PFR1_VIRTEXT_MASK U(0xf) 507 #define GET_VIRT_EXT(id) (((id) >> ID_PFR1_VIRTEXT_SHIFT) \ 508 & ID_PFR1_VIRTEXT_MASK) 509 510 /* SCTLR definitions */ 511 #define SCTLR_EL2_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ 512 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \ 513 (U(1) << 11) | (U(1) << 5) | (U(1) << 4)) 514 515 #define SCTLR_EL1_RES1 ((UL(1) << 29) | (UL(1) << 28) | (UL(1) << 23) | \ 516 (UL(1) << 22) | (UL(1) << 20) | (UL(1) << 11)) 517 518 #define SCTLR_AARCH32_EL1_RES1 \ 519 ((U(1) << 23) | (U(1) << 22) | (U(1) << 11) | \ 520 (U(1) << 4) | (U(1) << 3)) 521 522 #define SCTLR_EL3_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ 523 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \ 524 (U(1) << 11) | (U(1) << 5) | (U(1) << 4)) 525 526 #define SCTLR_M_BIT (ULL(1) << 0) 527 #define SCTLR_A_BIT (ULL(1) << 1) 528 #define SCTLR_C_BIT (ULL(1) << 2) 529 #define SCTLR_SA_BIT (ULL(1) << 3) 530 #define SCTLR_SA0_BIT (ULL(1) << 4) 531 #define SCTLR_CP15BEN_BIT (ULL(1) << 5) 532 #define SCTLR_nAA_BIT (ULL(1) << 6) 533 #define SCTLR_ITD_BIT (ULL(1) << 7) 534 #define SCTLR_SED_BIT (ULL(1) << 8) 535 #define SCTLR_UMA_BIT (ULL(1) << 9) 536 #define SCTLR_EnRCTX_BIT (ULL(1) << 10) 537 #define SCTLR_EOS_BIT (ULL(1) << 11) 538 #define SCTLR_I_BIT (ULL(1) << 12) 539 #define SCTLR_EnDB_BIT (ULL(1) << 13) 540 #define SCTLR_DZE_BIT (ULL(1) << 14) 541 #define SCTLR_UCT_BIT (ULL(1) << 15) 542 #define SCTLR_NTWI_BIT (ULL(1) << 16) 543 #define SCTLR_NTWE_BIT (ULL(1) << 18) 544 #define SCTLR_WXN_BIT (ULL(1) << 19) 545 #define SCTLR_TSCXT_BIT (ULL(1) << 20) 546 #define SCTLR_IESB_BIT (ULL(1) << 21) 547 #define SCTLR_EIS_BIT (ULL(1) << 22) 548 #define SCTLR_SPAN_BIT (ULL(1) << 23) 549 #define SCTLR_E0E_BIT (ULL(1) << 24) 550 #define SCTLR_EE_BIT (ULL(1) << 25) 551 #define SCTLR_UCI_BIT (ULL(1) << 26) 552 #define SCTLR_EnDA_BIT (ULL(1) << 27) 553 #define SCTLR_nTLSMD_BIT (ULL(1) << 28) 554 #define SCTLR_LSMAOE_BIT (ULL(1) << 29) 555 #define SCTLR_EnIB_BIT (ULL(1) << 30) 556 #define SCTLR_EnIA_BIT (ULL(1) << 31) 557 #define SCTLR_BT0_BIT (ULL(1) << 35) 558 #define SCTLR_BT1_BIT (ULL(1) << 36) 559 #define SCTLR_BT_BIT (ULL(1) << 36) 560 #define SCTLR_ITFSB_BIT (ULL(1) << 37) 561 #define SCTLR_TCF0_SHIFT U(38) 562 #define SCTLR_TCF0_MASK ULL(3) 563 #define SCTLR_ENTP2_BIT (ULL(1) << 60) 564 #define SCTLR_SPINTMASK_BIT (ULL(1) << 62) 565 566 /* Tag Check Faults in EL0 have no effect on the PE */ 567 #define SCTLR_TCF0_NO_EFFECT U(0) 568 /* Tag Check Faults in EL0 cause a synchronous exception */ 569 #define SCTLR_TCF0_SYNC U(1) 570 /* Tag Check Faults in EL0 are asynchronously accumulated */ 571 #define SCTLR_TCF0_ASYNC U(2) 572 /* 573 * Tag Check Faults in EL0 cause a synchronous exception on reads, 574 * and are asynchronously accumulated on writes 575 */ 576 #define SCTLR_TCF0_SYNCR_ASYNCW U(3) 577 578 #define SCTLR_TCF_SHIFT U(40) 579 #define SCTLR_TCF_MASK ULL(3) 580 581 /* Tag Check Faults in EL1 have no effect on the PE */ 582 #define SCTLR_TCF_NO_EFFECT U(0) 583 /* Tag Check Faults in EL1 cause a synchronous exception */ 584 #define SCTLR_TCF_SYNC U(1) 585 /* Tag Check Faults in EL1 are asynchronously accumulated */ 586 #define SCTLR_TCF_ASYNC U(2) 587 /* 588 * Tag Check Faults in EL1 cause a synchronous exception on reads, 589 * and are asynchronously accumulated on writes 590 */ 591 #define SCTLR_TCF_SYNCR_ASYNCW U(3) 592 593 #define SCTLR_ATA0_BIT (ULL(1) << 42) 594 #define SCTLR_ATA_BIT (ULL(1) << 43) 595 #define SCTLR_DSSBS_SHIFT U(44) 596 #define SCTLR_DSSBS_BIT (ULL(1) << SCTLR_DSSBS_SHIFT) 597 #define SCTLR_TWEDEn_BIT (ULL(1) << 45) 598 #define SCTLR_TWEDEL_SHIFT U(46) 599 #define SCTLR_TWEDEL_MASK ULL(0xf) 600 #define SCTLR_EnASR_BIT (ULL(1) << 54) 601 #define SCTLR_EnAS0_BIT (ULL(1) << 55) 602 #define SCTLR_EnALS_BIT (ULL(1) << 56) 603 #define SCTLR_EPAN_BIT (ULL(1) << 57) 604 #define SCTLR_RESET_VAL SCTLR_EL3_RES1 605 606 /* CPACR_EL1 definitions */ 607 #define CPACR_EL1_FPEN(x) ((x) << 20) 608 #define CPACR_EL1_FP_TRAP_EL0 UL(0x1) 609 #define CPACR_EL1_FP_TRAP_ALL UL(0x2) 610 #define CPACR_EL1_FP_TRAP_NONE UL(0x3) 611 #define CPACR_EL1_SMEN_SHIFT U(24) 612 #define CPACR_EL1_SMEN_MASK ULL(0x3) 613 614 /* SCR definitions */ 615 #define SCR_RES1_BITS ((U(1) << 4) | (U(1) << 5)) 616 #define SCR_NSE_SHIFT U(62) 617 #define SCR_FGTEN2_BIT (UL(1) << 59) 618 #define SCR_NSE_BIT (ULL(1) << SCR_NSE_SHIFT) 619 #define SCR_EnFPM_BIT (ULL(1) << 50) 620 #define SCR_GPF_BIT (UL(1) << 48) 621 #define SCR_D128En_BIT (UL(1) << 47) 622 #define SCR_TWEDEL_SHIFT U(30) 623 #define SCR_TWEDEL_MASK ULL(0xf) 624 #define SCR_PIEN_BIT (UL(1) << 45) 625 #define SCR_SCTLR2En_BIT (UL(1) << 44) 626 #define SCR_TCR2EN_BIT (UL(1) << 43) 627 #define SCR_RCWMASKEn_BIT (UL(1) << 42) 628 #define SCR_ENTP2_SHIFT U(41) 629 #define SCR_ENTP2_BIT (UL(1) << SCR_ENTP2_SHIFT) 630 #define SCR_TRNDR_BIT (UL(1) << 40) 631 #define SCR_GCSEn_BIT (UL(1) << 39) 632 #define SCR_HXEn_BIT (UL(1) << 38) 633 #define SCR_ADEn_BIT (UL(1) << 37) 634 #define SCR_EnAS0_BIT (UL(1) << 36) 635 #define SCR_AMVOFFEN_SHIFT U(35) 636 #define SCR_AMVOFFEN_BIT (UL(1) << SCR_AMVOFFEN_SHIFT) 637 #define SCR_TWEDEn_BIT (UL(1) << 29) 638 #define SCR_ECVEN_BIT (UL(1) << 28) 639 #define SCR_FGTEN_BIT (UL(1) << 27) 640 #define SCR_ATA_BIT (UL(1) << 26) 641 #define SCR_EnSCXT_BIT (UL(1) << 25) 642 #define SCR_FIEN_BIT (UL(1) << 21) 643 #define SCR_EEL2_BIT (UL(1) << 18) 644 #define SCR_API_BIT (UL(1) << 17) 645 #define SCR_APK_BIT (UL(1) << 16) 646 #define SCR_TERR_BIT (UL(1) << 15) 647 #define SCR_TWE_BIT (UL(1) << 13) 648 #define SCR_TWI_BIT (UL(1) << 12) 649 #define SCR_ST_BIT (UL(1) << 11) 650 #define SCR_RW_BIT (UL(1) << 10) 651 #define SCR_SIF_BIT (UL(1) << 9) 652 #define SCR_HCE_BIT (UL(1) << 8) 653 #define SCR_SMD_BIT (UL(1) << 7) 654 #define SCR_EA_BIT (UL(1) << 3) 655 #define SCR_FIQ_BIT (UL(1) << 2) 656 #define SCR_IRQ_BIT (UL(1) << 1) 657 #define SCR_NS_BIT (UL(1) << 0) 658 #define SCR_VALID_BIT_MASK U(0x24000002F8F) 659 #define SCR_RESET_VAL SCR_RES1_BITS 660 661 /* MDCR_EL3 definitions */ 662 #define MDCR_EBWE_BIT (ULL(1) << 43) 663 #define MDCR_E3BREC_BIT (ULL(1) << 38) 664 #define MDCR_E3BREW_BIT (ULL(1) << 37) 665 #define MDCR_EnPMSN_BIT (ULL(1) << 36) 666 #define MDCR_MPMX_BIT (ULL(1) << 35) 667 #define MDCR_MCCD_BIT (ULL(1) << 34) 668 #define MDCR_SBRBE_SHIFT U(32) 669 #define MDCR_SBRBE(x) ((x) << MDCR_SBRBE_SHIFT) 670 #define MDCR_SBRBE_ALL ULL(0x3) 671 #define MDCR_SBRBE_NS ULL(0x1) 672 #define MDCR_NSTB(x) ((x) << 24) 673 #define MDCR_NSTB_EL1 ULL(0x3) 674 #define MDCR_NSTB_EL3 ULL(0x2) 675 #define MDCR_NSTBE_BIT (ULL(1) << 26) 676 #define MDCR_MTPME_BIT (ULL(1) << 28) 677 #define MDCR_TDCC_BIT (ULL(1) << 27) 678 #define MDCR_SCCD_BIT (ULL(1) << 23) 679 #define MDCR_EPMAD_BIT (ULL(1) << 21) 680 #define MDCR_EDAD_BIT (ULL(1) << 20) 681 #define MDCR_TTRF_BIT (ULL(1) << 19) 682 #define MDCR_STE_BIT (ULL(1) << 18) 683 #define MDCR_SPME_BIT (ULL(1) << 17) 684 #define MDCR_SDD_BIT (ULL(1) << 16) 685 #define MDCR_SPD32(x) ((x) << 14) 686 #define MDCR_SPD32_LEGACY ULL(0x0) 687 #define MDCR_SPD32_DISABLE ULL(0x2) 688 #define MDCR_SPD32_ENABLE ULL(0x3) 689 #define MDCR_NSPB(x) ((x) << 12) 690 #define MDCR_NSPB_EL1 ULL(0x3) 691 #define MDCR_NSPB_EL3 ULL(0x2) 692 #define MDCR_NSPBE_BIT (ULL(1) << 11) 693 #define MDCR_TDOSA_BIT (ULL(1) << 10) 694 #define MDCR_TDA_BIT (ULL(1) << 9) 695 #define MDCR_TPM_BIT (ULL(1) << 6) 696 #define MDCR_EL3_RESET_VAL MDCR_MTPME_BIT 697 698 /* MDCR_EL2 definitions */ 699 #define MDCR_EL2_MTPME (U(1) << 28) 700 #define MDCR_EL2_HLP_BIT (U(1) << 26) 701 #define MDCR_EL2_E2TB(x) ((x) << 24) 702 #define MDCR_EL2_E2TB_EL1 U(0x3) 703 #define MDCR_EL2_HCCD_BIT (U(1) << 23) 704 #define MDCR_EL2_TTRF (U(1) << 19) 705 #define MDCR_EL2_HPMD_BIT (U(1) << 17) 706 #define MDCR_EL2_TPMS (U(1) << 14) 707 #define MDCR_EL2_E2PB(x) ((x) << 12) 708 #define MDCR_EL2_E2PB_EL1 U(0x3) 709 #define MDCR_EL2_TDRA_BIT (U(1) << 11) 710 #define MDCR_EL2_TDOSA_BIT (U(1) << 10) 711 #define MDCR_EL2_TDA_BIT (U(1) << 9) 712 #define MDCR_EL2_TDE_BIT (U(1) << 8) 713 #define MDCR_EL2_HPME_BIT (U(1) << 7) 714 #define MDCR_EL2_TPM_BIT (U(1) << 6) 715 #define MDCR_EL2_TPMCR_BIT (U(1) << 5) 716 #define MDCR_EL2_HPMN_MASK U(0x1f) 717 #define MDCR_EL2_RESET_VAL U(0x0) 718 719 /* HSTR_EL2 definitions */ 720 #define HSTR_EL2_RESET_VAL U(0x0) 721 #define HSTR_EL2_T_MASK U(0xff) 722 723 /* CNTHP_CTL_EL2 definitions */ 724 #define CNTHP_CTL_ENABLE_BIT (U(1) << 0) 725 #define CNTHP_CTL_RESET_VAL U(0x0) 726 727 /* VTTBR_EL2 definitions */ 728 #define VTTBR_RESET_VAL ULL(0x0) 729 #define VTTBR_VMID_MASK ULL(0xff) 730 #define VTTBR_VMID_SHIFT U(48) 731 #define VTTBR_BADDR_MASK ULL(0xffffffffffff) 732 #define VTTBR_BADDR_SHIFT U(0) 733 734 /* HCR definitions */ 735 #define HCR_RESET_VAL ULL(0x0) 736 #define HCR_AMVOFFEN_SHIFT U(51) 737 #define HCR_AMVOFFEN_BIT (ULL(1) << HCR_AMVOFFEN_SHIFT) 738 #define HCR_TEA_BIT (ULL(1) << 47) 739 #define HCR_API_BIT (ULL(1) << 41) 740 #define HCR_APK_BIT (ULL(1) << 40) 741 #define HCR_E2H_BIT (ULL(1) << 34) 742 #define HCR_HCD_BIT (ULL(1) << 29) 743 #define HCR_TGE_BIT (ULL(1) << 27) 744 #define HCR_RW_SHIFT U(31) 745 #define HCR_RW_BIT (ULL(1) << HCR_RW_SHIFT) 746 #define HCR_TWE_BIT (ULL(1) << 14) 747 #define HCR_TWI_BIT (ULL(1) << 13) 748 #define HCR_AMO_BIT (ULL(1) << 5) 749 #define HCR_IMO_BIT (ULL(1) << 4) 750 #define HCR_FMO_BIT (ULL(1) << 3) 751 752 /* ISR definitions */ 753 #define ISR_A_SHIFT U(8) 754 #define ISR_I_SHIFT U(7) 755 #define ISR_F_SHIFT U(6) 756 757 /* CNTHCTL_EL2 definitions */ 758 #define CNTHCTL_RESET_VAL U(0x0) 759 #define EVNTEN_BIT (U(1) << 2) 760 #define EL1PCEN_BIT (U(1) << 1) 761 #define EL1PCTEN_BIT (U(1) << 0) 762 763 /* CNTKCTL_EL1 definitions */ 764 #define EL0PTEN_BIT (U(1) << 9) 765 #define EL0VTEN_BIT (U(1) << 8) 766 #define EL0PCTEN_BIT (U(1) << 0) 767 #define EL0VCTEN_BIT (U(1) << 1) 768 #define EVNTEN_BIT (U(1) << 2) 769 #define EVNTDIR_BIT (U(1) << 3) 770 #define EVNTI_SHIFT U(4) 771 #define EVNTI_MASK U(0xf) 772 773 /* CPTR_EL3 definitions */ 774 #define TCPAC_BIT (U(1) << 31) 775 #define TAM_SHIFT U(30) 776 #define TAM_BIT (U(1) << TAM_SHIFT) 777 #define TTA_BIT (U(1) << 20) 778 #define ESM_BIT (U(1) << 12) 779 #define TFP_BIT (U(1) << 10) 780 #define CPTR_EZ_BIT (U(1) << 8) 781 #define CPTR_EL3_RESET_VAL ((TCPAC_BIT | TAM_BIT | TTA_BIT | TFP_BIT) & \ 782 ~(CPTR_EZ_BIT | ESM_BIT)) 783 784 /* CPTR_EL2 definitions */ 785 #define CPTR_EL2_RES1 ((U(1) << 13) | (U(1) << 12) | (U(0x3ff))) 786 #define CPTR_EL2_TCPAC_BIT (U(1) << 31) 787 #define CPTR_EL2_TAM_SHIFT U(30) 788 #define CPTR_EL2_TAM_BIT (U(1) << CPTR_EL2_TAM_SHIFT) 789 #define CPTR_EL2_SMEN_MASK ULL(0x3) 790 #define CPTR_EL2_SMEN_SHIFT U(24) 791 #define CPTR_EL2_TTA_BIT (U(1) << 20) 792 #define CPTR_EL2_TSM_BIT (U(1) << 12) 793 #define CPTR_EL2_TFP_BIT (U(1) << 10) 794 #define CPTR_EL2_TZ_BIT (U(1) << 8) 795 #define CPTR_EL2_RESET_VAL CPTR_EL2_RES1 796 797 /* VTCR_EL2 definitions */ 798 #define VTCR_RESET_VAL U(0x0) 799 #define VTCR_EL2_MSA (U(1) << 31) 800 801 /* CPSR/SPSR definitions */ 802 #define DAIF_FIQ_BIT (U(1) << 0) 803 #define DAIF_IRQ_BIT (U(1) << 1) 804 #define DAIF_ABT_BIT (U(1) << 2) 805 #define DAIF_DBG_BIT (U(1) << 3) 806 #define SPSR_V_BIT (U(1) << 28) 807 #define SPSR_C_BIT (U(1) << 29) 808 #define SPSR_Z_BIT (U(1) << 30) 809 #define SPSR_N_BIT (U(1) << 31) 810 #define SPSR_DAIF_SHIFT U(6) 811 #define SPSR_DAIF_MASK U(0xf) 812 813 #define SPSR_AIF_SHIFT U(6) 814 #define SPSR_AIF_MASK U(0x7) 815 816 #define SPSR_E_SHIFT U(9) 817 #define SPSR_E_MASK U(0x1) 818 #define SPSR_E_LITTLE U(0x0) 819 #define SPSR_E_BIG U(0x1) 820 821 #define SPSR_T_SHIFT U(5) 822 #define SPSR_T_MASK U(0x1) 823 #define SPSR_T_ARM U(0x0) 824 #define SPSR_T_THUMB U(0x1) 825 826 #define SPSR_M_SHIFT U(4) 827 #define SPSR_M_MASK U(0x1) 828 #define SPSR_M_AARCH64 U(0x0) 829 #define SPSR_M_AARCH32 U(0x1) 830 #define SPSR_M_EL1H U(0x5) 831 #define SPSR_M_EL2H U(0x9) 832 833 #define SPSR_EL_SHIFT U(2) 834 #define SPSR_EL_WIDTH U(2) 835 836 #define SPSR_BTYPE_SHIFT_AARCH64 U(10) 837 #define SPSR_BTYPE_MASK_AARCH64 U(0x3) 838 #define SPSR_SSBS_SHIFT_AARCH64 U(12) 839 #define SPSR_SSBS_BIT_AARCH64 (ULL(1) << SPSR_SSBS_SHIFT_AARCH64) 840 #define SPSR_SSBS_SHIFT_AARCH32 U(23) 841 #define SPSR_SSBS_BIT_AARCH32 (ULL(1) << SPSR_SSBS_SHIFT_AARCH32) 842 #define SPSR_ALLINT_BIT_AARCH64 BIT_64(13) 843 #define SPSR_IL_BIT BIT_64(20) 844 #define SPSR_SS_BIT BIT_64(21) 845 #define SPSR_PAN_BIT BIT_64(22) 846 #define SPSR_UAO_BIT_AARCH64 BIT_64(23) 847 #define SPSR_DIT_BIT BIT(24) 848 #define SPSR_TCO_BIT_AARCH64 BIT_64(25) 849 #define SPSR_PM_BIT_AARCH64 BIT_64(32) 850 #define SPSR_PPEND_BIT BIT(33) 851 #define SPSR_EXLOCK_BIT_AARCH64 BIT_64(34) 852 #define SPSR_NZCV (SPSR_V_BIT | SPSR_C_BIT | SPSR_Z_BIT | SPSR_N_BIT) 853 854 #define DISABLE_ALL_EXCEPTIONS \ 855 (DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT | DAIF_DBG_BIT) 856 #define DISABLE_INTERRUPTS (DAIF_FIQ_BIT | DAIF_IRQ_BIT) 857 858 /* 859 * RMR_EL3 definitions 860 */ 861 #define RMR_EL3_RR_BIT (U(1) << 1) 862 #define RMR_EL3_AA64_BIT (U(1) << 0) 863 864 /* 865 * HI-VECTOR address for AArch32 state 866 */ 867 #define HI_VECTOR_BASE U(0xFFFF0000) 868 869 /* 870 * TCR definitions 871 */ 872 #define TCR_EL3_RES1 ((ULL(1) << 31) | (ULL(1) << 23)) 873 #define TCR_EL2_RES1 ((ULL(1) << 31) | (ULL(1) << 23)) 874 #define TCR_EL1_IPS_SHIFT U(32) 875 #define TCR_EL2_PS_SHIFT U(16) 876 #define TCR_EL3_PS_SHIFT U(16) 877 878 #define TCR_TxSZ_MIN ULL(16) 879 #define TCR_TxSZ_MAX ULL(39) 880 #define TCR_TxSZ_MAX_TTST ULL(48) 881 882 #define TCR_T0SZ_SHIFT U(0) 883 #define TCR_T1SZ_SHIFT U(16) 884 885 /* (internal) physical address size bits in EL3/EL1 */ 886 #define TCR_PS_BITS_4GB ULL(0x0) 887 #define TCR_PS_BITS_64GB ULL(0x1) 888 #define TCR_PS_BITS_1TB ULL(0x2) 889 #define TCR_PS_BITS_4TB ULL(0x3) 890 #define TCR_PS_BITS_16TB ULL(0x4) 891 #define TCR_PS_BITS_256TB ULL(0x5) 892 893 #define ADDR_MASK_48_TO_63 ULL(0xFFFF000000000000) 894 #define ADDR_MASK_44_TO_47 ULL(0x0000F00000000000) 895 #define ADDR_MASK_42_TO_43 ULL(0x00000C0000000000) 896 #define ADDR_MASK_40_TO_41 ULL(0x0000030000000000) 897 #define ADDR_MASK_36_TO_39 ULL(0x000000F000000000) 898 #define ADDR_MASK_32_TO_35 ULL(0x0000000F00000000) 899 900 #define TCR_RGN_INNER_NC (ULL(0x0) << 8) 901 #define TCR_RGN_INNER_WBA (ULL(0x1) << 8) 902 #define TCR_RGN_INNER_WT (ULL(0x2) << 8) 903 #define TCR_RGN_INNER_WBNA (ULL(0x3) << 8) 904 905 #define TCR_RGN_OUTER_NC (ULL(0x0) << 10) 906 #define TCR_RGN_OUTER_WBA (ULL(0x1) << 10) 907 #define TCR_RGN_OUTER_WT (ULL(0x2) << 10) 908 #define TCR_RGN_OUTER_WBNA (ULL(0x3) << 10) 909 910 #define TCR_SH_NON_SHAREABLE (ULL(0x0) << 12) 911 #define TCR_SH_OUTER_SHAREABLE (ULL(0x2) << 12) 912 #define TCR_SH_INNER_SHAREABLE (ULL(0x3) << 12) 913 914 #define TCR_RGN1_INNER_NC (ULL(0x0) << 24) 915 #define TCR_RGN1_INNER_WBA (ULL(0x1) << 24) 916 #define TCR_RGN1_INNER_WT (ULL(0x2) << 24) 917 #define TCR_RGN1_INNER_WBNA (ULL(0x3) << 24) 918 919 #define TCR_RGN1_OUTER_NC (ULL(0x0) << 26) 920 #define TCR_RGN1_OUTER_WBA (ULL(0x1) << 26) 921 #define TCR_RGN1_OUTER_WT (ULL(0x2) << 26) 922 #define TCR_RGN1_OUTER_WBNA (ULL(0x3) << 26) 923 924 #define TCR_SH1_NON_SHAREABLE (ULL(0x0) << 28) 925 #define TCR_SH1_OUTER_SHAREABLE (ULL(0x2) << 28) 926 #define TCR_SH1_INNER_SHAREABLE (ULL(0x3) << 28) 927 928 #define TCR_TG0_SHIFT U(14) 929 #define TCR_TG0_MASK ULL(3) 930 #define TCR_TG0_4K (ULL(0) << TCR_TG0_SHIFT) 931 #define TCR_TG0_64K (ULL(1) << TCR_TG0_SHIFT) 932 #define TCR_TG0_16K (ULL(2) << TCR_TG0_SHIFT) 933 934 #define TCR_TG1_SHIFT U(30) 935 #define TCR_TG1_MASK ULL(3) 936 #define TCR_TG1_16K (ULL(1) << TCR_TG1_SHIFT) 937 #define TCR_TG1_4K (ULL(2) << TCR_TG1_SHIFT) 938 #define TCR_TG1_64K (ULL(3) << TCR_TG1_SHIFT) 939 940 #define TCR_EPD0_BIT (ULL(1) << 7) 941 #define TCR_EPD1_BIT (ULL(1) << 23) 942 943 #define MODE_SP_SHIFT U(0x0) 944 #define MODE_SP_MASK U(0x1) 945 #define MODE_SP_EL0 U(0x0) 946 #define MODE_SP_ELX U(0x1) 947 948 #define MODE_RW_SHIFT U(0x4) 949 #define MODE_RW_MASK U(0x1) 950 #define MODE_RW_64 U(0x0) 951 #define MODE_RW_32 U(0x1) 952 953 #define MODE_EL_SHIFT U(0x2) 954 #define MODE_EL_MASK U(0x3) 955 #define MODE_EL_WIDTH U(0x2) 956 #define MODE_EL3 U(0x3) 957 #define MODE_EL2 U(0x2) 958 #define MODE_EL1 U(0x1) 959 #define MODE_EL0 U(0x0) 960 961 #define MODE32_SHIFT U(0) 962 #define MODE32_MASK U(0xf) 963 #define MODE32_usr U(0x0) 964 #define MODE32_fiq U(0x1) 965 #define MODE32_irq U(0x2) 966 #define MODE32_svc U(0x3) 967 #define MODE32_mon U(0x6) 968 #define MODE32_abt U(0x7) 969 #define MODE32_hyp U(0xa) 970 #define MODE32_und U(0xb) 971 #define MODE32_sys U(0xf) 972 973 #define GET_RW(mode) (((mode) >> MODE_RW_SHIFT) & MODE_RW_MASK) 974 #define GET_EL(mode) (((mode) >> MODE_EL_SHIFT) & MODE_EL_MASK) 975 #define GET_SP(mode) (((mode) >> MODE_SP_SHIFT) & MODE_SP_MASK) 976 #define GET_M32(mode) (((mode) >> MODE32_SHIFT) & MODE32_MASK) 977 978 #define SPSR_64(el, sp, daif) \ 979 (((MODE_RW_64 << MODE_RW_SHIFT) | \ 980 (((el) & MODE_EL_MASK) << MODE_EL_SHIFT) | \ 981 (((sp) & MODE_SP_MASK) << MODE_SP_SHIFT) | \ 982 (((daif) & SPSR_DAIF_MASK) << SPSR_DAIF_SHIFT)) & \ 983 (~(SPSR_SSBS_BIT_AARCH64))) 984 985 #define SPSR_MODE32(mode, isa, endian, aif) \ 986 (((MODE_RW_32 << MODE_RW_SHIFT) | \ 987 (((mode) & MODE32_MASK) << MODE32_SHIFT) | \ 988 (((isa) & SPSR_T_MASK) << SPSR_T_SHIFT) | \ 989 (((endian) & SPSR_E_MASK) << SPSR_E_SHIFT) | \ 990 (((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT)) & \ 991 (~(SPSR_SSBS_BIT_AARCH32))) 992 993 /* 994 * TTBR Definitions 995 */ 996 #define TTBR_CNP_BIT ULL(0x1) 997 998 /* 999 * CTR_EL0 definitions 1000 */ 1001 #define CTR_CWG_SHIFT U(24) 1002 #define CTR_CWG_MASK U(0xf) 1003 #define CTR_ERG_SHIFT U(20) 1004 #define CTR_ERG_MASK U(0xf) 1005 #define CTR_DMINLINE_SHIFT U(16) 1006 #define CTR_DMINLINE_MASK U(0xf) 1007 #define CTR_L1IP_SHIFT U(14) 1008 #define CTR_L1IP_MASK U(0x3) 1009 #define CTR_IMINLINE_SHIFT U(0) 1010 #define CTR_IMINLINE_MASK U(0xf) 1011 1012 #define MAX_CACHE_LINE_SIZE U(0x800) /* 2KB */ 1013 1014 /* Physical timer control register bit fields shifts and masks */ 1015 #define CNTP_CTL_ENABLE_SHIFT U(0) 1016 #define CNTP_CTL_IMASK_SHIFT U(1) 1017 #define CNTP_CTL_ISTATUS_SHIFT U(2) 1018 1019 #define CNTP_CTL_ENABLE_MASK U(1) 1020 #define CNTP_CTL_IMASK_MASK U(1) 1021 #define CNTP_CTL_ISTATUS_MASK U(1) 1022 1023 /* Physical timer control macros */ 1024 #define CNTP_CTL_ENABLE_BIT (U(1) << CNTP_CTL_ENABLE_SHIFT) 1025 #define CNTP_CTL_IMASK_BIT (U(1) << CNTP_CTL_IMASK_SHIFT) 1026 1027 /* Exception Syndrome register bits and bobs */ 1028 #define ESR_EC_SHIFT U(26) 1029 #define ESR_EC_MASK U(0x3f) 1030 #define ESR_EC_LENGTH U(6) 1031 #define ESR_ISS_SHIFT U(0) 1032 #define ESR_ISS_LENGTH U(25) 1033 #define ESR_IL_BIT (U(1) << 25) 1034 #define EC_UNKNOWN U(0x0) 1035 #define EC_WFE_WFI U(0x1) 1036 #define EC_AARCH32_CP15_MRC_MCR U(0x3) 1037 #define EC_AARCH32_CP15_MRRC_MCRR U(0x4) 1038 #define EC_AARCH32_CP14_MRC_MCR U(0x5) 1039 #define EC_AARCH32_CP14_LDC_STC U(0x6) 1040 #define EC_FP_SIMD U(0x7) 1041 #define EC_AARCH32_CP10_MRC U(0x8) 1042 #define EC_AARCH32_CP14_MRRC_MCRR U(0xc) 1043 #define EC_ILLEGAL U(0xe) 1044 #define EC_AARCH32_SVC U(0x11) 1045 #define EC_AARCH32_HVC U(0x12) 1046 #define EC_AARCH32_SMC U(0x13) 1047 #define EC_AARCH64_SVC U(0x15) 1048 #define EC_AARCH64_HVC U(0x16) 1049 #define EC_AARCH64_SMC U(0x17) 1050 #define EC_AARCH64_SYS U(0x18) 1051 #define EC_IMP_DEF_EL3 U(0x1f) 1052 #define EC_IABORT_LOWER_EL U(0x20) 1053 #define EC_IABORT_CUR_EL U(0x21) 1054 #define EC_PC_ALIGN U(0x22) 1055 #define EC_DABORT_LOWER_EL U(0x24) 1056 #define EC_DABORT_CUR_EL U(0x25) 1057 #define EC_SP_ALIGN U(0x26) 1058 #define EC_AARCH32_FP U(0x28) 1059 #define EC_AARCH64_FP U(0x2c) 1060 #define EC_SERROR U(0x2f) 1061 #define EC_BRK U(0x3c) 1062 1063 /* 1064 * External Abort bit in Instruction and Data Aborts synchronous exception 1065 * syndromes. 1066 */ 1067 #define ESR_ISS_EABORT_EA_BIT U(9) 1068 1069 #define EC_BITS(x) (((x) >> ESR_EC_SHIFT) & ESR_EC_MASK) 1070 1071 /* Reset bit inside the Reset management register for EL3 (RMR_EL3) */ 1072 #define RMR_RESET_REQUEST_SHIFT U(0x1) 1073 #define RMR_WARM_RESET_CPU (U(1) << RMR_RESET_REQUEST_SHIFT) 1074 1075 /******************************************************************************* 1076 * Definitions of register offsets, fields and macros for CPU system 1077 * instructions. 1078 ******************************************************************************/ 1079 1080 #define TLBI_ADDR_SHIFT U(12) 1081 #define TLBI_ADDR_MASK ULL(0x00000FFFFFFFFFFF) 1082 #define TLBI_ADDR(x) (((x) >> TLBI_ADDR_SHIFT) & TLBI_ADDR_MASK) 1083 1084 /******************************************************************************* 1085 * Definitions of register offsets and fields in the CNTCTLBase Frame of the 1086 * system level implementation of the Generic Timer. 1087 ******************************************************************************/ 1088 #define CNTCTLBASE_CNTFRQ U(0x0) 1089 #define CNTNSAR U(0x4) 1090 #define CNTNSAR_NS_SHIFT(x) (x) 1091 1092 #define CNTACR_BASE(x) (U(0x40) + ((x) << 2)) 1093 #define CNTACR_RPCT_SHIFT U(0x0) 1094 #define CNTACR_RVCT_SHIFT U(0x1) 1095 #define CNTACR_RFRQ_SHIFT U(0x2) 1096 #define CNTACR_RVOFF_SHIFT U(0x3) 1097 #define CNTACR_RWVT_SHIFT U(0x4) 1098 #define CNTACR_RWPT_SHIFT U(0x5) 1099 1100 /******************************************************************************* 1101 * Definitions of register offsets and fields in the CNTBaseN Frame of the 1102 * system level implementation of the Generic Timer. 1103 ******************************************************************************/ 1104 /* Physical Count register. */ 1105 #define CNTPCT_LO U(0x0) 1106 /* Counter Frequency register. */ 1107 #define CNTBASEN_CNTFRQ U(0x10) 1108 /* Physical Timer CompareValue register. */ 1109 #define CNTP_CVAL_LO U(0x20) 1110 /* Physical Timer Control register. */ 1111 #define CNTP_CTL U(0x2c) 1112 1113 /* PMCR_EL0 definitions */ 1114 #define PMCR_EL0_RESET_VAL U(0x0) 1115 #define PMCR_EL0_N_SHIFT U(11) 1116 #define PMCR_EL0_N_MASK U(0x1f) 1117 #define PMCR_EL0_N_BITS (PMCR_EL0_N_MASK << PMCR_EL0_N_SHIFT) 1118 #define PMCR_EL0_LP_BIT (U(1) << 7) 1119 #define PMCR_EL0_LC_BIT (U(1) << 6) 1120 #define PMCR_EL0_DP_BIT (U(1) << 5) 1121 #define PMCR_EL0_X_BIT (U(1) << 4) 1122 #define PMCR_EL0_D_BIT (U(1) << 3) 1123 #define PMCR_EL0_C_BIT (U(1) << 2) 1124 #define PMCR_EL0_P_BIT (U(1) << 1) 1125 #define PMCR_EL0_E_BIT (U(1) << 0) 1126 1127 /******************************************************************************* 1128 * Definitions for system register interface to SVE 1129 ******************************************************************************/ 1130 #define ZCR_EL3 S3_6_C1_C2_0 1131 #define ZCR_EL2 S3_4_C1_C2_0 1132 1133 /* ZCR_EL3 definitions */ 1134 #define ZCR_EL3_LEN_MASK U(0xf) 1135 1136 /* ZCR_EL2 definitions */ 1137 #define ZCR_EL2_LEN_MASK U(0xf) 1138 1139 /******************************************************************************* 1140 * Definitions for system register interface to SME as needed in EL3 1141 ******************************************************************************/ 1142 #define ID_AA64SMFR0_EL1 S3_0_C0_C4_5 1143 #define SMCR_EL3 S3_6_C1_C2_6 1144 #define SVCR S3_3_C4_C2_2 1145 1146 /* ID_AA64SMFR0_EL1 definitions */ 1147 #define ID_AA64SMFR0_EL1_SME_FA64_SHIFT U(63) 1148 #define ID_AA64SMFR0_EL1_SME_FA64_MASK U(0x1) 1149 #define SME_FA64_IMPLEMENTED U(0x1) 1150 #define ID_AA64SMFR0_EL1_SME_VER_SHIFT U(55) 1151 #define ID_AA64SMFR0_EL1_SME_VER_MASK ULL(0xf) 1152 #define SME_INST_IMPLEMENTED ULL(0x0) 1153 #define SME2_INST_IMPLEMENTED ULL(0x1) 1154 1155 /* SMCR_ELx definitions */ 1156 #define SMCR_ELX_LEN_SHIFT U(0) 1157 #define SMCR_ELX_LEN_MAX U(0x1ff) 1158 #define SMCR_ELX_FA64_BIT (U(1) << 31) 1159 #define SMCR_ELX_EZT0_BIT (U(1) << 30) 1160 1161 /******************************************************************************* 1162 * Definitions of MAIR encodings for device and normal memory 1163 ******************************************************************************/ 1164 /* 1165 * MAIR encodings for device memory attributes. 1166 */ 1167 #define MAIR_DEV_nGnRnE ULL(0x0) 1168 #define MAIR_DEV_nGnRE ULL(0x4) 1169 #define MAIR_DEV_nGRE ULL(0x8) 1170 #define MAIR_DEV_GRE ULL(0xc) 1171 1172 /* 1173 * MAIR encodings for normal memory attributes. 1174 * 1175 * Cache Policy 1176 * WT: Write Through 1177 * WB: Write Back 1178 * NC: Non-Cacheable 1179 * 1180 * Transient Hint 1181 * NTR: Non-Transient 1182 * TR: Transient 1183 * 1184 * Allocation Policy 1185 * RA: Read Allocate 1186 * WA: Write Allocate 1187 * RWA: Read and Write Allocate 1188 * NA: No Allocation 1189 */ 1190 #define MAIR_NORM_WT_TR_WA ULL(0x1) 1191 #define MAIR_NORM_WT_TR_RA ULL(0x2) 1192 #define MAIR_NORM_WT_TR_RWA ULL(0x3) 1193 #define MAIR_NORM_NC ULL(0x4) 1194 #define MAIR_NORM_WB_TR_WA ULL(0x5) 1195 #define MAIR_NORM_WB_TR_RA ULL(0x6) 1196 #define MAIR_NORM_WB_TR_RWA ULL(0x7) 1197 #define MAIR_NORM_WT_NTR_NA ULL(0x8) 1198 #define MAIR_NORM_WT_NTR_WA ULL(0x9) 1199 #define MAIR_NORM_WT_NTR_RA ULL(0xa) 1200 #define MAIR_NORM_WT_NTR_RWA ULL(0xb) 1201 #define MAIR_NORM_WB_NTR_NA ULL(0xc) 1202 #define MAIR_NORM_WB_NTR_WA ULL(0xd) 1203 #define MAIR_NORM_WB_NTR_RA ULL(0xe) 1204 #define MAIR_NORM_WB_NTR_RWA ULL(0xf) 1205 1206 #define MAIR_NORM_OUTER_SHIFT U(4) 1207 1208 #define MAKE_MAIR_NORMAL_MEMORY(inner, outer) \ 1209 ((inner) | ((outer) << MAIR_NORM_OUTER_SHIFT)) 1210 1211 /* PAR_EL1 fields */ 1212 #define PAR_F_SHIFT U(0) 1213 #define PAR_F_MASK ULL(0x1) 1214 1215 #define PAR_D128_ADDR_MASK GENMASK(55, 12) /* 44-bits-wide page address */ 1216 #define PAR_ADDR_MASK GENMASK(51, 12) /* 40-bits-wide page address */ 1217 1218 /******************************************************************************* 1219 * Definitions for system register interface to SPE 1220 ******************************************************************************/ 1221 #define PMBLIMITR_EL1 S3_0_C9_C10_0 1222 1223 /******************************************************************************* 1224 * Definitions for system register interface, shifts and masks for MPAM 1225 ******************************************************************************/ 1226 #define MPAMIDR_EL1 S3_0_C10_C4_4 1227 #define MPAM2_EL2 S3_4_C10_C5_0 1228 #define MPAMHCR_EL2 S3_4_C10_C4_0 1229 #define MPAM3_EL3 S3_6_C10_C5_0 1230 1231 #define MPAMIDR_EL1_VPMR_MAX_SHIFT ULL(18) 1232 #define MPAMIDR_EL1_VPMR_MAX_MASK ULL(0x7) 1233 /******************************************************************************* 1234 * Definitions for system register interface to AMU for FEAT_AMUv1 1235 ******************************************************************************/ 1236 #define AMCR_EL0 S3_3_C13_C2_0 1237 #define AMCFGR_EL0 S3_3_C13_C2_1 1238 #define AMCGCR_EL0 S3_3_C13_C2_2 1239 #define AMUSERENR_EL0 S3_3_C13_C2_3 1240 #define AMCNTENCLR0_EL0 S3_3_C13_C2_4 1241 #define AMCNTENSET0_EL0 S3_3_C13_C2_5 1242 #define AMCNTENCLR1_EL0 S3_3_C13_C3_0 1243 #define AMCNTENSET1_EL0 S3_3_C13_C3_1 1244 1245 /* Activity Monitor Group 0 Event Counter Registers */ 1246 #define AMEVCNTR00_EL0 S3_3_C13_C4_0 1247 #define AMEVCNTR01_EL0 S3_3_C13_C4_1 1248 #define AMEVCNTR02_EL0 S3_3_C13_C4_2 1249 #define AMEVCNTR03_EL0 S3_3_C13_C4_3 1250 1251 /* Activity Monitor Group 0 Event Type Registers */ 1252 #define AMEVTYPER00_EL0 S3_3_C13_C6_0 1253 #define AMEVTYPER01_EL0 S3_3_C13_C6_1 1254 #define AMEVTYPER02_EL0 S3_3_C13_C6_2 1255 #define AMEVTYPER03_EL0 S3_3_C13_C6_3 1256 1257 /* Activity Monitor Group 1 Event Counter Registers */ 1258 #define AMEVCNTR10_EL0 S3_3_C13_C12_0 1259 #define AMEVCNTR11_EL0 S3_3_C13_C12_1 1260 #define AMEVCNTR12_EL0 S3_3_C13_C12_2 1261 #define AMEVCNTR13_EL0 S3_3_C13_C12_3 1262 #define AMEVCNTR14_EL0 S3_3_C13_C12_4 1263 #define AMEVCNTR15_EL0 S3_3_C13_C12_5 1264 #define AMEVCNTR16_EL0 S3_3_C13_C12_6 1265 #define AMEVCNTR17_EL0 S3_3_C13_C12_7 1266 #define AMEVCNTR18_EL0 S3_3_C13_C13_0 1267 #define AMEVCNTR19_EL0 S3_3_C13_C13_1 1268 #define AMEVCNTR1A_EL0 S3_3_C13_C13_2 1269 #define AMEVCNTR1B_EL0 S3_3_C13_C13_3 1270 #define AMEVCNTR1C_EL0 S3_3_C13_C13_4 1271 #define AMEVCNTR1D_EL0 S3_3_C13_C13_5 1272 #define AMEVCNTR1E_EL0 S3_3_C13_C13_6 1273 #define AMEVCNTR1F_EL0 S3_3_C13_C13_7 1274 1275 /* Activity Monitor Group 1 Event Type Registers */ 1276 #define AMEVTYPER10_EL0 S3_3_C13_C14_0 1277 #define AMEVTYPER11_EL0 S3_3_C13_C14_1 1278 #define AMEVTYPER12_EL0 S3_3_C13_C14_2 1279 #define AMEVTYPER13_EL0 S3_3_C13_C14_3 1280 #define AMEVTYPER14_EL0 S3_3_C13_C14_4 1281 #define AMEVTYPER15_EL0 S3_3_C13_C14_5 1282 #define AMEVTYPER16_EL0 S3_3_C13_C14_6 1283 #define AMEVTYPER17_EL0 S3_3_C13_C14_7 1284 #define AMEVTYPER18_EL0 S3_3_C13_C15_0 1285 #define AMEVTYPER19_EL0 S3_3_C13_C15_1 1286 #define AMEVTYPER1A_EL0 S3_3_C13_C15_2 1287 #define AMEVTYPER1B_EL0 S3_3_C13_C15_3 1288 #define AMEVTYPER1C_EL0 S3_3_C13_C15_4 1289 #define AMEVTYPER1D_EL0 S3_3_C13_C15_5 1290 #define AMEVTYPER1E_EL0 S3_3_C13_C15_6 1291 #define AMEVTYPER1F_EL0 S3_3_C13_C15_7 1292 1293 /* AMCNTENSET0_EL0 definitions */ 1294 #define AMCNTENSET0_EL0_Pn_SHIFT U(0) 1295 #define AMCNTENSET0_EL0_Pn_MASK ULL(0xffff) 1296 1297 /* AMCNTENSET1_EL0 definitions */ 1298 #define AMCNTENSET1_EL0_Pn_SHIFT U(0) 1299 #define AMCNTENSET1_EL0_Pn_MASK ULL(0xffff) 1300 1301 /* AMCNTENCLR0_EL0 definitions */ 1302 #define AMCNTENCLR0_EL0_Pn_SHIFT U(0) 1303 #define AMCNTENCLR0_EL0_Pn_MASK ULL(0xffff) 1304 1305 /* AMCNTENCLR1_EL0 definitions */ 1306 #define AMCNTENCLR1_EL0_Pn_SHIFT U(0) 1307 #define AMCNTENCLR1_EL0_Pn_MASK ULL(0xffff) 1308 1309 /* AMCFGR_EL0 definitions */ 1310 #define AMCFGR_EL0_NCG_SHIFT U(28) 1311 #define AMCFGR_EL0_NCG_MASK U(0xf) 1312 #define AMCFGR_EL0_N_SHIFT U(0) 1313 #define AMCFGR_EL0_N_MASK U(0xff) 1314 1315 /* AMCGCR_EL0 definitions */ 1316 #define AMCGCR_EL0_CG0NC_SHIFT U(0) 1317 #define AMCGCR_EL0_CG0NC_MASK U(0xff) 1318 #define AMCGCR_EL0_CG1NC_SHIFT U(8) 1319 #define AMCGCR_EL0_CG1NC_MASK U(0xff) 1320 1321 /* MPAM register definitions */ 1322 #define MPAM3_EL3_MPAMEN_BIT (ULL(1) << 63) 1323 #define MPAM3_EL3_TRAPLOWER_BIT (ULL(1) << 62) 1324 #define MPAMHCR_EL2_TRAP_MPAMIDR_EL1 (ULL(1) << 31) 1325 #define MPAM3_EL3_RESET_VAL MPAM3_EL3_TRAPLOWER_BIT 1326 1327 #define MPAM2_EL2_TRAPMPAM0EL1 (ULL(1) << 49) 1328 #define MPAM2_EL2_TRAPMPAM1EL1 (ULL(1) << 48) 1329 1330 #define MPAMIDR_HAS_HCR_BIT (ULL(1) << 17) 1331 1332 /******************************************************************************* 1333 * Definitions for system register interface to AMU for FEAT_AMUv1p1 1334 ******************************************************************************/ 1335 1336 /* Definition for register defining which virtual offsets are implemented. */ 1337 #define AMCG1IDR_EL0 S3_3_C13_C2_6 1338 #define AMCG1IDR_CTR_MASK ULL(0xffff) 1339 #define AMCG1IDR_CTR_SHIFT U(0) 1340 #define AMCG1IDR_VOFF_MASK ULL(0xffff) 1341 #define AMCG1IDR_VOFF_SHIFT U(16) 1342 1343 /* New bit added to AMCR_EL0 */ 1344 #define AMCR_CG1RZ_SHIFT U(17) 1345 #define AMCR_CG1RZ_BIT (ULL(0x1) << AMCR_CG1RZ_SHIFT) 1346 1347 /* 1348 * Definitions for virtual offset registers for architected activity monitor 1349 * event counters. 1350 * AMEVCNTVOFF01_EL2 intentionally left undefined, as it does not exist. 1351 */ 1352 #define AMEVCNTVOFF00_EL2 S3_4_C13_C8_0 1353 #define AMEVCNTVOFF02_EL2 S3_4_C13_C8_2 1354 #define AMEVCNTVOFF03_EL2 S3_4_C13_C8_3 1355 1356 /* 1357 * Definitions for virtual offset registers for auxiliary activity monitor event 1358 * counters. 1359 */ 1360 #define AMEVCNTVOFF10_EL2 S3_4_C13_C10_0 1361 #define AMEVCNTVOFF11_EL2 S3_4_C13_C10_1 1362 #define AMEVCNTVOFF12_EL2 S3_4_C13_C10_2 1363 #define AMEVCNTVOFF13_EL2 S3_4_C13_C10_3 1364 #define AMEVCNTVOFF14_EL2 S3_4_C13_C10_4 1365 #define AMEVCNTVOFF15_EL2 S3_4_C13_C10_5 1366 #define AMEVCNTVOFF16_EL2 S3_4_C13_C10_6 1367 #define AMEVCNTVOFF17_EL2 S3_4_C13_C10_7 1368 #define AMEVCNTVOFF18_EL2 S3_4_C13_C11_0 1369 #define AMEVCNTVOFF19_EL2 S3_4_C13_C11_1 1370 #define AMEVCNTVOFF1A_EL2 S3_4_C13_C11_2 1371 #define AMEVCNTVOFF1B_EL2 S3_4_C13_C11_3 1372 #define AMEVCNTVOFF1C_EL2 S3_4_C13_C11_4 1373 #define AMEVCNTVOFF1D_EL2 S3_4_C13_C11_5 1374 #define AMEVCNTVOFF1E_EL2 S3_4_C13_C11_6 1375 #define AMEVCNTVOFF1F_EL2 S3_4_C13_C11_7 1376 1377 /******************************************************************************* 1378 * Realm management extension register definitions 1379 ******************************************************************************/ 1380 #define GPCCR_EL3 S3_6_C2_C1_6 1381 #define GPTBR_EL3 S3_6_C2_C1_4 1382 1383 #define SCXTNUM_EL2 S3_4_C13_C0_7 1384 #define SCXTNUM_EL1 S3_0_C13_C0_7 1385 #define SCXTNUM_EL0 S3_3_C13_C0_7 1386 1387 /******************************************************************************* 1388 * RAS system registers 1389 ******************************************************************************/ 1390 #define DISR_EL1 S3_0_C12_C1_1 1391 #define DISR_A_BIT U(31) 1392 1393 #define ERRIDR_EL1 S3_0_C5_C3_0 1394 #define ERRIDR_MASK U(0xffff) 1395 1396 #define ERRSELR_EL1 S3_0_C5_C3_1 1397 1398 /* System register access to Standard Error Record registers */ 1399 #define ERXFR_EL1 S3_0_C5_C4_0 1400 #define ERXCTLR_EL1 S3_0_C5_C4_1 1401 #define ERXSTATUS_EL1 S3_0_C5_C4_2 1402 #define ERXADDR_EL1 S3_0_C5_C4_3 1403 #define ERXPFGF_EL1 S3_0_C5_C4_4 1404 #define ERXPFGCTL_EL1 S3_0_C5_C4_5 1405 #define ERXPFGCDN_EL1 S3_0_C5_C4_6 1406 #define ERXMISC0_EL1 S3_0_C5_C5_0 1407 #define ERXMISC1_EL1 S3_0_C5_C5_1 1408 1409 #define ERXCTLR_ED_SHIFT U(0) 1410 #define ERXCTLR_ED_BIT (U(1) << ERXCTLR_ED_SHIFT) 1411 #define ERXCTLR_UE_BIT (U(1) << 4) 1412 1413 #define ERXPFGCTL_UC_BIT (U(1) << 1) 1414 #define ERXPFGCTL_UEU_BIT (U(1) << 2) 1415 #define ERXPFGCTL_CDEN_BIT (U(1) << 31) 1416 1417 /******************************************************************************* 1418 * Armv8.3 Pointer Authentication Registers 1419 ******************************************************************************/ 1420 #define APIAKeyLo_EL1 S3_0_C2_C1_0 1421 #define APIAKeyHi_EL1 S3_0_C2_C1_1 1422 #define APIBKeyLo_EL1 S3_0_C2_C1_2 1423 #define APIBKeyHi_EL1 S3_0_C2_C1_3 1424 #define APDAKeyLo_EL1 S3_0_C2_C2_0 1425 #define APDAKeyHi_EL1 S3_0_C2_C2_1 1426 #define APDBKeyLo_EL1 S3_0_C2_C2_2 1427 #define APDBKeyHi_EL1 S3_0_C2_C2_3 1428 #define APGAKeyLo_EL1 S3_0_C2_C3_0 1429 #define APGAKeyHi_EL1 S3_0_C2_C3_1 1430 1431 /******************************************************************************* 1432 * Armv8.4 Data Independent Timing Registers 1433 ******************************************************************************/ 1434 #define DIT S3_3_C4_C2_5 1435 #define DIT_BIT BIT(24) 1436 1437 /******************************************************************************* 1438 * Armv8.5 - new MSR encoding to directly access PSTATE.SSBS field 1439 ******************************************************************************/ 1440 #define SSBS S3_3_C4_C2_6 1441 1442 /******************************************************************************* 1443 * Armv8.5 - Memory Tagging Extension Registers 1444 ******************************************************************************/ 1445 #define TFSRE0_EL1 S3_0_C5_C6_1 1446 #define TFSR_EL1 S3_0_C5_C6_0 1447 #define RGSR_EL1 S3_0_C1_C0_5 1448 #define GCR_EL1 S3_0_C1_C0_6 1449 1450 #define GCR_EL1_RRND_BIT (UL(1) << 16) 1451 1452 /******************************************************************************* 1453 * Armv8.5 - Random Number Generator Registers 1454 ******************************************************************************/ 1455 #define RNDR S3_3_C2_C4_0 1456 #define RNDRRS S3_3_C2_C4_1 1457 1458 /******************************************************************************* 1459 * FEAT_HCX - Extended Hypervisor Configuration Register 1460 ******************************************************************************/ 1461 #define HCRX_EL2 S3_4_C1_C2_2 1462 #define HCRX_EL2_MSCEn_BIT (UL(1) << 11) 1463 #define HCRX_EL2_MCE2_BIT (UL(1) << 10) 1464 #define HCRX_EL2_CMOW_BIT (UL(1) << 9) 1465 #define HCRX_EL2_VFNMI_BIT (UL(1) << 8) 1466 #define HCRX_EL2_VINMI_BIT (UL(1) << 7) 1467 #define HCRX_EL2_TALLINT_BIT (UL(1) << 6) 1468 #define HCRX_EL2_SMPME_BIT (UL(1) << 5) 1469 #define HCRX_EL2_FGTnXS_BIT (UL(1) << 4) 1470 #define HCRX_EL2_FnXS_BIT (UL(1) << 3) 1471 #define HCRX_EL2_EnASR_BIT (UL(1) << 2) 1472 #define HCRX_EL2_EnALS_BIT (UL(1) << 1) 1473 #define HCRX_EL2_EnAS0_BIT (UL(1) << 0) 1474 #define HCRX_EL2_INIT_VAL ULL(0x0) 1475 1476 /******************************************************************************* 1477 * FEAT_FGT - Definitions for Fine-Grained Trap registers 1478 ******************************************************************************/ 1479 #define HFGITR_EL2_INIT_VAL ULL(0x180000000000000) 1480 #define HFGRTR_EL2_INIT_VAL ULL(0xC4000000000000) 1481 #define HFGWTR_EL2_INIT_VAL ULL(0xC4000000000000) 1482 1483 /******************************************************************************* 1484 * FEAT_TCR2 - Extended Translation Control Registers 1485 ******************************************************************************/ 1486 #define TCR2_EL1 S3_0_C2_C0_3 1487 #define TCR2_EL2 S3_4_C2_C0_3 1488 1489 /******************************************************************************* 1490 * Permission indirection and overlay Registers 1491 ******************************************************************************/ 1492 1493 #define PIRE0_EL1 S3_0_C10_C2_2 1494 #define PIRE0_EL2 S3_4_C10_C2_2 1495 #define PIR_EL1 S3_0_C10_C2_3 1496 #define PIR_EL2 S3_4_C10_C2_3 1497 #define POR_EL1 S3_0_C10_C2_4 1498 #define POR_EL2 S3_4_C10_C2_4 1499 #define S2PIR_EL2 S3_4_C10_C2_5 1500 #define S2POR_EL1 S3_0_C10_C2_5 1501 1502 /******************************************************************************* 1503 * FEAT_GCS - Guarded Control Stack Registers 1504 ******************************************************************************/ 1505 #define GCSCR_EL2 S3_4_C2_C5_0 1506 #define GCSPR_EL2 S3_4_C2_C5_1 1507 #define GCSCR_EL1 S3_0_C2_C5_0 1508 #define GCSCRE0_EL1 S3_0_C2_C5_2 1509 #define GCSPR_EL1 S3_0_C2_C5_1 1510 #define GCSPR_EL0 S3_3_C2_C5_1 1511 1512 #define GCSCR_EXLOCK_EN_BIT (UL(1) << 6) 1513 1514 /******************************************************************************* 1515 * FEAT_TRF - Trace Filter Control Registers 1516 ******************************************************************************/ 1517 #define TRFCR_EL2 S3_4_C1_C2_1 1518 #define TRFCR_EL1 S3_0_C1_C2_1 1519 1520 /******************************************************************************* 1521 * FEAT_THE - Translation Hardening Extension Registers 1522 ******************************************************************************/ 1523 #define RCWMASK_EL1 S3_0_C13_C0_6 1524 #define RCWSMASK_EL1 S3_0_C13_C0_3 1525 1526 /******************************************************************************* 1527 * FEAT_SCTLR2 - Extension to SCTLR_ELx Registers 1528 ******************************************************************************/ 1529 #define SCTLR2_EL2 S3_4_C1_C0_3 1530 #define SCTLR2_EL1 S3_0_C1_C0_3 1531 1532 /******************************************************************************* 1533 * FEAT_LS64_ACCDATA - LoadStore64B with status data 1534 ******************************************************************************/ 1535 #define ACCDATA_EL1 S3_0_C13_C0_5 1536 1537 /******************************************************************************* 1538 * Definitions for DynamicIQ Shared Unit registers 1539 ******************************************************************************/ 1540 #define CLUSTERPWRDN_EL1 S3_0_c15_c3_6 1541 1542 /******************************************************************************* 1543 * FEAT_FPMR - Floating point Mode Register 1544 ******************************************************************************/ 1545 #define FPMR S3_3_C4_C4_2 1546 1547 /* CLUSTERPWRDN_EL1 register definitions */ 1548 #define DSU_CLUSTER_PWR_OFF 0 1549 #define DSU_CLUSTER_PWR_ON 1 1550 #define DSU_CLUSTER_PWR_MASK U(1) 1551 #define DSU_CLUSTER_MEM_RET BIT(1) 1552 1553 /******************************************************************************* 1554 * Definitions for CPU Power/Performance Management registers 1555 ******************************************************************************/ 1556 1557 #define CPUPPMCR_EL3 S3_6_C15_C2_0 1558 #define CPUPPMCR_EL3_MPMMPINCTL_SHIFT UINT64_C(0) 1559 #define CPUPPMCR_EL3_MPMMPINCTL_MASK UINT64_C(0x1) 1560 1561 #define CPUMPMMCR_EL3 S3_6_C15_C2_1 1562 #define CPUMPMMCR_EL3_MPMM_EN_SHIFT UINT64_C(0) 1563 #define CPUMPMMCR_EL3_MPMM_EN_MASK UINT64_C(0x1) 1564 1565 /* alternative system register encoding for the "sb" speculation barrier */ 1566 #define SYSREG_SB S0_3_C3_C0_7 1567 1568 #define CLUSTERPMCR_EL1 S3_0_C15_C5_0 1569 #define CLUSTERPMCNTENSET_EL1 S3_0_C15_C5_1 1570 #define CLUSTERPMCCNTR_EL1 S3_0_C15_C6_0 1571 #define CLUSTERPMOVSSET_EL1 S3_0_C15_C5_3 1572 #define CLUSTERPMOVSCLR_EL1 S3_0_C15_C5_4 1573 #define CLUSTERPMSELR_EL1 S3_0_C15_C5_5 1574 #define CLUSTERPMXEVTYPER_EL1 S3_0_C15_C6_1 1575 #define CLUSTERPMXEVCNTR_EL1 S3_0_C15_C6_2 1576 1577 #define CLUSTERPMCR_E_BIT BIT(0) 1578 #define CLUSTERPMCR_N_SHIFT U(11) 1579 #define CLUSTERPMCR_N_MASK U(0x1f) 1580 1581 #endif /* ARCH_H */ 1582