1 /* 2 * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef ARCH_H 8 #define ARCH_H 9 10 #include <lib/utils_def.h> 11 12 /******************************************************************************* 13 * MIDR bit definitions 14 ******************************************************************************/ 15 #define MIDR_IMPL_MASK U(0xff) 16 #define MIDR_IMPL_SHIFT U(0x18) 17 #define MIDR_VAR_SHIFT U(20) 18 #define MIDR_VAR_BITS U(4) 19 #define MIDR_VAR_MASK U(0xf) 20 #define MIDR_REV_SHIFT U(0) 21 #define MIDR_REV_BITS U(4) 22 #define MIDR_REV_MASK U(0xf) 23 #define MIDR_PN_MASK U(0xfff) 24 #define MIDR_PN_SHIFT U(0x4) 25 26 /******************************************************************************* 27 * MPIDR macros 28 ******************************************************************************/ 29 #define MPIDR_MT_MASK (ULL(1) << 24) 30 #define MPIDR_CPU_MASK MPIDR_AFFLVL_MASK 31 #define MPIDR_CLUSTER_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS) 32 #define MPIDR_AFFINITY_BITS U(8) 33 #define MPIDR_AFFLVL_MASK ULL(0xff) 34 #define MPIDR_AFF0_SHIFT U(0) 35 #define MPIDR_AFF1_SHIFT U(8) 36 #define MPIDR_AFF2_SHIFT U(16) 37 #define MPIDR_AFF3_SHIFT U(32) 38 #define MPIDR_AFF_SHIFT(_n) MPIDR_AFF##_n##_SHIFT 39 #define MPIDR_AFFINITY_MASK ULL(0xff00ffffff) 40 #define MPIDR_AFFLVL_SHIFT U(3) 41 #define MPIDR_AFFLVL0 ULL(0x0) 42 #define MPIDR_AFFLVL1 ULL(0x1) 43 #define MPIDR_AFFLVL2 ULL(0x2) 44 #define MPIDR_AFFLVL3 ULL(0x3) 45 #define MPIDR_AFFLVL(_n) MPIDR_AFFLVL##_n 46 #define MPIDR_AFFLVL0_VAL(mpidr) \ 47 (((mpidr) >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK) 48 #define MPIDR_AFFLVL1_VAL(mpidr) \ 49 (((mpidr) >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK) 50 #define MPIDR_AFFLVL2_VAL(mpidr) \ 51 (((mpidr) >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK) 52 #define MPIDR_AFFLVL3_VAL(mpidr) \ 53 (((mpidr) >> MPIDR_AFF3_SHIFT) & MPIDR_AFFLVL_MASK) 54 /* 55 * The MPIDR_MAX_AFFLVL count starts from 0. Take care to 56 * add one while using this macro to define array sizes. 57 * TODO: Support only the first 3 affinity levels for now. 58 */ 59 #define MPIDR_MAX_AFFLVL U(2) 60 61 #define MPID_MASK (MPIDR_MT_MASK | \ 62 (MPIDR_AFFLVL_MASK << MPIDR_AFF3_SHIFT) | \ 63 (MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT) | \ 64 (MPIDR_AFFLVL_MASK << MPIDR_AFF1_SHIFT) | \ 65 (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT)) 66 67 #define MPIDR_AFF_ID(mpid, n) \ 68 (((mpid) >> MPIDR_AFF_SHIFT(n)) & MPIDR_AFFLVL_MASK) 69 70 /* 71 * An invalid MPID. This value can be used by functions that return an MPID to 72 * indicate an error. 73 */ 74 #define INVALID_MPID U(0xFFFFFFFF) 75 76 /******************************************************************************* 77 * Definitions for CPU system register interface to GICv3 78 ******************************************************************************/ 79 #define ICC_IGRPEN1_EL1 S3_0_C12_C12_7 80 #define ICC_SGI1R S3_0_C12_C11_5 81 #define ICC_SRE_EL1 S3_0_C12_C12_5 82 #define ICC_SRE_EL2 S3_4_C12_C9_5 83 #define ICC_SRE_EL3 S3_6_C12_C12_5 84 #define ICC_CTLR_EL1 S3_0_C12_C12_4 85 #define ICC_CTLR_EL3 S3_6_C12_C12_4 86 #define ICC_PMR_EL1 S3_0_C4_C6_0 87 #define ICC_RPR_EL1 S3_0_C12_C11_3 88 #define ICC_IGRPEN1_EL3 S3_6_c12_c12_7 89 #define ICC_IGRPEN0_EL1 S3_0_c12_c12_6 90 #define ICC_HPPIR0_EL1 S3_0_c12_c8_2 91 #define ICC_HPPIR1_EL1 S3_0_c12_c12_2 92 #define ICC_IAR0_EL1 S3_0_c12_c8_0 93 #define ICC_IAR1_EL1 S3_0_c12_c12_0 94 #define ICC_EOIR0_EL1 S3_0_c12_c8_1 95 #define ICC_EOIR1_EL1 S3_0_c12_c12_1 96 #define ICC_SGI0R_EL1 S3_0_c12_c11_7 97 98 /******************************************************************************* 99 * Generic timer memory mapped registers & offsets 100 ******************************************************************************/ 101 #define CNTCR_OFF U(0x000) 102 #define CNTCV_OFF U(0x008) 103 #define CNTFID_OFF U(0x020) 104 105 #define CNTCR_EN (U(1) << 0) 106 #define CNTCR_HDBG (U(1) << 1) 107 #define CNTCR_FCREQ(x) ((x) << 8) 108 109 /******************************************************************************* 110 * System register bit definitions 111 ******************************************************************************/ 112 /* CLIDR definitions */ 113 #define LOUIS_SHIFT U(21) 114 #define LOC_SHIFT U(24) 115 #define CTYPE_SHIFT(n) U(3 * (n - 1)) 116 #define CLIDR_FIELD_WIDTH U(3) 117 118 /* CSSELR definitions */ 119 #define LEVEL_SHIFT U(1) 120 121 /* Data cache set/way op type defines */ 122 #define DCISW U(0x0) 123 #define DCCISW U(0x1) 124 #if ERRATA_A53_827319 125 #define DCCSW DCCISW 126 #else 127 #define DCCSW U(0x2) 128 #endif 129 130 /* ID_AA64PFR0_EL1 definitions */ 131 #define ID_AA64PFR0_EL0_SHIFT U(0) 132 #define ID_AA64PFR0_EL1_SHIFT U(4) 133 #define ID_AA64PFR0_EL2_SHIFT U(8) 134 #define ID_AA64PFR0_EL3_SHIFT U(12) 135 #define ID_AA64PFR0_AMU_SHIFT U(44) 136 #define ID_AA64PFR0_AMU_MASK ULL(0xf) 137 #define ID_AA64PFR0_ELX_MASK ULL(0xf) 138 #define ID_AA64PFR0_GIC_SHIFT U(24) 139 #define ID_AA64PFR0_GIC_WIDTH U(4) 140 #define ID_AA64PFR0_GIC_MASK ULL(0xf) 141 #define ID_AA64PFR0_SVE_SHIFT U(32) 142 #define ID_AA64PFR0_SVE_MASK ULL(0xf) 143 #define ID_AA64PFR0_MPAM_SHIFT U(40) 144 #define ID_AA64PFR0_MPAM_MASK ULL(0xf) 145 #define ID_AA64PFR0_DIT_SHIFT U(48) 146 #define ID_AA64PFR0_DIT_MASK ULL(0xf) 147 #define ID_AA64PFR0_DIT_LENGTH U(4) 148 #define ID_AA64PFR0_DIT_SUPPORTED U(1) 149 #define ID_AA64PFR0_CSV2_SHIFT U(56) 150 #define ID_AA64PFR0_CSV2_MASK ULL(0xf) 151 #define ID_AA64PFR0_CSV2_LENGTH U(4) 152 153 /* Exception level handling */ 154 #define EL_IMPL_NONE ULL(0) 155 #define EL_IMPL_A64ONLY ULL(1) 156 #define EL_IMPL_A64_A32 ULL(2) 157 158 /* ID_AA64DFR0_EL1.PMS definitions (for ARMv8.2+) */ 159 #define ID_AA64DFR0_PMS_SHIFT U(32) 160 #define ID_AA64DFR0_PMS_MASK ULL(0xf) 161 162 /* ID_AA64ISAR1_EL1 definitions */ 163 #define ID_AA64ISAR1_EL1 S3_0_C0_C6_1 164 #define ID_AA64ISAR1_GPI_SHIFT U(28) 165 #define ID_AA64ISAR1_GPI_MASK ULL(0xf) 166 #define ID_AA64ISAR1_GPA_SHIFT U(24) 167 #define ID_AA64ISAR1_GPA_MASK ULL(0xf) 168 #define ID_AA64ISAR1_API_SHIFT U(8) 169 #define ID_AA64ISAR1_API_MASK ULL(0xf) 170 #define ID_AA64ISAR1_APA_SHIFT U(4) 171 #define ID_AA64ISAR1_APA_MASK ULL(0xf) 172 173 /* ID_AA64MMFR0_EL1 definitions */ 174 #define ID_AA64MMFR0_EL1_PARANGE_SHIFT U(0) 175 #define ID_AA64MMFR0_EL1_PARANGE_MASK ULL(0xf) 176 177 #define PARANGE_0000 U(32) 178 #define PARANGE_0001 U(36) 179 #define PARANGE_0010 U(40) 180 #define PARANGE_0011 U(42) 181 #define PARANGE_0100 U(44) 182 #define PARANGE_0101 U(48) 183 #define PARANGE_0110 U(52) 184 185 #define ID_AA64MMFR0_EL1_TGRAN4_SHIFT U(28) 186 #define ID_AA64MMFR0_EL1_TGRAN4_MASK ULL(0xf) 187 #define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED ULL(0x0) 188 #define ID_AA64MMFR0_EL1_TGRAN4_NOT_SUPPORTED ULL(0xf) 189 190 #define ID_AA64MMFR0_EL1_TGRAN64_SHIFT U(24) 191 #define ID_AA64MMFR0_EL1_TGRAN64_MASK ULL(0xf) 192 #define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED ULL(0x0) 193 #define ID_AA64MMFR0_EL1_TGRAN64_NOT_SUPPORTED ULL(0xf) 194 195 #define ID_AA64MMFR0_EL1_TGRAN16_SHIFT U(20) 196 #define ID_AA64MMFR0_EL1_TGRAN16_MASK ULL(0xf) 197 #define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED ULL(0x1) 198 #define ID_AA64MMFR0_EL1_TGRAN16_NOT_SUPPORTED ULL(0x0) 199 200 /* ID_AA64MMFR2_EL1 definitions */ 201 #define ID_AA64MMFR2_EL1 S3_0_C0_C7_2 202 203 #define ID_AA64MMFR2_EL1_ST_SHIFT U(28) 204 #define ID_AA64MMFR2_EL1_ST_MASK ULL(0xf) 205 206 #define ID_AA64MMFR2_EL1_CNP_SHIFT U(0) 207 #define ID_AA64MMFR2_EL1_CNP_MASK ULL(0xf) 208 209 /* ID_AA64PFR1_EL1 definitions */ 210 #define ID_AA64PFR1_EL1_SSBS_SHIFT U(4) 211 #define ID_AA64PFR1_EL1_SSBS_MASK ULL(0xf) 212 213 #define SSBS_UNAVAILABLE ULL(0) /* No architectural SSBS support */ 214 215 #define ID_AA64PFR1_EL1_BT_SHIFT U(0) 216 #define ID_AA64PFR1_EL1_BT_MASK ULL(0xf) 217 218 #define BTI_IMPLEMENTED ULL(1) /* The BTI mechanism is implemented */ 219 220 #define ID_AA64PFR1_EL1_MTE_SHIFT U(8) 221 #define ID_AA64PFR1_EL1_MTE_MASK ULL(0xf) 222 223 #define MTE_UNIMPLEMENTED ULL(0) 224 #define MTE_IMPLEMENTED_EL0 ULL(1) /* MTE is only implemented at EL0 */ 225 #define MTE_IMPLEMENTED_ELX ULL(2) /* MTE is implemented at all ELs */ 226 227 /* ID_PFR1_EL1 definitions */ 228 #define ID_PFR1_VIRTEXT_SHIFT U(12) 229 #define ID_PFR1_VIRTEXT_MASK U(0xf) 230 #define GET_VIRT_EXT(id) (((id) >> ID_PFR1_VIRTEXT_SHIFT) \ 231 & ID_PFR1_VIRTEXT_MASK) 232 233 /* SCTLR definitions */ 234 #define SCTLR_EL2_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ 235 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \ 236 (U(1) << 11) | (U(1) << 5) | (U(1) << 4)) 237 238 #define SCTLR_EL1_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ 239 (U(1) << 22) | (U(1) << 20) | (U(1) << 11)) 240 #define SCTLR_AARCH32_EL1_RES1 \ 241 ((U(1) << 23) | (U(1) << 22) | (U(1) << 11) | \ 242 (U(1) << 4) | (U(1) << 3)) 243 244 #define SCTLR_EL3_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ 245 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \ 246 (U(1) << 11) | (U(1) << 5) | (U(1) << 4)) 247 248 #define SCTLR_M_BIT (ULL(1) << 0) 249 #define SCTLR_A_BIT (ULL(1) << 1) 250 #define SCTLR_C_BIT (ULL(1) << 2) 251 #define SCTLR_SA_BIT (ULL(1) << 3) 252 #define SCTLR_SA0_BIT (ULL(1) << 4) 253 #define SCTLR_CP15BEN_BIT (ULL(1) << 5) 254 #define SCTLR_ITD_BIT (ULL(1) << 7) 255 #define SCTLR_SED_BIT (ULL(1) << 8) 256 #define SCTLR_UMA_BIT (ULL(1) << 9) 257 #define SCTLR_I_BIT (ULL(1) << 12) 258 #define SCTLR_EnDB_BIT (ULL(1) << 13) 259 #define SCTLR_DZE_BIT (ULL(1) << 14) 260 #define SCTLR_UCT_BIT (ULL(1) << 15) 261 #define SCTLR_NTWI_BIT (ULL(1) << 16) 262 #define SCTLR_NTWE_BIT (ULL(1) << 18) 263 #define SCTLR_WXN_BIT (ULL(1) << 19) 264 #define SCTLR_UWXN_BIT (ULL(1) << 20) 265 #define SCTLR_IESB_BIT (ULL(1) << 21) 266 #define SCTLR_E0E_BIT (ULL(1) << 24) 267 #define SCTLR_EE_BIT (ULL(1) << 25) 268 #define SCTLR_UCI_BIT (ULL(1) << 26) 269 #define SCTLR_EnDA_BIT (ULL(1) << 27) 270 #define SCTLR_EnIB_BIT (ULL(1) << 30) 271 #define SCTLR_EnIA_BIT (ULL(1) << 31) 272 #define SCTLR_BT0_BIT (ULL(1) << 35) 273 #define SCTLR_BT1_BIT (ULL(1) << 36) 274 #define SCTLR_BT_BIT (ULL(1) << 36) 275 #define SCTLR_DSSBS_BIT (ULL(1) << 44) 276 #define SCTLR_RESET_VAL SCTLR_EL3_RES1 277 278 /* CPACR_El1 definitions */ 279 #define CPACR_EL1_FPEN(x) ((x) << 20) 280 #define CPACR_EL1_FP_TRAP_EL0 U(0x1) 281 #define CPACR_EL1_FP_TRAP_ALL U(0x2) 282 #define CPACR_EL1_FP_TRAP_NONE U(0x3) 283 284 /* SCR definitions */ 285 #define SCR_RES1_BITS ((U(1) << 4) | (U(1) << 5)) 286 #define SCR_ATA_BIT (U(1) << 26) 287 #define SCR_FIEN_BIT (U(1) << 21) 288 #define SCR_API_BIT (U(1) << 17) 289 #define SCR_APK_BIT (U(1) << 16) 290 #define SCR_TWE_BIT (U(1) << 13) 291 #define SCR_TWI_BIT (U(1) << 12) 292 #define SCR_ST_BIT (U(1) << 11) 293 #define SCR_RW_BIT (U(1) << 10) 294 #define SCR_SIF_BIT (U(1) << 9) 295 #define SCR_HCE_BIT (U(1) << 8) 296 #define SCR_SMD_BIT (U(1) << 7) 297 #define SCR_EA_BIT (U(1) << 3) 298 #define SCR_FIQ_BIT (U(1) << 2) 299 #define SCR_IRQ_BIT (U(1) << 1) 300 #define SCR_NS_BIT (U(1) << 0) 301 #define SCR_VALID_BIT_MASK U(0x2f8f) 302 #define SCR_RESET_VAL SCR_RES1_BITS 303 304 /* MDCR_EL3 definitions */ 305 #define MDCR_SCCD_BIT (ULL(1) << 23) 306 #define MDCR_SPME_BIT (ULL(1) << 17) 307 #define MDCR_SDD_BIT (ULL(1) << 16) 308 #define MDCR_SPD32(x) ((x) << 14) 309 #define MDCR_SPD32_LEGACY ULL(0x0) 310 #define MDCR_SPD32_DISABLE ULL(0x2) 311 #define MDCR_SPD32_ENABLE ULL(0x3) 312 #define MDCR_NSPB(x) ((x) << 12) 313 #define MDCR_NSPB_EL1 ULL(0x3) 314 #define MDCR_TDOSA_BIT (ULL(1) << 10) 315 #define MDCR_TDA_BIT (ULL(1) << 9) 316 #define MDCR_TPM_BIT (ULL(1) << 6) 317 #define MDCR_EL3_RESET_VAL ULL(0x0) 318 319 /* MDCR_EL2 definitions */ 320 #define MDCR_EL2_HLP (U(1) << 26) 321 #define MDCR_EL2_HCCD (U(1) << 23) 322 #define MDCR_EL2_TTRF (U(1) << 19) 323 #define MDCR_EL2_HPMD (U(1) << 17) 324 #define MDCR_EL2_TPMS (U(1) << 14) 325 #define MDCR_EL2_E2PB(x) ((x) << 12) 326 #define MDCR_EL2_E2PB_EL1 U(0x3) 327 #define MDCR_EL2_TDRA_BIT (U(1) << 11) 328 #define MDCR_EL2_TDOSA_BIT (U(1) << 10) 329 #define MDCR_EL2_TDA_BIT (U(1) << 9) 330 #define MDCR_EL2_TDE_BIT (U(1) << 8) 331 #define MDCR_EL2_HPME_BIT (U(1) << 7) 332 #define MDCR_EL2_TPM_BIT (U(1) << 6) 333 #define MDCR_EL2_TPMCR_BIT (U(1) << 5) 334 #define MDCR_EL2_RESET_VAL U(0x0) 335 336 /* HSTR_EL2 definitions */ 337 #define HSTR_EL2_RESET_VAL U(0x0) 338 #define HSTR_EL2_T_MASK U(0xff) 339 340 /* CNTHP_CTL_EL2 definitions */ 341 #define CNTHP_CTL_ENABLE_BIT (U(1) << 0) 342 #define CNTHP_CTL_RESET_VAL U(0x0) 343 344 /* VTTBR_EL2 definitions */ 345 #define VTTBR_RESET_VAL ULL(0x0) 346 #define VTTBR_VMID_MASK ULL(0xff) 347 #define VTTBR_VMID_SHIFT U(48) 348 #define VTTBR_BADDR_MASK ULL(0xffffffffffff) 349 #define VTTBR_BADDR_SHIFT U(0) 350 351 /* HCR definitions */ 352 #define HCR_API_BIT (ULL(1) << 41) 353 #define HCR_APK_BIT (ULL(1) << 40) 354 #define HCR_TGE_BIT (ULL(1) << 27) 355 #define HCR_RW_SHIFT U(31) 356 #define HCR_RW_BIT (ULL(1) << HCR_RW_SHIFT) 357 #define HCR_AMO_BIT (ULL(1) << 5) 358 #define HCR_IMO_BIT (ULL(1) << 4) 359 #define HCR_FMO_BIT (ULL(1) << 3) 360 361 /* ISR definitions */ 362 #define ISR_A_SHIFT U(8) 363 #define ISR_I_SHIFT U(7) 364 #define ISR_F_SHIFT U(6) 365 366 /* CNTHCTL_EL2 definitions */ 367 #define CNTHCTL_RESET_VAL U(0x0) 368 #define EVNTEN_BIT (U(1) << 2) 369 #define EL1PCEN_BIT (U(1) << 1) 370 #define EL1PCTEN_BIT (U(1) << 0) 371 372 /* CNTKCTL_EL1 definitions */ 373 #define EL0PTEN_BIT (U(1) << 9) 374 #define EL0VTEN_BIT (U(1) << 8) 375 #define EL0PCTEN_BIT (U(1) << 0) 376 #define EL0VCTEN_BIT (U(1) << 1) 377 #define EVNTEN_BIT (U(1) << 2) 378 #define EVNTDIR_BIT (U(1) << 3) 379 #define EVNTI_SHIFT U(4) 380 #define EVNTI_MASK U(0xf) 381 382 /* CPTR_EL3 definitions */ 383 #define TCPAC_BIT (U(1) << 31) 384 #define TAM_BIT (U(1) << 30) 385 #define TTA_BIT (U(1) << 20) 386 #define TFP_BIT (U(1) << 10) 387 #define CPTR_EZ_BIT (U(1) << 8) 388 #define CPTR_EL3_RESET_VAL U(0x0) 389 390 /* CPTR_EL2 definitions */ 391 #define CPTR_EL2_RES1 ((U(1) << 13) | (U(1) << 12) | (U(0x3ff))) 392 #define CPTR_EL2_TCPAC_BIT (U(1) << 31) 393 #define CPTR_EL2_TAM_BIT (U(1) << 30) 394 #define CPTR_EL2_TTA_BIT (U(1) << 20) 395 #define CPTR_EL2_TFP_BIT (U(1) << 10) 396 #define CPTR_EL2_TZ_BIT (U(1) << 8) 397 #define CPTR_EL2_RESET_VAL CPTR_EL2_RES1 398 399 /* CPSR/SPSR definitions */ 400 #define DAIF_FIQ_BIT (U(1) << 0) 401 #define DAIF_IRQ_BIT (U(1) << 1) 402 #define DAIF_ABT_BIT (U(1) << 2) 403 #define DAIF_DBG_BIT (U(1) << 3) 404 #define SPSR_DAIF_SHIFT U(6) 405 #define SPSR_DAIF_MASK U(0xf) 406 407 #define SPSR_AIF_SHIFT U(6) 408 #define SPSR_AIF_MASK U(0x7) 409 410 #define SPSR_E_SHIFT U(9) 411 #define SPSR_E_MASK U(0x1) 412 #define SPSR_E_LITTLE U(0x0) 413 #define SPSR_E_BIG U(0x1) 414 415 #define SPSR_T_SHIFT U(5) 416 #define SPSR_T_MASK U(0x1) 417 #define SPSR_T_ARM U(0x0) 418 #define SPSR_T_THUMB U(0x1) 419 420 #define SPSR_M_SHIFT U(4) 421 #define SPSR_M_MASK U(0x1) 422 #define SPSR_M_AARCH64 U(0x0) 423 #define SPSR_M_AARCH32 U(0x1) 424 425 #define SPSR_SSBS_BIT_AARCH64 BIT_64(12) 426 #define SPSR_SSBS_BIT_AARCH32 BIT_64(23) 427 428 #define DISABLE_ALL_EXCEPTIONS \ 429 (DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT | DAIF_DBG_BIT) 430 431 #define DISABLE_INTERRUPTS (DAIF_FIQ_BIT | DAIF_IRQ_BIT) 432 433 /* 434 * RMR_EL3 definitions 435 */ 436 #define RMR_EL3_RR_BIT (U(1) << 1) 437 #define RMR_EL3_AA64_BIT (U(1) << 0) 438 439 /* 440 * HI-VECTOR address for AArch32 state 441 */ 442 #define HI_VECTOR_BASE U(0xFFFF0000) 443 444 /* 445 * TCR defintions 446 */ 447 #define TCR_EL3_RES1 ((ULL(1) << 31) | (ULL(1) << 23)) 448 #define TCR_EL2_RES1 ((ULL(1) << 31) | (ULL(1) << 23)) 449 #define TCR_EL1_IPS_SHIFT U(32) 450 #define TCR_EL2_PS_SHIFT U(16) 451 #define TCR_EL3_PS_SHIFT U(16) 452 453 #define TCR_TxSZ_MIN ULL(16) 454 #define TCR_TxSZ_MAX ULL(39) 455 #define TCR_TxSZ_MAX_TTST ULL(48) 456 457 #define TCR_T0SZ_SHIFT U(0) 458 #define TCR_T1SZ_SHIFT U(16) 459 460 /* (internal) physical address size bits in EL3/EL1 */ 461 #define TCR_PS_BITS_4GB ULL(0x0) 462 #define TCR_PS_BITS_64GB ULL(0x1) 463 #define TCR_PS_BITS_1TB ULL(0x2) 464 #define TCR_PS_BITS_4TB ULL(0x3) 465 #define TCR_PS_BITS_16TB ULL(0x4) 466 #define TCR_PS_BITS_256TB ULL(0x5) 467 468 #define ADDR_MASK_48_TO_63 ULL(0xFFFF000000000000) 469 #define ADDR_MASK_44_TO_47 ULL(0x0000F00000000000) 470 #define ADDR_MASK_42_TO_43 ULL(0x00000C0000000000) 471 #define ADDR_MASK_40_TO_41 ULL(0x0000030000000000) 472 #define ADDR_MASK_36_TO_39 ULL(0x000000F000000000) 473 #define ADDR_MASK_32_TO_35 ULL(0x0000000F00000000) 474 475 #define TCR_RGN_INNER_NC (ULL(0x0) << 8) 476 #define TCR_RGN_INNER_WBA (ULL(0x1) << 8) 477 #define TCR_RGN_INNER_WT (ULL(0x2) << 8) 478 #define TCR_RGN_INNER_WBNA (ULL(0x3) << 8) 479 480 #define TCR_RGN_OUTER_NC (ULL(0x0) << 10) 481 #define TCR_RGN_OUTER_WBA (ULL(0x1) << 10) 482 #define TCR_RGN_OUTER_WT (ULL(0x2) << 10) 483 #define TCR_RGN_OUTER_WBNA (ULL(0x3) << 10) 484 485 #define TCR_SH_NON_SHAREABLE (ULL(0x0) << 12) 486 #define TCR_SH_OUTER_SHAREABLE (ULL(0x2) << 12) 487 #define TCR_SH_INNER_SHAREABLE (ULL(0x3) << 12) 488 489 #define TCR_RGN1_INNER_NC (ULL(0x0) << 24) 490 #define TCR_RGN1_INNER_WBA (ULL(0x1) << 24) 491 #define TCR_RGN1_INNER_WT (ULL(0x2) << 24) 492 #define TCR_RGN1_INNER_WBNA (ULL(0x3) << 24) 493 494 #define TCR_RGN1_OUTER_NC (ULL(0x0) << 26) 495 #define TCR_RGN1_OUTER_WBA (ULL(0x1) << 26) 496 #define TCR_RGN1_OUTER_WT (ULL(0x2) << 26) 497 #define TCR_RGN1_OUTER_WBNA (ULL(0x3) << 26) 498 499 #define TCR_SH1_NON_SHAREABLE (ULL(0x0) << 28) 500 #define TCR_SH1_OUTER_SHAREABLE (ULL(0x2) << 28) 501 #define TCR_SH1_INNER_SHAREABLE (ULL(0x3) << 28) 502 503 #define TCR_TG0_SHIFT U(14) 504 #define TCR_TG0_MASK ULL(3) 505 #define TCR_TG0_4K (ULL(0) << TCR_TG0_SHIFT) 506 #define TCR_TG0_64K (ULL(1) << TCR_TG0_SHIFT) 507 #define TCR_TG0_16K (ULL(2) << TCR_TG0_SHIFT) 508 509 #define TCR_TG1_SHIFT U(30) 510 #define TCR_TG1_MASK ULL(3) 511 #define TCR_TG1_16K (ULL(1) << TCR_TG1_SHIFT) 512 #define TCR_TG1_4K (ULL(2) << TCR_TG1_SHIFT) 513 #define TCR_TG1_64K (ULL(3) << TCR_TG1_SHIFT) 514 515 #define TCR_EPD0_BIT (ULL(1) << 7) 516 #define TCR_EPD1_BIT (ULL(1) << 23) 517 518 #define MODE_SP_SHIFT U(0x0) 519 #define MODE_SP_MASK U(0x1) 520 #define MODE_SP_EL0 U(0x0) 521 #define MODE_SP_ELX U(0x1) 522 523 #define MODE_RW_SHIFT U(0x4) 524 #define MODE_RW_MASK U(0x1) 525 #define MODE_RW_64 U(0x0) 526 #define MODE_RW_32 U(0x1) 527 528 #define MODE_EL_SHIFT U(0x2) 529 #define MODE_EL_MASK U(0x3) 530 #define MODE_EL3 U(0x3) 531 #define MODE_EL2 U(0x2) 532 #define MODE_EL1 U(0x1) 533 #define MODE_EL0 U(0x0) 534 535 #define MODE32_SHIFT U(0) 536 #define MODE32_MASK U(0xf) 537 #define MODE32_usr U(0x0) 538 #define MODE32_fiq U(0x1) 539 #define MODE32_irq U(0x2) 540 #define MODE32_svc U(0x3) 541 #define MODE32_mon U(0x6) 542 #define MODE32_abt U(0x7) 543 #define MODE32_hyp U(0xa) 544 #define MODE32_und U(0xb) 545 #define MODE32_sys U(0xf) 546 547 #define GET_RW(mode) (((mode) >> MODE_RW_SHIFT) & MODE_RW_MASK) 548 #define GET_EL(mode) (((mode) >> MODE_EL_SHIFT) & MODE_EL_MASK) 549 #define GET_SP(mode) (((mode) >> MODE_SP_SHIFT) & MODE_SP_MASK) 550 #define GET_M32(mode) (((mode) >> MODE32_SHIFT) & MODE32_MASK) 551 552 #define SPSR_64(el, sp, daif) \ 553 (((MODE_RW_64 << MODE_RW_SHIFT) | \ 554 (((el) & MODE_EL_MASK) << MODE_EL_SHIFT) | \ 555 (((sp) & MODE_SP_MASK) << MODE_SP_SHIFT) | \ 556 (((daif) & SPSR_DAIF_MASK) << SPSR_DAIF_SHIFT)) & \ 557 (~(SPSR_SSBS_BIT_AARCH64))) 558 559 #define SPSR_MODE32(mode, isa, endian, aif) \ 560 (((MODE_RW_32 << MODE_RW_SHIFT) | \ 561 (((mode) & MODE32_MASK) << MODE32_SHIFT) | \ 562 (((isa) & SPSR_T_MASK) << SPSR_T_SHIFT) | \ 563 (((endian) & SPSR_E_MASK) << SPSR_E_SHIFT) | \ 564 (((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT)) & \ 565 (~(SPSR_SSBS_BIT_AARCH32))) 566 567 /* 568 * TTBR Definitions 569 */ 570 #define TTBR_CNP_BIT ULL(0x1) 571 572 /* 573 * CTR_EL0 definitions 574 */ 575 #define CTR_CWG_SHIFT U(24) 576 #define CTR_CWG_MASK U(0xf) 577 #define CTR_ERG_SHIFT U(20) 578 #define CTR_ERG_MASK U(0xf) 579 #define CTR_DMINLINE_SHIFT U(16) 580 #define CTR_DMINLINE_MASK U(0xf) 581 #define CTR_L1IP_SHIFT U(14) 582 #define CTR_L1IP_MASK U(0x3) 583 #define CTR_IMINLINE_SHIFT U(0) 584 #define CTR_IMINLINE_MASK U(0xf) 585 586 #define MAX_CACHE_LINE_SIZE U(0x800) /* 2KB */ 587 588 /* Physical timer control register bit fields shifts and masks */ 589 #define CNTP_CTL_ENABLE_SHIFT U(0) 590 #define CNTP_CTL_IMASK_SHIFT U(1) 591 #define CNTP_CTL_ISTATUS_SHIFT U(2) 592 593 #define CNTP_CTL_ENABLE_MASK U(1) 594 #define CNTP_CTL_IMASK_MASK U(1) 595 #define CNTP_CTL_ISTATUS_MASK U(1) 596 597 /* Exception Syndrome register bits and bobs */ 598 #define ESR_EC_SHIFT U(26) 599 #define ESR_EC_MASK U(0x3f) 600 #define ESR_EC_LENGTH U(6) 601 #define ESR_ISS_SHIFT U(0) 602 #define ESR_ISS_LENGTH U(25) 603 #define EC_UNKNOWN U(0x0) 604 #define EC_WFE_WFI U(0x1) 605 #define EC_AARCH32_CP15_MRC_MCR U(0x3) 606 #define EC_AARCH32_CP15_MRRC_MCRR U(0x4) 607 #define EC_AARCH32_CP14_MRC_MCR U(0x5) 608 #define EC_AARCH32_CP14_LDC_STC U(0x6) 609 #define EC_FP_SIMD U(0x7) 610 #define EC_AARCH32_CP10_MRC U(0x8) 611 #define EC_AARCH32_CP14_MRRC_MCRR U(0xc) 612 #define EC_ILLEGAL U(0xe) 613 #define EC_AARCH32_SVC U(0x11) 614 #define EC_AARCH32_HVC U(0x12) 615 #define EC_AARCH32_SMC U(0x13) 616 #define EC_AARCH64_SVC U(0x15) 617 #define EC_AARCH64_HVC U(0x16) 618 #define EC_AARCH64_SMC U(0x17) 619 #define EC_AARCH64_SYS U(0x18) 620 #define EC_IABORT_LOWER_EL U(0x20) 621 #define EC_IABORT_CUR_EL U(0x21) 622 #define EC_PC_ALIGN U(0x22) 623 #define EC_DABORT_LOWER_EL U(0x24) 624 #define EC_DABORT_CUR_EL U(0x25) 625 #define EC_SP_ALIGN U(0x26) 626 #define EC_AARCH32_FP U(0x28) 627 #define EC_AARCH64_FP U(0x2c) 628 #define EC_SERROR U(0x2f) 629 #define EC_BRK U(0x3c) 630 631 /* 632 * External Abort bit in Instruction and Data Aborts synchronous exception 633 * syndromes. 634 */ 635 #define ESR_ISS_EABORT_EA_BIT U(9) 636 637 #define EC_BITS(x) (((x) >> ESR_EC_SHIFT) & ESR_EC_MASK) 638 639 /* Reset bit inside the Reset management register for EL3 (RMR_EL3) */ 640 #define RMR_RESET_REQUEST_SHIFT U(0x1) 641 #define RMR_WARM_RESET_CPU (U(1) << RMR_RESET_REQUEST_SHIFT) 642 643 /******************************************************************************* 644 * Definitions of register offsets, fields and macros for CPU system 645 * instructions. 646 ******************************************************************************/ 647 648 #define TLBI_ADDR_SHIFT U(12) 649 #define TLBI_ADDR_MASK ULL(0x00000FFFFFFFFFFF) 650 #define TLBI_ADDR(x) (((x) >> TLBI_ADDR_SHIFT) & TLBI_ADDR_MASK) 651 652 /******************************************************************************* 653 * Definitions of register offsets and fields in the CNTCTLBase Frame of the 654 * system level implementation of the Generic Timer. 655 ******************************************************************************/ 656 #define CNTCTLBASE_CNTFRQ U(0x0) 657 #define CNTNSAR U(0x4) 658 #define CNTNSAR_NS_SHIFT(x) (x) 659 660 #define CNTACR_BASE(x) (U(0x40) + ((x) << 2)) 661 #define CNTACR_RPCT_SHIFT U(0x0) 662 #define CNTACR_RVCT_SHIFT U(0x1) 663 #define CNTACR_RFRQ_SHIFT U(0x2) 664 #define CNTACR_RVOFF_SHIFT U(0x3) 665 #define CNTACR_RWVT_SHIFT U(0x4) 666 #define CNTACR_RWPT_SHIFT U(0x5) 667 668 /******************************************************************************* 669 * Definitions of register offsets and fields in the CNTBaseN Frame of the 670 * system level implementation of the Generic Timer. 671 ******************************************************************************/ 672 /* Physical Count register. */ 673 #define CNTPCT_LO U(0x0) 674 /* Counter Frequency register. */ 675 #define CNTBASEN_CNTFRQ U(0x10) 676 /* Physical Timer CompareValue register. */ 677 #define CNTP_CVAL_LO U(0x20) 678 /* Physical Timer Control register. */ 679 #define CNTP_CTL U(0x2c) 680 681 /* PMCR_EL0 definitions */ 682 #define PMCR_EL0_RESET_VAL U(0x0) 683 #define PMCR_EL0_N_SHIFT U(11) 684 #define PMCR_EL0_N_MASK U(0x1f) 685 #define PMCR_EL0_N_BITS (PMCR_EL0_N_MASK << PMCR_EL0_N_SHIFT) 686 #define PMCR_EL0_LP_BIT (U(1) << 7) 687 #define PMCR_EL0_LC_BIT (U(1) << 6) 688 #define PMCR_EL0_DP_BIT (U(1) << 5) 689 #define PMCR_EL0_X_BIT (U(1) << 4) 690 #define PMCR_EL0_D_BIT (U(1) << 3) 691 #define PMCR_EL0_C_BIT (U(1) << 2) 692 #define PMCR_EL0_P_BIT (U(1) << 1) 693 #define PMCR_EL0_E_BIT (U(1) << 0) 694 695 /******************************************************************************* 696 * Definitions for system register interface to SVE 697 ******************************************************************************/ 698 #define ZCR_EL3 S3_6_C1_C2_0 699 #define ZCR_EL2 S3_4_C1_C2_0 700 701 /* ZCR_EL3 definitions */ 702 #define ZCR_EL3_LEN_MASK U(0xf) 703 704 /* ZCR_EL2 definitions */ 705 #define ZCR_EL2_LEN_MASK U(0xf) 706 707 /******************************************************************************* 708 * Definitions of MAIR encodings for device and normal memory 709 ******************************************************************************/ 710 /* 711 * MAIR encodings for device memory attributes. 712 */ 713 #define MAIR_DEV_nGnRnE ULL(0x0) 714 #define MAIR_DEV_nGnRE ULL(0x4) 715 #define MAIR_DEV_nGRE ULL(0x8) 716 #define MAIR_DEV_GRE ULL(0xc) 717 718 /* 719 * MAIR encodings for normal memory attributes. 720 * 721 * Cache Policy 722 * WT: Write Through 723 * WB: Write Back 724 * NC: Non-Cacheable 725 * 726 * Transient Hint 727 * NTR: Non-Transient 728 * TR: Transient 729 * 730 * Allocation Policy 731 * RA: Read Allocate 732 * WA: Write Allocate 733 * RWA: Read and Write Allocate 734 * NA: No Allocation 735 */ 736 #define MAIR_NORM_WT_TR_WA ULL(0x1) 737 #define MAIR_NORM_WT_TR_RA ULL(0x2) 738 #define MAIR_NORM_WT_TR_RWA ULL(0x3) 739 #define MAIR_NORM_NC ULL(0x4) 740 #define MAIR_NORM_WB_TR_WA ULL(0x5) 741 #define MAIR_NORM_WB_TR_RA ULL(0x6) 742 #define MAIR_NORM_WB_TR_RWA ULL(0x7) 743 #define MAIR_NORM_WT_NTR_NA ULL(0x8) 744 #define MAIR_NORM_WT_NTR_WA ULL(0x9) 745 #define MAIR_NORM_WT_NTR_RA ULL(0xa) 746 #define MAIR_NORM_WT_NTR_RWA ULL(0xb) 747 #define MAIR_NORM_WB_NTR_NA ULL(0xc) 748 #define MAIR_NORM_WB_NTR_WA ULL(0xd) 749 #define MAIR_NORM_WB_NTR_RA ULL(0xe) 750 #define MAIR_NORM_WB_NTR_RWA ULL(0xf) 751 752 #define MAIR_NORM_OUTER_SHIFT U(4) 753 754 #define MAKE_MAIR_NORMAL_MEMORY(inner, outer) \ 755 ((inner) | ((outer) << MAIR_NORM_OUTER_SHIFT)) 756 757 /* PAR_EL1 fields */ 758 #define PAR_F_SHIFT U(0) 759 #define PAR_F_MASK ULL(0x1) 760 #define PAR_ADDR_SHIFT U(12) 761 #define PAR_ADDR_MASK (BIT(40) - ULL(1)) /* 40-bits-wide page address */ 762 763 /******************************************************************************* 764 * Definitions for system register interface to SPE 765 ******************************************************************************/ 766 #define PMBLIMITR_EL1 S3_0_C9_C10_0 767 768 /******************************************************************************* 769 * Definitions for system register interface to MPAM 770 ******************************************************************************/ 771 #define MPAMIDR_EL1 S3_0_C10_C4_4 772 #define MPAM2_EL2 S3_4_C10_C5_0 773 #define MPAMHCR_EL2 S3_4_C10_C4_0 774 #define MPAM3_EL3 S3_6_C10_C5_0 775 776 /******************************************************************************* 777 * Definitions for system register interface to AMU for ARMv8.4 onwards 778 ******************************************************************************/ 779 #define AMCR_EL0 S3_3_C13_C2_0 780 #define AMCFGR_EL0 S3_3_C13_C2_1 781 #define AMCGCR_EL0 S3_3_C13_C2_2 782 #define AMUSERENR_EL0 S3_3_C13_C2_3 783 #define AMCNTENCLR0_EL0 S3_3_C13_C2_4 784 #define AMCNTENSET0_EL0 S3_3_C13_C2_5 785 #define AMCNTENCLR1_EL0 S3_3_C13_C3_0 786 #define AMCNTENSET1_EL0 S3_3_C13_C3_1 787 788 /* Activity Monitor Group 0 Event Counter Registers */ 789 #define AMEVCNTR00_EL0 S3_3_C13_C4_0 790 #define AMEVCNTR01_EL0 S3_3_C13_C4_1 791 #define AMEVCNTR02_EL0 S3_3_C13_C4_2 792 #define AMEVCNTR03_EL0 S3_3_C13_C4_3 793 794 /* Activity Monitor Group 0 Event Type Registers */ 795 #define AMEVTYPER00_EL0 S3_3_C13_C6_0 796 #define AMEVTYPER01_EL0 S3_3_C13_C6_1 797 #define AMEVTYPER02_EL0 S3_3_C13_C6_2 798 #define AMEVTYPER03_EL0 S3_3_C13_C6_3 799 800 /* Activity Monitor Group 1 Event Counter Registers */ 801 #define AMEVCNTR10_EL0 S3_3_C13_C12_0 802 #define AMEVCNTR11_EL0 S3_3_C13_C12_1 803 #define AMEVCNTR12_EL0 S3_3_C13_C12_2 804 #define AMEVCNTR13_EL0 S3_3_C13_C12_3 805 #define AMEVCNTR14_EL0 S3_3_C13_C12_4 806 #define AMEVCNTR15_EL0 S3_3_C13_C12_5 807 #define AMEVCNTR16_EL0 S3_3_C13_C12_6 808 #define AMEVCNTR17_EL0 S3_3_C13_C12_7 809 #define AMEVCNTR18_EL0 S3_3_C13_C13_0 810 #define AMEVCNTR19_EL0 S3_3_C13_C13_1 811 #define AMEVCNTR1A_EL0 S3_3_C13_C13_2 812 #define AMEVCNTR1B_EL0 S3_3_C13_C13_3 813 #define AMEVCNTR1C_EL0 S3_3_C13_C13_4 814 #define AMEVCNTR1D_EL0 S3_3_C13_C13_5 815 #define AMEVCNTR1E_EL0 S3_3_C13_C13_6 816 #define AMEVCNTR1F_EL0 S3_3_C13_C13_7 817 818 /* Activity Monitor Group 1 Event Type Registers */ 819 #define AMEVTYPER10_EL0 S3_3_C13_C14_0 820 #define AMEVTYPER11_EL0 S3_3_C13_C14_1 821 #define AMEVTYPER12_EL0 S3_3_C13_C14_2 822 #define AMEVTYPER13_EL0 S3_3_C13_C14_3 823 #define AMEVTYPER14_EL0 S3_3_C13_C14_4 824 #define AMEVTYPER15_EL0 S3_3_C13_C14_5 825 #define AMEVTYPER16_EL0 S3_3_C13_C14_6 826 #define AMEVTYPER17_EL0 S3_3_C13_C14_7 827 #define AMEVTYPER18_EL0 S3_3_C13_C15_0 828 #define AMEVTYPER19_EL0 S3_3_C13_C15_1 829 #define AMEVTYPER1A_EL0 S3_3_C13_C15_2 830 #define AMEVTYPER1B_EL0 S3_3_C13_C15_3 831 #define AMEVTYPER1C_EL0 S3_3_C13_C15_4 832 #define AMEVTYPER1D_EL0 S3_3_C13_C15_5 833 #define AMEVTYPER1E_EL0 S3_3_C13_C15_6 834 #define AMEVTYPER1F_EL0 S3_3_C13_C15_7 835 836 /* AMCGCR_EL0 definitions */ 837 #define AMCGCR_EL0_CG1NC_SHIFT U(8) 838 #define AMCGCR_EL0_CG1NC_LENGTH U(8) 839 #define AMCGCR_EL0_CG1NC_MASK U(0xff) 840 841 /* MPAM register definitions */ 842 #define MPAM3_EL3_MPAMEN_BIT (ULL(1) << 63) 843 #define MPAMHCR_EL2_TRAP_MPAMIDR_EL1 (ULL(1) << 31) 844 845 #define MPAM2_EL2_TRAPMPAM0EL1 (ULL(1) << 49) 846 #define MPAM2_EL2_TRAPMPAM1EL1 (ULL(1) << 48) 847 848 #define MPAMIDR_HAS_HCR_BIT (ULL(1) << 17) 849 850 /******************************************************************************* 851 * RAS system registers 852 ******************************************************************************/ 853 #define DISR_EL1 S3_0_C12_C1_1 854 #define DISR_A_BIT U(31) 855 856 #define ERRIDR_EL1 S3_0_C5_C3_0 857 #define ERRIDR_MASK U(0xffff) 858 859 #define ERRSELR_EL1 S3_0_C5_C3_1 860 861 /* System register access to Standard Error Record registers */ 862 #define ERXFR_EL1 S3_0_C5_C4_0 863 #define ERXCTLR_EL1 S3_0_C5_C4_1 864 #define ERXSTATUS_EL1 S3_0_C5_C4_2 865 #define ERXADDR_EL1 S3_0_C5_C4_3 866 #define ERXPFGF_EL1 S3_0_C5_C4_4 867 #define ERXPFGCTL_EL1 S3_0_C5_C4_5 868 #define ERXPFGCDN_EL1 S3_0_C5_C4_6 869 #define ERXMISC0_EL1 S3_0_C5_C5_0 870 #define ERXMISC1_EL1 S3_0_C5_C5_1 871 872 #define ERXCTLR_ED_BIT (U(1) << 0) 873 #define ERXCTLR_UE_BIT (U(1) << 4) 874 875 #define ERXPFGCTL_UC_BIT (U(1) << 1) 876 #define ERXPFGCTL_UEU_BIT (U(1) << 2) 877 #define ERXPFGCTL_CDEN_BIT (U(1) << 31) 878 879 /******************************************************************************* 880 * Armv8.3 Pointer Authentication Registers 881 ******************************************************************************/ 882 #define APIAKeyLo_EL1 S3_0_C2_C1_0 883 #define APIAKeyHi_EL1 S3_0_C2_C1_1 884 #define APIBKeyLo_EL1 S3_0_C2_C1_2 885 #define APIBKeyHi_EL1 S3_0_C2_C1_3 886 #define APDAKeyLo_EL1 S3_0_C2_C2_0 887 #define APDAKeyHi_EL1 S3_0_C2_C2_1 888 #define APDBKeyLo_EL1 S3_0_C2_C2_2 889 #define APDBKeyHi_EL1 S3_0_C2_C2_3 890 #define APGAKeyLo_EL1 S3_0_C2_C3_0 891 #define APGAKeyHi_EL1 S3_0_C2_C3_1 892 893 /******************************************************************************* 894 * Armv8.4 Data Independent Timing Registers 895 ******************************************************************************/ 896 #define DIT S3_3_C4_C2_5 897 #define DIT_BIT BIT(24) 898 899 /******************************************************************************* 900 * Armv8.5 - new MSR encoding to directly access PSTATE.SSBS field 901 ******************************************************************************/ 902 #define SSBS S3_3_C4_C2_6 903 904 /******************************************************************************* 905 * Armv8.5 - Memory Tagging Extension Registers 906 ******************************************************************************/ 907 #define TFSRE0_EL1 S3_0_C5_C6_1 908 #define TFSR_EL1 S3_0_C5_C6_0 909 #define RGSR_EL1 S3_0_C1_C0_5 910 #define GCR_EL1 S3_0_C1_C0_6 911 912 #endif /* ARCH_H */ 913