1 /* 2 * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef ARCH_H 9 #define ARCH_H 10 11 #include <lib/utils_def.h> 12 13 /******************************************************************************* 14 * MIDR bit definitions 15 ******************************************************************************/ 16 #define MIDR_IMPL_MASK U(0xff) 17 #define MIDR_IMPL_SHIFT U(0x18) 18 #define MIDR_VAR_SHIFT U(20) 19 #define MIDR_VAR_BITS U(4) 20 #define MIDR_VAR_MASK U(0xf) 21 #define MIDR_REV_SHIFT U(0) 22 #define MIDR_REV_BITS U(4) 23 #define MIDR_REV_MASK U(0xf) 24 #define MIDR_PN_MASK U(0xfff) 25 #define MIDR_PN_SHIFT U(0x4) 26 27 /******************************************************************************* 28 * MPIDR macros 29 ******************************************************************************/ 30 #define MPIDR_MT_MASK (ULL(1) << 24) 31 #define MPIDR_CPU_MASK MPIDR_AFFLVL_MASK 32 #define MPIDR_CLUSTER_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS) 33 #define MPIDR_AFFINITY_BITS U(8) 34 #define MPIDR_AFFLVL_MASK ULL(0xff) 35 #define MPIDR_AFF0_SHIFT U(0) 36 #define MPIDR_AFF1_SHIFT U(8) 37 #define MPIDR_AFF2_SHIFT U(16) 38 #define MPIDR_AFF3_SHIFT U(32) 39 #define MPIDR_AFF_SHIFT(_n) MPIDR_AFF##_n##_SHIFT 40 #define MPIDR_AFFINITY_MASK ULL(0xff00ffffff) 41 #define MPIDR_AFFLVL_SHIFT U(3) 42 #define MPIDR_AFFLVL0 ULL(0x0) 43 #define MPIDR_AFFLVL1 ULL(0x1) 44 #define MPIDR_AFFLVL2 ULL(0x2) 45 #define MPIDR_AFFLVL3 ULL(0x3) 46 #define MPIDR_AFFLVL(_n) MPIDR_AFFLVL##_n 47 #define MPIDR_AFFLVL0_VAL(mpidr) \ 48 (((mpidr) >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK) 49 #define MPIDR_AFFLVL1_VAL(mpidr) \ 50 (((mpidr) >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK) 51 #define MPIDR_AFFLVL2_VAL(mpidr) \ 52 (((mpidr) >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK) 53 #define MPIDR_AFFLVL3_VAL(mpidr) \ 54 (((mpidr) >> MPIDR_AFF3_SHIFT) & MPIDR_AFFLVL_MASK) 55 /* 56 * The MPIDR_MAX_AFFLVL count starts from 0. Take care to 57 * add one while using this macro to define array sizes. 58 * TODO: Support only the first 3 affinity levels for now. 59 */ 60 #define MPIDR_MAX_AFFLVL U(2) 61 62 #define MPID_MASK (MPIDR_MT_MASK | \ 63 (MPIDR_AFFLVL_MASK << MPIDR_AFF3_SHIFT) | \ 64 (MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT) | \ 65 (MPIDR_AFFLVL_MASK << MPIDR_AFF1_SHIFT) | \ 66 (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT)) 67 68 #define MPIDR_AFF_ID(mpid, n) \ 69 (((mpid) >> MPIDR_AFF_SHIFT(n)) & MPIDR_AFFLVL_MASK) 70 71 /* 72 * An invalid MPID. This value can be used by functions that return an MPID to 73 * indicate an error. 74 */ 75 #define INVALID_MPID U(0xFFFFFFFF) 76 77 /******************************************************************************* 78 * Definitions for CPU system register interface to GICv3 79 ******************************************************************************/ 80 #define ICC_IGRPEN1_EL1 S3_0_C12_C12_7 81 #define ICC_SGI1R S3_0_C12_C11_5 82 #define ICC_SRE_EL1 S3_0_C12_C12_5 83 #define ICC_SRE_EL2 S3_4_C12_C9_5 84 #define ICC_SRE_EL3 S3_6_C12_C12_5 85 #define ICC_CTLR_EL1 S3_0_C12_C12_4 86 #define ICC_CTLR_EL3 S3_6_C12_C12_4 87 #define ICC_PMR_EL1 S3_0_C4_C6_0 88 #define ICC_RPR_EL1 S3_0_C12_C11_3 89 #define ICC_IGRPEN1_EL3 S3_6_c12_c12_7 90 #define ICC_IGRPEN0_EL1 S3_0_c12_c12_6 91 #define ICC_HPPIR0_EL1 S3_0_c12_c8_2 92 #define ICC_HPPIR1_EL1 S3_0_c12_c12_2 93 #define ICC_IAR0_EL1 S3_0_c12_c8_0 94 #define ICC_IAR1_EL1 S3_0_c12_c12_0 95 #define ICC_EOIR0_EL1 S3_0_c12_c8_1 96 #define ICC_EOIR1_EL1 S3_0_c12_c12_1 97 #define ICC_SGI0R_EL1 S3_0_c12_c11_7 98 99 /******************************************************************************* 100 * Definitions for EL2 system registers for save/restore routine 101 ******************************************************************************/ 102 103 #define CNTPOFF_EL2 S3_4_C14_C0_6 104 #define HAFGRTR_EL2 S3_4_C3_C1_6 105 #define HDFGRTR_EL2 S3_4_C3_C1_4 106 #define HDFGWTR_EL2 S3_4_C3_C1_5 107 #define HFGITR_EL2 S3_4_C1_C1_6 108 #define HFGRTR_EL2 S3_4_C1_C1_4 109 #define HFGWTR_EL2 S3_4_C1_C1_5 110 #define ICH_HCR_EL2 S3_4_C12_C11_0 111 #define ICH_VMCR_EL2 S3_4_C12_C11_7 112 #define MPAMVPM0_EL2 S3_4_C10_C5_0 113 #define MPAMVPM1_EL2 S3_4_C10_C5_1 114 #define MPAMVPM2_EL2 S3_4_C10_C5_2 115 #define MPAMVPM3_EL2 S3_4_C10_C5_3 116 #define MPAMVPM4_EL2 S3_4_C10_C5_4 117 #define MPAMVPM5_EL2 S3_4_C10_C5_5 118 #define MPAMVPM6_EL2 S3_4_C10_C5_6 119 #define MPAMVPM7_EL2 S3_4_C10_C5_7 120 #define MPAMVPMV_EL2 S3_4_C10_C4_1 121 #define TRFCR_EL2 S3_4_C1_C2_1 122 #define PMSCR_EL2 S3_4_C9_C9_0 123 #define TFSR_EL2 S3_4_C5_C6_0 124 125 /******************************************************************************* 126 * Generic timer memory mapped registers & offsets 127 ******************************************************************************/ 128 #define CNTCR_OFF U(0x000) 129 #define CNTCV_OFF U(0x008) 130 #define CNTFID_OFF U(0x020) 131 132 #define CNTCR_EN (U(1) << 0) 133 #define CNTCR_HDBG (U(1) << 1) 134 #define CNTCR_FCREQ(x) ((x) << 8) 135 136 /******************************************************************************* 137 * System register bit definitions 138 ******************************************************************************/ 139 /* CLIDR definitions */ 140 #define LOUIS_SHIFT U(21) 141 #define LOC_SHIFT U(24) 142 #define CTYPE_SHIFT(n) U(3 * (n - 1)) 143 #define CLIDR_FIELD_WIDTH U(3) 144 145 /* CSSELR definitions */ 146 #define LEVEL_SHIFT U(1) 147 148 /* Data cache set/way op type defines */ 149 #define DCISW U(0x0) 150 #define DCCISW U(0x1) 151 #if ERRATA_A53_827319 152 #define DCCSW DCCISW 153 #else 154 #define DCCSW U(0x2) 155 #endif 156 157 /* ID_AA64PFR0_EL1 definitions */ 158 #define ID_AA64PFR0_EL0_SHIFT U(0) 159 #define ID_AA64PFR0_EL1_SHIFT U(4) 160 #define ID_AA64PFR0_EL2_SHIFT U(8) 161 #define ID_AA64PFR0_EL3_SHIFT U(12) 162 #define ID_AA64PFR0_AMU_SHIFT U(44) 163 #define ID_AA64PFR0_AMU_MASK ULL(0xf) 164 #define ID_AA64PFR0_ELX_MASK ULL(0xf) 165 #define ID_AA64PFR0_GIC_SHIFT U(24) 166 #define ID_AA64PFR0_GIC_WIDTH U(4) 167 #define ID_AA64PFR0_GIC_MASK ULL(0xf) 168 #define ID_AA64PFR0_SVE_SHIFT U(32) 169 #define ID_AA64PFR0_SVE_MASK ULL(0xf) 170 #define ID_AA64PFR0_SEL2_SHIFT U(36) 171 #define ID_AA64PFR0_SEL2_MASK ULL(0xf) 172 #define ID_AA64PFR0_MPAM_SHIFT U(40) 173 #define ID_AA64PFR0_MPAM_MASK ULL(0xf) 174 #define ID_AA64PFR0_DIT_SHIFT U(48) 175 #define ID_AA64PFR0_DIT_MASK ULL(0xf) 176 #define ID_AA64PFR0_DIT_LENGTH U(4) 177 #define ID_AA64PFR0_DIT_SUPPORTED U(1) 178 #define ID_AA64PFR0_CSV2_SHIFT U(56) 179 #define ID_AA64PFR0_CSV2_MASK ULL(0xf) 180 #define ID_AA64PFR0_CSV2_LENGTH U(4) 181 182 /* Exception level handling */ 183 #define EL_IMPL_NONE ULL(0) 184 #define EL_IMPL_A64ONLY ULL(1) 185 #define EL_IMPL_A64_A32 ULL(2) 186 187 /* ID_AA64DFR0_EL1.PMS definitions (for ARMv8.2+) */ 188 #define ID_AA64DFR0_PMS_SHIFT U(32) 189 #define ID_AA64DFR0_PMS_MASK ULL(0xf) 190 191 /* ID_AA64ISAR1_EL1 definitions */ 192 #define ID_AA64ISAR1_EL1 S3_0_C0_C6_1 193 #define ID_AA64ISAR1_GPI_SHIFT U(28) 194 #define ID_AA64ISAR1_GPI_MASK ULL(0xf) 195 #define ID_AA64ISAR1_GPA_SHIFT U(24) 196 #define ID_AA64ISAR1_GPA_MASK ULL(0xf) 197 #define ID_AA64ISAR1_API_SHIFT U(8) 198 #define ID_AA64ISAR1_API_MASK ULL(0xf) 199 #define ID_AA64ISAR1_APA_SHIFT U(4) 200 #define ID_AA64ISAR1_APA_MASK ULL(0xf) 201 202 /* ID_AA64MMFR0_EL1 definitions */ 203 #define ID_AA64MMFR0_EL1_PARANGE_SHIFT U(0) 204 #define ID_AA64MMFR0_EL1_PARANGE_MASK ULL(0xf) 205 206 #define PARANGE_0000 U(32) 207 #define PARANGE_0001 U(36) 208 #define PARANGE_0010 U(40) 209 #define PARANGE_0011 U(42) 210 #define PARANGE_0100 U(44) 211 #define PARANGE_0101 U(48) 212 #define PARANGE_0110 U(52) 213 214 #define ID_AA64MMFR0_EL1_ECV_SHIFT U(60) 215 #define ID_AA64MMFR0_EL1_ECV_MASK ULL(0xf) 216 #define ID_AA64MMFR0_EL1_ECV_NOT_SUPPORTED ULL(0x0) 217 #define ID_AA64MMFR0_EL1_ECV_SUPPORTED ULL(0x1) 218 #define ID_AA64MMFR0_EL1_ECV_SELF_SYNCH ULL(0x2) 219 220 #define ID_AA64MMFR0_EL1_FGT_SHIFT U(56) 221 #define ID_AA64MMFR0_EL1_FGT_MASK ULL(0xf) 222 #define ID_AA64MMFR0_EL1_FGT_SUPPORTED ULL(0x1) 223 #define ID_AA64MMFR0_EL1_FGT_NOT_SUPPORTED ULL(0x0) 224 225 #define ID_AA64MMFR0_EL1_TGRAN4_SHIFT U(28) 226 #define ID_AA64MMFR0_EL1_TGRAN4_MASK ULL(0xf) 227 #define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED ULL(0x0) 228 #define ID_AA64MMFR0_EL1_TGRAN4_NOT_SUPPORTED ULL(0xf) 229 230 #define ID_AA64MMFR0_EL1_TGRAN64_SHIFT U(24) 231 #define ID_AA64MMFR0_EL1_TGRAN64_MASK ULL(0xf) 232 #define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED ULL(0x0) 233 #define ID_AA64MMFR0_EL1_TGRAN64_NOT_SUPPORTED ULL(0xf) 234 235 #define ID_AA64MMFR0_EL1_TGRAN16_SHIFT U(20) 236 #define ID_AA64MMFR0_EL1_TGRAN16_MASK ULL(0xf) 237 #define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED ULL(0x1) 238 #define ID_AA64MMFR0_EL1_TGRAN16_NOT_SUPPORTED ULL(0x0) 239 240 /* ID_AA64MMFR1_EL1 definitions */ 241 #define ID_AA64MMFR1_EL1_TWED_SHIFT U(32) 242 #define ID_AA64MMFR1_EL1_TWED_MASK ULL(0xf) 243 #define ID_AA64MMFR1_EL1_TWED_SUPPORTED ULL(0x1) 244 #define ID_AA64MMFR1_EL1_TWED_NOT_SUPPORTED ULL(0x0) 245 246 #define ID_AA64MMFR1_EL1_PAN_SHIFT U(20) 247 #define ID_AA64MMFR1_EL1_PAN_MASK ULL(0xf) 248 #define ID_AA64MMFR1_EL1_PAN_NOT_SUPPORTED ULL(0x0) 249 #define ID_AA64MMFR1_EL1_PAN_SUPPORTED ULL(0x1) 250 #define ID_AA64MMFR1_EL1_PAN2_SUPPORTED ULL(0x2) 251 #define ID_AA64MMFR1_EL1_PAN3_SUPPORTED ULL(0x3) 252 253 /* ID_AA64MMFR2_EL1 definitions */ 254 #define ID_AA64MMFR2_EL1 S3_0_C0_C7_2 255 256 #define ID_AA64MMFR2_EL1_ST_SHIFT U(28) 257 #define ID_AA64MMFR2_EL1_ST_MASK ULL(0xf) 258 259 #define ID_AA64MMFR2_EL1_CNP_SHIFT U(0) 260 #define ID_AA64MMFR2_EL1_CNP_MASK ULL(0xf) 261 262 /* ID_AA64PFR1_EL1 definitions */ 263 #define ID_AA64PFR1_EL1_SSBS_SHIFT U(4) 264 #define ID_AA64PFR1_EL1_SSBS_MASK ULL(0xf) 265 266 #define SSBS_UNAVAILABLE ULL(0) /* No architectural SSBS support */ 267 268 #define ID_AA64PFR1_EL1_BT_SHIFT U(0) 269 #define ID_AA64PFR1_EL1_BT_MASK ULL(0xf) 270 271 #define BTI_IMPLEMENTED ULL(1) /* The BTI mechanism is implemented */ 272 273 #define ID_AA64PFR1_EL1_MTE_SHIFT U(8) 274 #define ID_AA64PFR1_EL1_MTE_MASK ULL(0xf) 275 276 /* Memory Tagging Extension is not implemented */ 277 #define MTE_UNIMPLEMENTED U(0) 278 /* FEAT_MTE: MTE instructions accessible at EL0 are implemented */ 279 #define MTE_IMPLEMENTED_EL0 U(1) 280 /* FEAT_MTE2: Full MTE is implemented */ 281 #define MTE_IMPLEMENTED_ELX U(2) 282 /* 283 * FEAT_MTE3: MTE is implemented with support for 284 * asymmetric Tag Check Fault handling 285 */ 286 #define MTE_IMPLEMENTED_ASY U(3) 287 288 #define ID_AA64PFR1_MPAM_FRAC_SHIFT ULL(16) 289 #define ID_AA64PFR1_MPAM_FRAC_MASK ULL(0xf) 290 291 /* ID_PFR1_EL1 definitions */ 292 #define ID_PFR1_VIRTEXT_SHIFT U(12) 293 #define ID_PFR1_VIRTEXT_MASK U(0xf) 294 #define GET_VIRT_EXT(id) (((id) >> ID_PFR1_VIRTEXT_SHIFT) \ 295 & ID_PFR1_VIRTEXT_MASK) 296 297 /* SCTLR definitions */ 298 #define SCTLR_EL2_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ 299 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \ 300 (U(1) << 11) | (U(1) << 5) | (U(1) << 4)) 301 302 #define SCTLR_EL1_RES1 ((UL(1) << 29) | (UL(1) << 28) | (UL(1) << 23) | \ 303 (UL(1) << 22) | (UL(1) << 20) | (UL(1) << 11)) 304 305 #define SCTLR_AARCH32_EL1_RES1 \ 306 ((U(1) << 23) | (U(1) << 22) | (U(1) << 11) | \ 307 (U(1) << 4) | (U(1) << 3)) 308 309 #define SCTLR_EL3_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ 310 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \ 311 (U(1) << 11) | (U(1) << 5) | (U(1) << 4)) 312 313 #define SCTLR_M_BIT (ULL(1) << 0) 314 #define SCTLR_A_BIT (ULL(1) << 1) 315 #define SCTLR_C_BIT (ULL(1) << 2) 316 #define SCTLR_SA_BIT (ULL(1) << 3) 317 #define SCTLR_SA0_BIT (ULL(1) << 4) 318 #define SCTLR_CP15BEN_BIT (ULL(1) << 5) 319 #define SCTLR_nAA_BIT (ULL(1) << 6) 320 #define SCTLR_ITD_BIT (ULL(1) << 7) 321 #define SCTLR_SED_BIT (ULL(1) << 8) 322 #define SCTLR_UMA_BIT (ULL(1) << 9) 323 #define SCTLR_EnRCTX_BIT (ULL(1) << 10) 324 #define SCTLR_EOS_BIT (ULL(1) << 11) 325 #define SCTLR_I_BIT (ULL(1) << 12) 326 #define SCTLR_EnDB_BIT (ULL(1) << 13) 327 #define SCTLR_DZE_BIT (ULL(1) << 14) 328 #define SCTLR_UCT_BIT (ULL(1) << 15) 329 #define SCTLR_NTWI_BIT (ULL(1) << 16) 330 #define SCTLR_NTWE_BIT (ULL(1) << 18) 331 #define SCTLR_WXN_BIT (ULL(1) << 19) 332 #define SCTLR_TSCXT_BIT (ULL(1) << 20) 333 #define SCTLR_IESB_BIT (ULL(1) << 21) 334 #define SCTLR_EIS_BIT (ULL(1) << 22) 335 #define SCTLR_SPAN_BIT (ULL(1) << 23) 336 #define SCTLR_E0E_BIT (ULL(1) << 24) 337 #define SCTLR_EE_BIT (ULL(1) << 25) 338 #define SCTLR_UCI_BIT (ULL(1) << 26) 339 #define SCTLR_EnDA_BIT (ULL(1) << 27) 340 #define SCTLR_nTLSMD_BIT (ULL(1) << 28) 341 #define SCTLR_LSMAOE_BIT (ULL(1) << 29) 342 #define SCTLR_EnIB_BIT (ULL(1) << 30) 343 #define SCTLR_EnIA_BIT (ULL(1) << 31) 344 #define SCTLR_BT0_BIT (ULL(1) << 35) 345 #define SCTLR_BT1_BIT (ULL(1) << 36) 346 #define SCTLR_BT_BIT (ULL(1) << 36) 347 #define SCTLR_ITFSB_BIT (ULL(1) << 37) 348 #define SCTLR_TCF0_SHIFT U(38) 349 #define SCTLR_TCF0_MASK ULL(3) 350 351 /* Tag Check Faults in EL0 have no effect on the PE */ 352 #define SCTLR_TCF0_NO_EFFECT U(0) 353 /* Tag Check Faults in EL0 cause a synchronous exception */ 354 #define SCTLR_TCF0_SYNC U(1) 355 /* Tag Check Faults in EL0 are asynchronously accumulated */ 356 #define SCTLR_TCF0_ASYNC U(2) 357 /* 358 * Tag Check Faults in EL0 cause a synchronous exception on reads, 359 * and are asynchronously accumulated on writes 360 */ 361 #define SCTLR_TCF0_SYNCR_ASYNCW U(3) 362 363 #define SCTLR_TCF_SHIFT U(40) 364 #define SCTLR_TCF_MASK ULL(3) 365 366 /* Tag Check Faults in EL1 have no effect on the PE */ 367 #define SCTLR_TCF_NO_EFFECT U(0) 368 /* Tag Check Faults in EL1 cause a synchronous exception */ 369 #define SCTLR_TCF_SYNC U(1) 370 /* Tag Check Faults in EL1 are asynchronously accumulated */ 371 #define SCTLR_TCF_ASYNC U(2) 372 /* 373 * Tag Check Faults in EL1 cause a synchronous exception on reads, 374 * and are asynchronously accumulated on writes 375 */ 376 #define SCTLR_TCF_SYNCR_ASYNCW U(3) 377 378 #define SCTLR_ATA0_BIT (ULL(1) << 42) 379 #define SCTLR_ATA_BIT (ULL(1) << 43) 380 #define SCTLR_DSSBS_BIT (ULL(1) << 44) 381 #define SCTLR_TWEDEn_BIT (ULL(1) << 45) 382 #define SCTLR_TWEDEL_SHIFT U(46) 383 #define SCTLR_TWEDEL_MASK ULL(0xf) 384 #define SCTLR_EnASR_BIT (ULL(1) << 54) 385 #define SCTLR_EnAS0_BIT (ULL(1) << 55) 386 #define SCTLR_EnALS_BIT (ULL(1) << 56) 387 #define SCTLR_EPAN_BIT (ULL(1) << 57) 388 #define SCTLR_RESET_VAL SCTLR_EL3_RES1 389 390 /* CPACR_EL1 definitions */ 391 #define CPACR_EL1_FPEN(x) ((x) << 20) 392 #define CPACR_EL1_FP_TRAP_EL0 UL(0x1) 393 #define CPACR_EL1_FP_TRAP_ALL UL(0x2) 394 #define CPACR_EL1_FP_TRAP_NONE UL(0x3) 395 396 /* SCR definitions */ 397 #define SCR_RES1_BITS ((U(1) << 4) | (U(1) << 5)) 398 #define SCR_TWEDEL_SHIFT U(30) 399 #define SCR_TWEDEL_MASK ULL(0xf) 400 #define SCR_TWEDEn_BIT (UL(1) << 29) 401 #define SCR_ECVEN_BIT (UL(1) << 28) 402 #define SCR_FGTEN_BIT (UL(1) << 27) 403 #define SCR_ATA_BIT (UL(1) << 26) 404 #define SCR_FIEN_BIT (UL(1) << 21) 405 #define SCR_EEL2_BIT (UL(1) << 18) 406 #define SCR_API_BIT (UL(1) << 17) 407 #define SCR_APK_BIT (UL(1) << 16) 408 #define SCR_TERR_BIT (UL(1) << 15) 409 #define SCR_TWE_BIT (UL(1) << 13) 410 #define SCR_TWI_BIT (UL(1) << 12) 411 #define SCR_ST_BIT (UL(1) << 11) 412 #define SCR_RW_BIT (UL(1) << 10) 413 #define SCR_SIF_BIT (UL(1) << 9) 414 #define SCR_HCE_BIT (UL(1) << 8) 415 #define SCR_SMD_BIT (UL(1) << 7) 416 #define SCR_EA_BIT (UL(1) << 3) 417 #define SCR_FIQ_BIT (UL(1) << 2) 418 #define SCR_IRQ_BIT (UL(1) << 1) 419 #define SCR_NS_BIT (UL(1) << 0) 420 #define SCR_VALID_BIT_MASK U(0x2f8f) 421 #define SCR_RESET_VAL SCR_RES1_BITS 422 423 /* MDCR_EL3 definitions */ 424 #define MDCR_SCCD_BIT (ULL(1) << 23) 425 #define MDCR_SPME_BIT (ULL(1) << 17) 426 #define MDCR_SDD_BIT (ULL(1) << 16) 427 #define MDCR_SPD32(x) ((x) << 14) 428 #define MDCR_SPD32_LEGACY ULL(0x0) 429 #define MDCR_SPD32_DISABLE ULL(0x2) 430 #define MDCR_SPD32_ENABLE ULL(0x3) 431 #define MDCR_NSPB(x) ((x) << 12) 432 #define MDCR_NSPB_EL1 ULL(0x3) 433 #define MDCR_TDOSA_BIT (ULL(1) << 10) 434 #define MDCR_TDA_BIT (ULL(1) << 9) 435 #define MDCR_TPM_BIT (ULL(1) << 6) 436 #define MDCR_EL3_RESET_VAL ULL(0x0) 437 438 /* MDCR_EL2 definitions */ 439 #define MDCR_EL2_HLP (U(1) << 26) 440 #define MDCR_EL2_HCCD (U(1) << 23) 441 #define MDCR_EL2_TTRF (U(1) << 19) 442 #define MDCR_EL2_HPMD (U(1) << 17) 443 #define MDCR_EL2_TPMS (U(1) << 14) 444 #define MDCR_EL2_E2PB(x) ((x) << 12) 445 #define MDCR_EL2_E2PB_EL1 U(0x3) 446 #define MDCR_EL2_TDRA_BIT (U(1) << 11) 447 #define MDCR_EL2_TDOSA_BIT (U(1) << 10) 448 #define MDCR_EL2_TDA_BIT (U(1) << 9) 449 #define MDCR_EL2_TDE_BIT (U(1) << 8) 450 #define MDCR_EL2_HPME_BIT (U(1) << 7) 451 #define MDCR_EL2_TPM_BIT (U(1) << 6) 452 #define MDCR_EL2_TPMCR_BIT (U(1) << 5) 453 #define MDCR_EL2_RESET_VAL U(0x0) 454 455 /* HSTR_EL2 definitions */ 456 #define HSTR_EL2_RESET_VAL U(0x0) 457 #define HSTR_EL2_T_MASK U(0xff) 458 459 /* CNTHP_CTL_EL2 definitions */ 460 #define CNTHP_CTL_ENABLE_BIT (U(1) << 0) 461 #define CNTHP_CTL_RESET_VAL U(0x0) 462 463 /* VTTBR_EL2 definitions */ 464 #define VTTBR_RESET_VAL ULL(0x0) 465 #define VTTBR_VMID_MASK ULL(0xff) 466 #define VTTBR_VMID_SHIFT U(48) 467 #define VTTBR_BADDR_MASK ULL(0xffffffffffff) 468 #define VTTBR_BADDR_SHIFT U(0) 469 470 /* HCR definitions */ 471 #define HCR_API_BIT (ULL(1) << 41) 472 #define HCR_APK_BIT (ULL(1) << 40) 473 #define HCR_E2H_BIT (ULL(1) << 34) 474 #define HCR_TGE_BIT (ULL(1) << 27) 475 #define HCR_RW_SHIFT U(31) 476 #define HCR_RW_BIT (ULL(1) << HCR_RW_SHIFT) 477 #define HCR_AMO_BIT (ULL(1) << 5) 478 #define HCR_IMO_BIT (ULL(1) << 4) 479 #define HCR_FMO_BIT (ULL(1) << 3) 480 481 /* ISR definitions */ 482 #define ISR_A_SHIFT U(8) 483 #define ISR_I_SHIFT U(7) 484 #define ISR_F_SHIFT U(6) 485 486 /* CNTHCTL_EL2 definitions */ 487 #define CNTHCTL_RESET_VAL U(0x0) 488 #define EVNTEN_BIT (U(1) << 2) 489 #define EL1PCEN_BIT (U(1) << 1) 490 #define EL1PCTEN_BIT (U(1) << 0) 491 492 /* CNTKCTL_EL1 definitions */ 493 #define EL0PTEN_BIT (U(1) << 9) 494 #define EL0VTEN_BIT (U(1) << 8) 495 #define EL0PCTEN_BIT (U(1) << 0) 496 #define EL0VCTEN_BIT (U(1) << 1) 497 #define EVNTEN_BIT (U(1) << 2) 498 #define EVNTDIR_BIT (U(1) << 3) 499 #define EVNTI_SHIFT U(4) 500 #define EVNTI_MASK U(0xf) 501 502 /* CPTR_EL3 definitions */ 503 #define TCPAC_BIT (U(1) << 31) 504 #define TAM_BIT (U(1) << 30) 505 #define TTA_BIT (U(1) << 20) 506 #define TFP_BIT (U(1) << 10) 507 #define CPTR_EZ_BIT (U(1) << 8) 508 #define CPTR_EL3_RESET_VAL U(0x0) 509 510 /* CPTR_EL2 definitions */ 511 #define CPTR_EL2_RES1 ((U(1) << 13) | (U(1) << 12) | (U(0x3ff))) 512 #define CPTR_EL2_TCPAC_BIT (U(1) << 31) 513 #define CPTR_EL2_TAM_BIT (U(1) << 30) 514 #define CPTR_EL2_TTA_BIT (U(1) << 20) 515 #define CPTR_EL2_TFP_BIT (U(1) << 10) 516 #define CPTR_EL2_TZ_BIT (U(1) << 8) 517 #define CPTR_EL2_RESET_VAL CPTR_EL2_RES1 518 519 /* CPSR/SPSR definitions */ 520 #define DAIF_FIQ_BIT (U(1) << 0) 521 #define DAIF_IRQ_BIT (U(1) << 1) 522 #define DAIF_ABT_BIT (U(1) << 2) 523 #define DAIF_DBG_BIT (U(1) << 3) 524 #define SPSR_DAIF_SHIFT U(6) 525 #define SPSR_DAIF_MASK U(0xf) 526 527 #define SPSR_AIF_SHIFT U(6) 528 #define SPSR_AIF_MASK U(0x7) 529 530 #define SPSR_E_SHIFT U(9) 531 #define SPSR_E_MASK U(0x1) 532 #define SPSR_E_LITTLE U(0x0) 533 #define SPSR_E_BIG U(0x1) 534 535 #define SPSR_T_SHIFT U(5) 536 #define SPSR_T_MASK U(0x1) 537 #define SPSR_T_ARM U(0x0) 538 #define SPSR_T_THUMB U(0x1) 539 540 #define SPSR_M_SHIFT U(4) 541 #define SPSR_M_MASK U(0x1) 542 #define SPSR_M_AARCH64 U(0x0) 543 #define SPSR_M_AARCH32 U(0x1) 544 545 #define SPSR_EL_SHIFT U(2) 546 #define SPSR_EL_WIDTH U(2) 547 548 #define SPSR_SSBS_BIT_AARCH64 BIT_64(12) 549 #define SPSR_SSBS_BIT_AARCH32 BIT_64(23) 550 551 #define DISABLE_ALL_EXCEPTIONS \ 552 (DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT | DAIF_DBG_BIT) 553 554 #define DISABLE_INTERRUPTS (DAIF_FIQ_BIT | DAIF_IRQ_BIT) 555 556 /* 557 * RMR_EL3 definitions 558 */ 559 #define RMR_EL3_RR_BIT (U(1) << 1) 560 #define RMR_EL3_AA64_BIT (U(1) << 0) 561 562 /* 563 * HI-VECTOR address for AArch32 state 564 */ 565 #define HI_VECTOR_BASE U(0xFFFF0000) 566 567 /* 568 * TCR defintions 569 */ 570 #define TCR_EL3_RES1 ((ULL(1) << 31) | (ULL(1) << 23)) 571 #define TCR_EL2_RES1 ((ULL(1) << 31) | (ULL(1) << 23)) 572 #define TCR_EL1_IPS_SHIFT U(32) 573 #define TCR_EL2_PS_SHIFT U(16) 574 #define TCR_EL3_PS_SHIFT U(16) 575 576 #define TCR_TxSZ_MIN ULL(16) 577 #define TCR_TxSZ_MAX ULL(39) 578 #define TCR_TxSZ_MAX_TTST ULL(48) 579 580 #define TCR_T0SZ_SHIFT U(0) 581 #define TCR_T1SZ_SHIFT U(16) 582 583 /* (internal) physical address size bits in EL3/EL1 */ 584 #define TCR_PS_BITS_4GB ULL(0x0) 585 #define TCR_PS_BITS_64GB ULL(0x1) 586 #define TCR_PS_BITS_1TB ULL(0x2) 587 #define TCR_PS_BITS_4TB ULL(0x3) 588 #define TCR_PS_BITS_16TB ULL(0x4) 589 #define TCR_PS_BITS_256TB ULL(0x5) 590 591 #define ADDR_MASK_48_TO_63 ULL(0xFFFF000000000000) 592 #define ADDR_MASK_44_TO_47 ULL(0x0000F00000000000) 593 #define ADDR_MASK_42_TO_43 ULL(0x00000C0000000000) 594 #define ADDR_MASK_40_TO_41 ULL(0x0000030000000000) 595 #define ADDR_MASK_36_TO_39 ULL(0x000000F000000000) 596 #define ADDR_MASK_32_TO_35 ULL(0x0000000F00000000) 597 598 #define TCR_RGN_INNER_NC (ULL(0x0) << 8) 599 #define TCR_RGN_INNER_WBA (ULL(0x1) << 8) 600 #define TCR_RGN_INNER_WT (ULL(0x2) << 8) 601 #define TCR_RGN_INNER_WBNA (ULL(0x3) << 8) 602 603 #define TCR_RGN_OUTER_NC (ULL(0x0) << 10) 604 #define TCR_RGN_OUTER_WBA (ULL(0x1) << 10) 605 #define TCR_RGN_OUTER_WT (ULL(0x2) << 10) 606 #define TCR_RGN_OUTER_WBNA (ULL(0x3) << 10) 607 608 #define TCR_SH_NON_SHAREABLE (ULL(0x0) << 12) 609 #define TCR_SH_OUTER_SHAREABLE (ULL(0x2) << 12) 610 #define TCR_SH_INNER_SHAREABLE (ULL(0x3) << 12) 611 612 #define TCR_RGN1_INNER_NC (ULL(0x0) << 24) 613 #define TCR_RGN1_INNER_WBA (ULL(0x1) << 24) 614 #define TCR_RGN1_INNER_WT (ULL(0x2) << 24) 615 #define TCR_RGN1_INNER_WBNA (ULL(0x3) << 24) 616 617 #define TCR_RGN1_OUTER_NC (ULL(0x0) << 26) 618 #define TCR_RGN1_OUTER_WBA (ULL(0x1) << 26) 619 #define TCR_RGN1_OUTER_WT (ULL(0x2) << 26) 620 #define TCR_RGN1_OUTER_WBNA (ULL(0x3) << 26) 621 622 #define TCR_SH1_NON_SHAREABLE (ULL(0x0) << 28) 623 #define TCR_SH1_OUTER_SHAREABLE (ULL(0x2) << 28) 624 #define TCR_SH1_INNER_SHAREABLE (ULL(0x3) << 28) 625 626 #define TCR_TG0_SHIFT U(14) 627 #define TCR_TG0_MASK ULL(3) 628 #define TCR_TG0_4K (ULL(0) << TCR_TG0_SHIFT) 629 #define TCR_TG0_64K (ULL(1) << TCR_TG0_SHIFT) 630 #define TCR_TG0_16K (ULL(2) << TCR_TG0_SHIFT) 631 632 #define TCR_TG1_SHIFT U(30) 633 #define TCR_TG1_MASK ULL(3) 634 #define TCR_TG1_16K (ULL(1) << TCR_TG1_SHIFT) 635 #define TCR_TG1_4K (ULL(2) << TCR_TG1_SHIFT) 636 #define TCR_TG1_64K (ULL(3) << TCR_TG1_SHIFT) 637 638 #define TCR_EPD0_BIT (ULL(1) << 7) 639 #define TCR_EPD1_BIT (ULL(1) << 23) 640 641 #define MODE_SP_SHIFT U(0x0) 642 #define MODE_SP_MASK U(0x1) 643 #define MODE_SP_EL0 U(0x0) 644 #define MODE_SP_ELX U(0x1) 645 646 #define MODE_RW_SHIFT U(0x4) 647 #define MODE_RW_MASK U(0x1) 648 #define MODE_RW_64 U(0x0) 649 #define MODE_RW_32 U(0x1) 650 651 #define MODE_EL_SHIFT U(0x2) 652 #define MODE_EL_MASK U(0x3) 653 #define MODE_EL_WIDTH U(0x2) 654 #define MODE_EL3 U(0x3) 655 #define MODE_EL2 U(0x2) 656 #define MODE_EL1 U(0x1) 657 #define MODE_EL0 U(0x0) 658 659 #define MODE32_SHIFT U(0) 660 #define MODE32_MASK U(0xf) 661 #define MODE32_usr U(0x0) 662 #define MODE32_fiq U(0x1) 663 #define MODE32_irq U(0x2) 664 #define MODE32_svc U(0x3) 665 #define MODE32_mon U(0x6) 666 #define MODE32_abt U(0x7) 667 #define MODE32_hyp U(0xa) 668 #define MODE32_und U(0xb) 669 #define MODE32_sys U(0xf) 670 671 #define GET_RW(mode) (((mode) >> MODE_RW_SHIFT) & MODE_RW_MASK) 672 #define GET_EL(mode) (((mode) >> MODE_EL_SHIFT) & MODE_EL_MASK) 673 #define GET_SP(mode) (((mode) >> MODE_SP_SHIFT) & MODE_SP_MASK) 674 #define GET_M32(mode) (((mode) >> MODE32_SHIFT) & MODE32_MASK) 675 676 #define SPSR_64(el, sp, daif) \ 677 (((MODE_RW_64 << MODE_RW_SHIFT) | \ 678 (((el) & MODE_EL_MASK) << MODE_EL_SHIFT) | \ 679 (((sp) & MODE_SP_MASK) << MODE_SP_SHIFT) | \ 680 (((daif) & SPSR_DAIF_MASK) << SPSR_DAIF_SHIFT)) & \ 681 (~(SPSR_SSBS_BIT_AARCH64))) 682 683 #define SPSR_MODE32(mode, isa, endian, aif) \ 684 (((MODE_RW_32 << MODE_RW_SHIFT) | \ 685 (((mode) & MODE32_MASK) << MODE32_SHIFT) | \ 686 (((isa) & SPSR_T_MASK) << SPSR_T_SHIFT) | \ 687 (((endian) & SPSR_E_MASK) << SPSR_E_SHIFT) | \ 688 (((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT)) & \ 689 (~(SPSR_SSBS_BIT_AARCH32))) 690 691 /* 692 * TTBR Definitions 693 */ 694 #define TTBR_CNP_BIT ULL(0x1) 695 696 /* 697 * CTR_EL0 definitions 698 */ 699 #define CTR_CWG_SHIFT U(24) 700 #define CTR_CWG_MASK U(0xf) 701 #define CTR_ERG_SHIFT U(20) 702 #define CTR_ERG_MASK U(0xf) 703 #define CTR_DMINLINE_SHIFT U(16) 704 #define CTR_DMINLINE_MASK U(0xf) 705 #define CTR_L1IP_SHIFT U(14) 706 #define CTR_L1IP_MASK U(0x3) 707 #define CTR_IMINLINE_SHIFT U(0) 708 #define CTR_IMINLINE_MASK U(0xf) 709 710 #define MAX_CACHE_LINE_SIZE U(0x800) /* 2KB */ 711 712 /* Physical timer control register bit fields shifts and masks */ 713 #define CNTP_CTL_ENABLE_SHIFT U(0) 714 #define CNTP_CTL_IMASK_SHIFT U(1) 715 #define CNTP_CTL_ISTATUS_SHIFT U(2) 716 717 #define CNTP_CTL_ENABLE_MASK U(1) 718 #define CNTP_CTL_IMASK_MASK U(1) 719 #define CNTP_CTL_ISTATUS_MASK U(1) 720 721 /* Physical timer control macros */ 722 #define CNTP_CTL_ENABLE_BIT (U(1) << CNTP_CTL_ENABLE_SHIFT) 723 #define CNTP_CTL_IMASK_BIT (U(1) << CNTP_CTL_IMASK_SHIFT) 724 725 /* Exception Syndrome register bits and bobs */ 726 #define ESR_EC_SHIFT U(26) 727 #define ESR_EC_MASK U(0x3f) 728 #define ESR_EC_LENGTH U(6) 729 #define ESR_ISS_SHIFT U(0) 730 #define ESR_ISS_LENGTH U(25) 731 #define EC_UNKNOWN U(0x0) 732 #define EC_WFE_WFI U(0x1) 733 #define EC_AARCH32_CP15_MRC_MCR U(0x3) 734 #define EC_AARCH32_CP15_MRRC_MCRR U(0x4) 735 #define EC_AARCH32_CP14_MRC_MCR U(0x5) 736 #define EC_AARCH32_CP14_LDC_STC U(0x6) 737 #define EC_FP_SIMD U(0x7) 738 #define EC_AARCH32_CP10_MRC U(0x8) 739 #define EC_AARCH32_CP14_MRRC_MCRR U(0xc) 740 #define EC_ILLEGAL U(0xe) 741 #define EC_AARCH32_SVC U(0x11) 742 #define EC_AARCH32_HVC U(0x12) 743 #define EC_AARCH32_SMC U(0x13) 744 #define EC_AARCH64_SVC U(0x15) 745 #define EC_AARCH64_HVC U(0x16) 746 #define EC_AARCH64_SMC U(0x17) 747 #define EC_AARCH64_SYS U(0x18) 748 #define EC_IABORT_LOWER_EL U(0x20) 749 #define EC_IABORT_CUR_EL U(0x21) 750 #define EC_PC_ALIGN U(0x22) 751 #define EC_DABORT_LOWER_EL U(0x24) 752 #define EC_DABORT_CUR_EL U(0x25) 753 #define EC_SP_ALIGN U(0x26) 754 #define EC_AARCH32_FP U(0x28) 755 #define EC_AARCH64_FP U(0x2c) 756 #define EC_SERROR U(0x2f) 757 #define EC_BRK U(0x3c) 758 759 /* 760 * External Abort bit in Instruction and Data Aborts synchronous exception 761 * syndromes. 762 */ 763 #define ESR_ISS_EABORT_EA_BIT U(9) 764 765 #define EC_BITS(x) (((x) >> ESR_EC_SHIFT) & ESR_EC_MASK) 766 767 /* Reset bit inside the Reset management register for EL3 (RMR_EL3) */ 768 #define RMR_RESET_REQUEST_SHIFT U(0x1) 769 #define RMR_WARM_RESET_CPU (U(1) << RMR_RESET_REQUEST_SHIFT) 770 771 /******************************************************************************* 772 * Definitions of register offsets, fields and macros for CPU system 773 * instructions. 774 ******************************************************************************/ 775 776 #define TLBI_ADDR_SHIFT U(12) 777 #define TLBI_ADDR_MASK ULL(0x00000FFFFFFFFFFF) 778 #define TLBI_ADDR(x) (((x) >> TLBI_ADDR_SHIFT) & TLBI_ADDR_MASK) 779 780 /******************************************************************************* 781 * Definitions of register offsets and fields in the CNTCTLBase Frame of the 782 * system level implementation of the Generic Timer. 783 ******************************************************************************/ 784 #define CNTCTLBASE_CNTFRQ U(0x0) 785 #define CNTNSAR U(0x4) 786 #define CNTNSAR_NS_SHIFT(x) (x) 787 788 #define CNTACR_BASE(x) (U(0x40) + ((x) << 2)) 789 #define CNTACR_RPCT_SHIFT U(0x0) 790 #define CNTACR_RVCT_SHIFT U(0x1) 791 #define CNTACR_RFRQ_SHIFT U(0x2) 792 #define CNTACR_RVOFF_SHIFT U(0x3) 793 #define CNTACR_RWVT_SHIFT U(0x4) 794 #define CNTACR_RWPT_SHIFT U(0x5) 795 796 /******************************************************************************* 797 * Definitions of register offsets and fields in the CNTBaseN Frame of the 798 * system level implementation of the Generic Timer. 799 ******************************************************************************/ 800 /* Physical Count register. */ 801 #define CNTPCT_LO U(0x0) 802 /* Counter Frequency register. */ 803 #define CNTBASEN_CNTFRQ U(0x10) 804 /* Physical Timer CompareValue register. */ 805 #define CNTP_CVAL_LO U(0x20) 806 /* Physical Timer Control register. */ 807 #define CNTP_CTL U(0x2c) 808 809 /* PMCR_EL0 definitions */ 810 #define PMCR_EL0_RESET_VAL U(0x0) 811 #define PMCR_EL0_N_SHIFT U(11) 812 #define PMCR_EL0_N_MASK U(0x1f) 813 #define PMCR_EL0_N_BITS (PMCR_EL0_N_MASK << PMCR_EL0_N_SHIFT) 814 #define PMCR_EL0_LP_BIT (U(1) << 7) 815 #define PMCR_EL0_LC_BIT (U(1) << 6) 816 #define PMCR_EL0_DP_BIT (U(1) << 5) 817 #define PMCR_EL0_X_BIT (U(1) << 4) 818 #define PMCR_EL0_D_BIT (U(1) << 3) 819 #define PMCR_EL0_C_BIT (U(1) << 2) 820 #define PMCR_EL0_P_BIT (U(1) << 1) 821 #define PMCR_EL0_E_BIT (U(1) << 0) 822 823 /******************************************************************************* 824 * Definitions for system register interface to SVE 825 ******************************************************************************/ 826 #define ZCR_EL3 S3_6_C1_C2_0 827 #define ZCR_EL2 S3_4_C1_C2_0 828 829 /* ZCR_EL3 definitions */ 830 #define ZCR_EL3_LEN_MASK U(0xf) 831 832 /* ZCR_EL2 definitions */ 833 #define ZCR_EL2_LEN_MASK U(0xf) 834 835 /******************************************************************************* 836 * Definitions of MAIR encodings for device and normal memory 837 ******************************************************************************/ 838 /* 839 * MAIR encodings for device memory attributes. 840 */ 841 #define MAIR_DEV_nGnRnE ULL(0x0) 842 #define MAIR_DEV_nGnRE ULL(0x4) 843 #define MAIR_DEV_nGRE ULL(0x8) 844 #define MAIR_DEV_GRE ULL(0xc) 845 846 /* 847 * MAIR encodings for normal memory attributes. 848 * 849 * Cache Policy 850 * WT: Write Through 851 * WB: Write Back 852 * NC: Non-Cacheable 853 * 854 * Transient Hint 855 * NTR: Non-Transient 856 * TR: Transient 857 * 858 * Allocation Policy 859 * RA: Read Allocate 860 * WA: Write Allocate 861 * RWA: Read and Write Allocate 862 * NA: No Allocation 863 */ 864 #define MAIR_NORM_WT_TR_WA ULL(0x1) 865 #define MAIR_NORM_WT_TR_RA ULL(0x2) 866 #define MAIR_NORM_WT_TR_RWA ULL(0x3) 867 #define MAIR_NORM_NC ULL(0x4) 868 #define MAIR_NORM_WB_TR_WA ULL(0x5) 869 #define MAIR_NORM_WB_TR_RA ULL(0x6) 870 #define MAIR_NORM_WB_TR_RWA ULL(0x7) 871 #define MAIR_NORM_WT_NTR_NA ULL(0x8) 872 #define MAIR_NORM_WT_NTR_WA ULL(0x9) 873 #define MAIR_NORM_WT_NTR_RA ULL(0xa) 874 #define MAIR_NORM_WT_NTR_RWA ULL(0xb) 875 #define MAIR_NORM_WB_NTR_NA ULL(0xc) 876 #define MAIR_NORM_WB_NTR_WA ULL(0xd) 877 #define MAIR_NORM_WB_NTR_RA ULL(0xe) 878 #define MAIR_NORM_WB_NTR_RWA ULL(0xf) 879 880 #define MAIR_NORM_OUTER_SHIFT U(4) 881 882 #define MAKE_MAIR_NORMAL_MEMORY(inner, outer) \ 883 ((inner) | ((outer) << MAIR_NORM_OUTER_SHIFT)) 884 885 /* PAR_EL1 fields */ 886 #define PAR_F_SHIFT U(0) 887 #define PAR_F_MASK ULL(0x1) 888 #define PAR_ADDR_SHIFT U(12) 889 #define PAR_ADDR_MASK (BIT(40) - ULL(1)) /* 40-bits-wide page address */ 890 891 /******************************************************************************* 892 * Definitions for system register interface to SPE 893 ******************************************************************************/ 894 #define PMBLIMITR_EL1 S3_0_C9_C10_0 895 896 /******************************************************************************* 897 * Definitions for system register interface to MPAM 898 ******************************************************************************/ 899 #define MPAMIDR_EL1 S3_0_C10_C4_4 900 #define MPAM2_EL2 S3_4_C10_C5_0 901 #define MPAMHCR_EL2 S3_4_C10_C4_0 902 #define MPAM3_EL3 S3_6_C10_C5_0 903 904 /******************************************************************************* 905 * Definitions for system register interface to AMU for ARMv8.4 onwards 906 ******************************************************************************/ 907 #define AMCR_EL0 S3_3_C13_C2_0 908 #define AMCFGR_EL0 S3_3_C13_C2_1 909 #define AMCGCR_EL0 S3_3_C13_C2_2 910 #define AMUSERENR_EL0 S3_3_C13_C2_3 911 #define AMCNTENCLR0_EL0 S3_3_C13_C2_4 912 #define AMCNTENSET0_EL0 S3_3_C13_C2_5 913 #define AMCNTENCLR1_EL0 S3_3_C13_C3_0 914 #define AMCNTENSET1_EL0 S3_3_C13_C3_1 915 916 /* Activity Monitor Group 0 Event Counter Registers */ 917 #define AMEVCNTR00_EL0 S3_3_C13_C4_0 918 #define AMEVCNTR01_EL0 S3_3_C13_C4_1 919 #define AMEVCNTR02_EL0 S3_3_C13_C4_2 920 #define AMEVCNTR03_EL0 S3_3_C13_C4_3 921 922 /* Activity Monitor Group 0 Event Type Registers */ 923 #define AMEVTYPER00_EL0 S3_3_C13_C6_0 924 #define AMEVTYPER01_EL0 S3_3_C13_C6_1 925 #define AMEVTYPER02_EL0 S3_3_C13_C6_2 926 #define AMEVTYPER03_EL0 S3_3_C13_C6_3 927 928 /* Activity Monitor Group 1 Event Counter Registers */ 929 #define AMEVCNTR10_EL0 S3_3_C13_C12_0 930 #define AMEVCNTR11_EL0 S3_3_C13_C12_1 931 #define AMEVCNTR12_EL0 S3_3_C13_C12_2 932 #define AMEVCNTR13_EL0 S3_3_C13_C12_3 933 #define AMEVCNTR14_EL0 S3_3_C13_C12_4 934 #define AMEVCNTR15_EL0 S3_3_C13_C12_5 935 #define AMEVCNTR16_EL0 S3_3_C13_C12_6 936 #define AMEVCNTR17_EL0 S3_3_C13_C12_7 937 #define AMEVCNTR18_EL0 S3_3_C13_C13_0 938 #define AMEVCNTR19_EL0 S3_3_C13_C13_1 939 #define AMEVCNTR1A_EL0 S3_3_C13_C13_2 940 #define AMEVCNTR1B_EL0 S3_3_C13_C13_3 941 #define AMEVCNTR1C_EL0 S3_3_C13_C13_4 942 #define AMEVCNTR1D_EL0 S3_3_C13_C13_5 943 #define AMEVCNTR1E_EL0 S3_3_C13_C13_6 944 #define AMEVCNTR1F_EL0 S3_3_C13_C13_7 945 946 /* Activity Monitor Group 1 Event Type Registers */ 947 #define AMEVTYPER10_EL0 S3_3_C13_C14_0 948 #define AMEVTYPER11_EL0 S3_3_C13_C14_1 949 #define AMEVTYPER12_EL0 S3_3_C13_C14_2 950 #define AMEVTYPER13_EL0 S3_3_C13_C14_3 951 #define AMEVTYPER14_EL0 S3_3_C13_C14_4 952 #define AMEVTYPER15_EL0 S3_3_C13_C14_5 953 #define AMEVTYPER16_EL0 S3_3_C13_C14_6 954 #define AMEVTYPER17_EL0 S3_3_C13_C14_7 955 #define AMEVTYPER18_EL0 S3_3_C13_C15_0 956 #define AMEVTYPER19_EL0 S3_3_C13_C15_1 957 #define AMEVTYPER1A_EL0 S3_3_C13_C15_2 958 #define AMEVTYPER1B_EL0 S3_3_C13_C15_3 959 #define AMEVTYPER1C_EL0 S3_3_C13_C15_4 960 #define AMEVTYPER1D_EL0 S3_3_C13_C15_5 961 #define AMEVTYPER1E_EL0 S3_3_C13_C15_6 962 #define AMEVTYPER1F_EL0 S3_3_C13_C15_7 963 964 /* AMCFGR_EL0 definitions */ 965 #define AMCFGR_EL0_NCG_SHIFT U(28) 966 #define AMCFGR_EL0_NCG_MASK U(0xf) 967 #define AMCFGR_EL0_N_SHIFT U(0) 968 #define AMCFGR_EL0_N_MASK U(0xff) 969 970 /* AMCGCR_EL0 definitions */ 971 #define AMCGCR_EL0_CG1NC_SHIFT U(8) 972 #define AMCGCR_EL0_CG1NC_MASK U(0xff) 973 974 /* MPAM register definitions */ 975 #define MPAM3_EL3_MPAMEN_BIT (ULL(1) << 63) 976 #define MPAMHCR_EL2_TRAP_MPAMIDR_EL1 (ULL(1) << 31) 977 978 #define MPAM2_EL2_TRAPMPAM0EL1 (ULL(1) << 49) 979 #define MPAM2_EL2_TRAPMPAM1EL1 (ULL(1) << 48) 980 981 #define MPAMIDR_HAS_HCR_BIT (ULL(1) << 17) 982 983 /******************************************************************************* 984 * RAS system registers 985 ******************************************************************************/ 986 #define DISR_EL1 S3_0_C12_C1_1 987 #define DISR_A_BIT U(31) 988 989 #define ERRIDR_EL1 S3_0_C5_C3_0 990 #define ERRIDR_MASK U(0xffff) 991 992 #define ERRSELR_EL1 S3_0_C5_C3_1 993 994 /* System register access to Standard Error Record registers */ 995 #define ERXFR_EL1 S3_0_C5_C4_0 996 #define ERXCTLR_EL1 S3_0_C5_C4_1 997 #define ERXSTATUS_EL1 S3_0_C5_C4_2 998 #define ERXADDR_EL1 S3_0_C5_C4_3 999 #define ERXPFGF_EL1 S3_0_C5_C4_4 1000 #define ERXPFGCTL_EL1 S3_0_C5_C4_5 1001 #define ERXPFGCDN_EL1 S3_0_C5_C4_6 1002 #define ERXMISC0_EL1 S3_0_C5_C5_0 1003 #define ERXMISC1_EL1 S3_0_C5_C5_1 1004 1005 #define ERXCTLR_ED_BIT (U(1) << 0) 1006 #define ERXCTLR_UE_BIT (U(1) << 4) 1007 1008 #define ERXPFGCTL_UC_BIT (U(1) << 1) 1009 #define ERXPFGCTL_UEU_BIT (U(1) << 2) 1010 #define ERXPFGCTL_CDEN_BIT (U(1) << 31) 1011 1012 /******************************************************************************* 1013 * Armv8.3 Pointer Authentication Registers 1014 ******************************************************************************/ 1015 #define APIAKeyLo_EL1 S3_0_C2_C1_0 1016 #define APIAKeyHi_EL1 S3_0_C2_C1_1 1017 #define APIBKeyLo_EL1 S3_0_C2_C1_2 1018 #define APIBKeyHi_EL1 S3_0_C2_C1_3 1019 #define APDAKeyLo_EL1 S3_0_C2_C2_0 1020 #define APDAKeyHi_EL1 S3_0_C2_C2_1 1021 #define APDBKeyLo_EL1 S3_0_C2_C2_2 1022 #define APDBKeyHi_EL1 S3_0_C2_C2_3 1023 #define APGAKeyLo_EL1 S3_0_C2_C3_0 1024 #define APGAKeyHi_EL1 S3_0_C2_C3_1 1025 1026 /******************************************************************************* 1027 * Armv8.4 Data Independent Timing Registers 1028 ******************************************************************************/ 1029 #define DIT S3_3_C4_C2_5 1030 #define DIT_BIT BIT(24) 1031 1032 /******************************************************************************* 1033 * Armv8.5 - new MSR encoding to directly access PSTATE.SSBS field 1034 ******************************************************************************/ 1035 #define SSBS S3_3_C4_C2_6 1036 1037 /******************************************************************************* 1038 * Armv8.5 - Memory Tagging Extension Registers 1039 ******************************************************************************/ 1040 #define TFSRE0_EL1 S3_0_C5_C6_1 1041 #define TFSR_EL1 S3_0_C5_C6_0 1042 #define RGSR_EL1 S3_0_C1_C0_5 1043 #define GCR_EL1 S3_0_C1_C0_6 1044 1045 /******************************************************************************* 1046 * Definitions for DynamicIQ Shared Unit registers 1047 ******************************************************************************/ 1048 #define CLUSTERPWRDN_EL1 S3_0_c15_c3_6 1049 1050 /* CLUSTERPWRDN_EL1 register definitions */ 1051 #define DSU_CLUSTER_PWR_OFF 0 1052 #define DSU_CLUSTER_PWR_ON 1 1053 #define DSU_CLUSTER_PWR_MASK U(1) 1054 1055 #endif /* ARCH_H */ 1056