1 /* 2 * Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2020-2022, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef ARCH_H 9 #define ARCH_H 10 11 #include <lib/utils_def.h> 12 13 /******************************************************************************* 14 * MIDR bit definitions 15 ******************************************************************************/ 16 #define MIDR_IMPL_MASK U(0xff) 17 #define MIDR_IMPL_SHIFT U(0x18) 18 #define MIDR_VAR_SHIFT U(20) 19 #define MIDR_VAR_BITS U(4) 20 #define MIDR_VAR_MASK U(0xf) 21 #define MIDR_REV_SHIFT U(0) 22 #define MIDR_REV_BITS U(4) 23 #define MIDR_REV_MASK U(0xf) 24 #define MIDR_PN_MASK U(0xfff) 25 #define MIDR_PN_SHIFT U(0x4) 26 27 /******************************************************************************* 28 * MPIDR macros 29 ******************************************************************************/ 30 #define MPIDR_MT_MASK (ULL(1) << 24) 31 #define MPIDR_CPU_MASK MPIDR_AFFLVL_MASK 32 #define MPIDR_CLUSTER_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS) 33 #define MPIDR_AFFINITY_BITS U(8) 34 #define MPIDR_AFFLVL_MASK ULL(0xff) 35 #define MPIDR_AFF0_SHIFT U(0) 36 #define MPIDR_AFF1_SHIFT U(8) 37 #define MPIDR_AFF2_SHIFT U(16) 38 #define MPIDR_AFF3_SHIFT U(32) 39 #define MPIDR_AFF_SHIFT(_n) MPIDR_AFF##_n##_SHIFT 40 #define MPIDR_AFFINITY_MASK ULL(0xff00ffffff) 41 #define MPIDR_AFFLVL_SHIFT U(3) 42 #define MPIDR_AFFLVL0 ULL(0x0) 43 #define MPIDR_AFFLVL1 ULL(0x1) 44 #define MPIDR_AFFLVL2 ULL(0x2) 45 #define MPIDR_AFFLVL3 ULL(0x3) 46 #define MPIDR_AFFLVL(_n) MPIDR_AFFLVL##_n 47 #define MPIDR_AFFLVL0_VAL(mpidr) \ 48 (((mpidr) >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK) 49 #define MPIDR_AFFLVL1_VAL(mpidr) \ 50 (((mpidr) >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK) 51 #define MPIDR_AFFLVL2_VAL(mpidr) \ 52 (((mpidr) >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK) 53 #define MPIDR_AFFLVL3_VAL(mpidr) \ 54 (((mpidr) >> MPIDR_AFF3_SHIFT) & MPIDR_AFFLVL_MASK) 55 /* 56 * The MPIDR_MAX_AFFLVL count starts from 0. Take care to 57 * add one while using this macro to define array sizes. 58 * TODO: Support only the first 3 affinity levels for now. 59 */ 60 #define MPIDR_MAX_AFFLVL U(2) 61 62 #define MPID_MASK (MPIDR_MT_MASK | \ 63 (MPIDR_AFFLVL_MASK << MPIDR_AFF3_SHIFT) | \ 64 (MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT) | \ 65 (MPIDR_AFFLVL_MASK << MPIDR_AFF1_SHIFT) | \ 66 (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT)) 67 68 #define MPIDR_AFF_ID(mpid, n) \ 69 (((mpid) >> MPIDR_AFF_SHIFT(n)) & MPIDR_AFFLVL_MASK) 70 71 /* 72 * An invalid MPID. This value can be used by functions that return an MPID to 73 * indicate an error. 74 */ 75 #define INVALID_MPID U(0xFFFFFFFF) 76 77 /******************************************************************************* 78 * Definitions for Exception vector offsets 79 ******************************************************************************/ 80 #define CURRENT_EL_SP0 0x0 81 #define CURRENT_EL_SPX 0x200 82 #define LOWER_EL_AARCH64 0x400 83 #define LOWER_EL_AARCH32 0x600 84 85 #define SYNC_EXCEPTION 0x0 86 #define IRQ_EXCEPTION 0x80 87 #define FIQ_EXCEPTION 0x100 88 #define SERROR_EXCEPTION 0x180 89 90 /******************************************************************************* 91 * Definitions for CPU system register interface to GICv3 92 ******************************************************************************/ 93 #define ICC_IGRPEN1_EL1 S3_0_C12_C12_7 94 #define ICC_SGI1R S3_0_C12_C11_5 95 #define ICC_ASGI1R S3_0_C12_C11_6 96 #define ICC_SRE_EL1 S3_0_C12_C12_5 97 #define ICC_SRE_EL2 S3_4_C12_C9_5 98 #define ICC_SRE_EL3 S3_6_C12_C12_5 99 #define ICC_CTLR_EL1 S3_0_C12_C12_4 100 #define ICC_CTLR_EL3 S3_6_C12_C12_4 101 #define ICC_PMR_EL1 S3_0_C4_C6_0 102 #define ICC_RPR_EL1 S3_0_C12_C11_3 103 #define ICC_IGRPEN1_EL3 S3_6_c12_c12_7 104 #define ICC_IGRPEN0_EL1 S3_0_c12_c12_6 105 #define ICC_HPPIR0_EL1 S3_0_c12_c8_2 106 #define ICC_HPPIR1_EL1 S3_0_c12_c12_2 107 #define ICC_IAR0_EL1 S3_0_c12_c8_0 108 #define ICC_IAR1_EL1 S3_0_c12_c12_0 109 #define ICC_EOIR0_EL1 S3_0_c12_c8_1 110 #define ICC_EOIR1_EL1 S3_0_c12_c12_1 111 #define ICC_SGI0R_EL1 S3_0_c12_c11_7 112 113 /******************************************************************************* 114 * Definitions for EL2 system registers for save/restore routine 115 ******************************************************************************/ 116 #define CNTPOFF_EL2 S3_4_C14_C0_6 117 #define HAFGRTR_EL2 S3_4_C3_C1_6 118 #define HDFGRTR_EL2 S3_4_C3_C1_4 119 #define HDFGWTR_EL2 S3_4_C3_C1_5 120 #define HFGITR_EL2 S3_4_C1_C1_6 121 #define HFGRTR_EL2 S3_4_C1_C1_4 122 #define HFGWTR_EL2 S3_4_C1_C1_5 123 #define ICH_HCR_EL2 S3_4_C12_C11_0 124 #define ICH_VMCR_EL2 S3_4_C12_C11_7 125 #define MPAMVPM0_EL2 S3_4_C10_C6_0 126 #define MPAMVPM1_EL2 S3_4_C10_C6_1 127 #define MPAMVPM2_EL2 S3_4_C10_C6_2 128 #define MPAMVPM3_EL2 S3_4_C10_C6_3 129 #define MPAMVPM4_EL2 S3_4_C10_C6_4 130 #define MPAMVPM5_EL2 S3_4_C10_C6_5 131 #define MPAMVPM6_EL2 S3_4_C10_C6_6 132 #define MPAMVPM7_EL2 S3_4_C10_C6_7 133 #define MPAMVPMV_EL2 S3_4_C10_C4_1 134 #define TRFCR_EL2 S3_4_C1_C2_1 135 #define VNCR_EL2 S3_4_C2_C2_0 136 #define PMSCR_EL2 S3_4_C9_C9_0 137 #define TFSR_EL2 S3_4_C5_C6_0 138 #define CONTEXTIDR_EL2 S3_4_C13_C0_1 139 #define TTBR1_EL2 S3_4_C2_C0_1 140 141 /******************************************************************************* 142 * Generic timer memory mapped registers & offsets 143 ******************************************************************************/ 144 #define CNTCR_OFF U(0x000) 145 #define CNTCV_OFF U(0x008) 146 #define CNTFID_OFF U(0x020) 147 148 #define CNTCR_EN (U(1) << 0) 149 #define CNTCR_HDBG (U(1) << 1) 150 #define CNTCR_FCREQ(x) ((x) << 8) 151 152 /******************************************************************************* 153 * System register bit definitions 154 ******************************************************************************/ 155 /* CLIDR definitions */ 156 #define LOUIS_SHIFT U(21) 157 #define LOC_SHIFT U(24) 158 #define CTYPE_SHIFT(n) U(3 * (n - 1)) 159 #define CLIDR_FIELD_WIDTH U(3) 160 161 /* CSSELR definitions */ 162 #define LEVEL_SHIFT U(1) 163 164 /* Data cache set/way op type defines */ 165 #define DCISW U(0x0) 166 #define DCCISW U(0x1) 167 #if ERRATA_A53_827319 168 #define DCCSW DCCISW 169 #else 170 #define DCCSW U(0x2) 171 #endif 172 173 #define ID_REG_FIELD_MASK ULL(0xf) 174 175 /* ID_AA64PFR0_EL1 definitions */ 176 #define ID_AA64PFR0_EL0_SHIFT U(0) 177 #define ID_AA64PFR0_EL1_SHIFT U(4) 178 #define ID_AA64PFR0_EL2_SHIFT U(8) 179 #define ID_AA64PFR0_EL3_SHIFT U(12) 180 181 #define ID_AA64PFR0_AMU_SHIFT U(44) 182 #define ID_AA64PFR0_AMU_MASK ULL(0xf) 183 #define ID_AA64PFR0_AMU_NOT_SUPPORTED U(0x0) 184 #define ID_AA64PFR0_AMU_V1 ULL(0x1) 185 #define ID_AA64PFR0_AMU_V1P1 U(0x2) 186 187 #define ID_AA64PFR0_ELX_MASK ULL(0xf) 188 189 #define ID_AA64PFR0_GIC_SHIFT U(24) 190 #define ID_AA64PFR0_GIC_WIDTH U(4) 191 #define ID_AA64PFR0_GIC_MASK ULL(0xf) 192 193 #define ID_AA64PFR0_SVE_SHIFT U(32) 194 #define ID_AA64PFR0_SVE_MASK ULL(0xf) 195 #define ID_AA64PFR0_SVE_SUPPORTED ULL(0x1) 196 #define ID_AA64PFR0_SVE_LENGTH U(4) 197 198 #define ID_AA64PFR0_SEL2_SHIFT U(36) 199 #define ID_AA64PFR0_SEL2_MASK ULL(0xf) 200 201 #define ID_AA64PFR0_MPAM_SHIFT U(40) 202 #define ID_AA64PFR0_MPAM_MASK ULL(0xf) 203 204 #define ID_AA64PFR0_DIT_SHIFT U(48) 205 #define ID_AA64PFR0_DIT_MASK ULL(0xf) 206 #define ID_AA64PFR0_DIT_LENGTH U(4) 207 #define ID_AA64PFR0_DIT_SUPPORTED U(1) 208 209 #define ID_AA64PFR0_CSV2_SHIFT U(56) 210 #define ID_AA64PFR0_CSV2_MASK ULL(0xf) 211 #define ID_AA64PFR0_CSV2_LENGTH U(4) 212 #define ID_AA64PFR0_CSV2_2_SUPPORTED ULL(0x2) 213 #define ID_AA64PFR0_CSV2_3_SUPPORTED ULL(0x3) 214 215 #define ID_AA64PFR0_FEAT_RME_SHIFT U(52) 216 #define ID_AA64PFR0_FEAT_RME_MASK ULL(0xf) 217 #define ID_AA64PFR0_FEAT_RME_LENGTH U(4) 218 #define ID_AA64PFR0_FEAT_RME_NOT_SUPPORTED U(0) 219 #define ID_AA64PFR0_FEAT_RME_V1 U(1) 220 221 #define ID_AA64PFR0_RAS_SHIFT U(28) 222 #define ID_AA64PFR0_RAS_MASK ULL(0xf) 223 #define ID_AA64PFR0_RAS_NOT_SUPPORTED ULL(0x0) 224 #define ID_AA64PFR0_RAS_LENGTH U(4) 225 226 /* Exception level handling */ 227 #define EL_IMPL_NONE ULL(0) 228 #define EL_IMPL_A64ONLY ULL(1) 229 #define EL_IMPL_A64_A32 ULL(2) 230 231 /* ID_AA64DFR0_EL1.TraceVer definitions */ 232 #define ID_AA64DFR0_TRACEVER_SHIFT U(4) 233 #define ID_AA64DFR0_TRACEVER_MASK ULL(0xf) 234 #define ID_AA64DFR0_TRACEVER_SUPPORTED ULL(1) 235 #define ID_AA64DFR0_TRACEVER_LENGTH U(4) 236 #define ID_AA64DFR0_TRACEFILT_SHIFT U(40) 237 #define ID_AA64DFR0_TRACEFILT_MASK U(0xf) 238 #define ID_AA64DFR0_TRACEFILT_SUPPORTED U(1) 239 #define ID_AA64DFR0_TRACEFILT_LENGTH U(4) 240 #define ID_AA64DFR0_PMUVER_LENGTH U(4) 241 #define ID_AA64DFR0_PMUVER_SHIFT U(8) 242 #define ID_AA64DFR0_PMUVER_MASK U(0xf) 243 #define ID_AA64DFR0_PMUVER_PMUV3 U(1) 244 #define ID_AA64DFR0_PMUVER_PMUV3P7 U(7) 245 #define ID_AA64DFR0_PMUVER_IMP_DEF U(0xf) 246 247 /* ID_AA64DFR0_EL1.SEBEP definitions */ 248 #define ID_AA64DFR0_SEBEP_SHIFT U(24) 249 #define ID_AA64DFR0_SEBEP_MASK ULL(0xf) 250 #define SEBEP_IMPLEMENTED ULL(1) 251 252 /* ID_AA64DFR0_EL1.PMS definitions (for ARMv8.2+) */ 253 #define ID_AA64DFR0_PMS_SHIFT U(32) 254 #define ID_AA64DFR0_PMS_MASK ULL(0xf) 255 #define ID_AA64DFR0_SPE_SUPPORTED ULL(0x1) 256 #define ID_AA64DFR0_SPE_NOT_SUPPORTED ULL(0x0) 257 258 /* ID_AA64DFR0_EL1.TraceBuffer definitions */ 259 #define ID_AA64DFR0_TRACEBUFFER_SHIFT U(44) 260 #define ID_AA64DFR0_TRACEBUFFER_MASK ULL(0xf) 261 #define ID_AA64DFR0_TRACEBUFFER_SUPPORTED ULL(1) 262 263 /* ID_AA64DFR0_EL1.MTPMU definitions (for ARMv8.6+) */ 264 #define ID_AA64DFR0_MTPMU_SHIFT U(48) 265 #define ID_AA64DFR0_MTPMU_MASK ULL(0xf) 266 #define ID_AA64DFR0_MTPMU_SUPPORTED ULL(1) 267 #define ID_AA64DFR0_MTPMU_DISABLED ULL(15) 268 269 /* ID_AA64DFR0_EL1.BRBE definitions */ 270 #define ID_AA64DFR0_BRBE_SHIFT U(52) 271 #define ID_AA64DFR0_BRBE_MASK ULL(0xf) 272 #define ID_AA64DFR0_BRBE_SUPPORTED ULL(1) 273 274 /* ID_AA64DFR1_EL1 definitions */ 275 #define ID_AA64DFR1_EBEP_SHIFT U(48) 276 #define ID_AA64DFR1_EBEP_MASK ULL(0xf) 277 #define EBEP_IMPLEMENTED ULL(1) 278 279 /* ID_AA64ISAR0_EL1 definitions */ 280 #define ID_AA64ISAR0_RNDR_SHIFT U(60) 281 #define ID_AA64ISAR0_RNDR_MASK ULL(0xf) 282 283 /* ID_AA64ISAR1_EL1 definitions */ 284 #define ID_AA64ISAR1_EL1 S3_0_C0_C6_1 285 286 #define ID_AA64ISAR1_GPI_SHIFT U(28) 287 #define ID_AA64ISAR1_GPI_MASK ULL(0xf) 288 #define ID_AA64ISAR1_GPA_SHIFT U(24) 289 #define ID_AA64ISAR1_GPA_MASK ULL(0xf) 290 291 #define ID_AA64ISAR1_API_SHIFT U(8) 292 #define ID_AA64ISAR1_API_MASK ULL(0xf) 293 #define ID_AA64ISAR1_APA_SHIFT U(4) 294 #define ID_AA64ISAR1_APA_MASK ULL(0xf) 295 296 #define ID_AA64ISAR1_SB_SHIFT U(36) 297 #define ID_AA64ISAR1_SB_MASK ULL(0xf) 298 #define ID_AA64ISAR1_SB_SUPPORTED ULL(0x1) 299 #define ID_AA64ISAR1_SB_NOT_SUPPORTED ULL(0x0) 300 301 /* ID_AA64ISAR2_EL1 definitions */ 302 #define ID_AA64ISAR2_EL1 S3_0_C0_C6_2 303 304 /* ID_AA64PFR2_EL1 definitions */ 305 #define ID_AA64PFR2_EL1 S3_0_C0_C4_2 306 307 #define ID_AA64ISAR2_GPA3_SHIFT U(8) 308 #define ID_AA64ISAR2_GPA3_MASK ULL(0xf) 309 310 #define ID_AA64ISAR2_APA3_SHIFT U(12) 311 #define ID_AA64ISAR2_APA3_MASK ULL(0xf) 312 313 /* ID_AA64MMFR0_EL1 definitions */ 314 #define ID_AA64MMFR0_EL1_PARANGE_SHIFT U(0) 315 #define ID_AA64MMFR0_EL1_PARANGE_MASK ULL(0xf) 316 317 #define PARANGE_0000 U(32) 318 #define PARANGE_0001 U(36) 319 #define PARANGE_0010 U(40) 320 #define PARANGE_0011 U(42) 321 #define PARANGE_0100 U(44) 322 #define PARANGE_0101 U(48) 323 #define PARANGE_0110 U(52) 324 325 #define ID_AA64MMFR0_EL1_ECV_SHIFT U(60) 326 #define ID_AA64MMFR0_EL1_ECV_MASK ULL(0xf) 327 #define ID_AA64MMFR0_EL1_ECV_NOT_SUPPORTED ULL(0x0) 328 #define ID_AA64MMFR0_EL1_ECV_SUPPORTED ULL(0x1) 329 #define ID_AA64MMFR0_EL1_ECV_SELF_SYNCH ULL(0x2) 330 331 #define ID_AA64MMFR0_EL1_FGT_SHIFT U(56) 332 #define ID_AA64MMFR0_EL1_FGT_MASK ULL(0xf) 333 #define ID_AA64MMFR0_EL1_FGT_SUPPORTED ULL(0x1) 334 #define ID_AA64MMFR0_EL1_FGT_NOT_SUPPORTED ULL(0x0) 335 336 #define ID_AA64MMFR0_EL1_TGRAN4_SHIFT U(28) 337 #define ID_AA64MMFR0_EL1_TGRAN4_MASK ULL(0xf) 338 #define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED ULL(0x0) 339 #define ID_AA64MMFR0_EL1_TGRAN4_52B_SUPPORTED ULL(0x1) 340 #define ID_AA64MMFR0_EL1_TGRAN4_NOT_SUPPORTED ULL(0xf) 341 342 #define ID_AA64MMFR0_EL1_TGRAN64_SHIFT U(24) 343 #define ID_AA64MMFR0_EL1_TGRAN64_MASK ULL(0xf) 344 #define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED ULL(0x0) 345 #define ID_AA64MMFR0_EL1_TGRAN64_NOT_SUPPORTED ULL(0xf) 346 347 #define ID_AA64MMFR0_EL1_TGRAN16_SHIFT U(20) 348 #define ID_AA64MMFR0_EL1_TGRAN16_MASK ULL(0xf) 349 #define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED ULL(0x1) 350 #define ID_AA64MMFR0_EL1_TGRAN16_NOT_SUPPORTED ULL(0x0) 351 #define ID_AA64MMFR0_EL1_TGRAN16_52B_SUPPORTED ULL(0x2) 352 353 /* ID_AA64MMFR1_EL1 definitions */ 354 #define ID_AA64MMFR1_EL1_TWED_SHIFT U(32) 355 #define ID_AA64MMFR1_EL1_TWED_MASK ULL(0xf) 356 #define ID_AA64MMFR1_EL1_TWED_SUPPORTED ULL(0x1) 357 #define ID_AA64MMFR1_EL1_TWED_NOT_SUPPORTED ULL(0x0) 358 359 #define ID_AA64MMFR1_EL1_PAN_SHIFT U(20) 360 #define ID_AA64MMFR1_EL1_PAN_MASK ULL(0xf) 361 #define ID_AA64MMFR1_EL1_PAN_NOT_SUPPORTED ULL(0x0) 362 #define ID_AA64MMFR1_EL1_PAN_SUPPORTED ULL(0x1) 363 #define ID_AA64MMFR1_EL1_PAN2_SUPPORTED ULL(0x2) 364 #define ID_AA64MMFR1_EL1_PAN3_SUPPORTED ULL(0x3) 365 366 #define ID_AA64MMFR1_EL1_VHE_SHIFT U(8) 367 #define ID_AA64MMFR1_EL1_VHE_MASK ULL(0xf) 368 369 #define ID_AA64MMFR1_EL1_HCX_SHIFT U(40) 370 #define ID_AA64MMFR1_EL1_HCX_MASK ULL(0xf) 371 #define ID_AA64MMFR1_EL1_HCX_SUPPORTED ULL(0x1) 372 #define ID_AA64MMFR1_EL1_HCX_NOT_SUPPORTED ULL(0x0) 373 374 /* ID_AA64MMFR2_EL1 definitions */ 375 #define ID_AA64MMFR2_EL1 S3_0_C0_C7_2 376 377 #define ID_AA64MMFR2_EL1_ST_SHIFT U(28) 378 #define ID_AA64MMFR2_EL1_ST_MASK ULL(0xf) 379 380 #define ID_AA64MMFR2_EL1_CCIDX_SHIFT U(20) 381 #define ID_AA64MMFR2_EL1_CCIDX_MASK ULL(0xf) 382 #define ID_AA64MMFR2_EL1_CCIDX_LENGTH U(4) 383 384 #define ID_AA64MMFR2_EL1_UAO_SHIFT U(4) 385 #define ID_AA64MMFR2_EL1_UAO_MASK ULL(0xf) 386 387 #define ID_AA64MMFR2_EL1_CNP_SHIFT U(0) 388 #define ID_AA64MMFR2_EL1_CNP_MASK ULL(0xf) 389 390 #define ID_AA64MMFR2_EL1_NV_SHIFT U(24) 391 #define ID_AA64MMFR2_EL1_NV_MASK ULL(0xf) 392 #define ID_AA64MMFR2_EL1_NV_NOT_SUPPORTED ULL(0x0) 393 #define ID_AA64MMFR2_EL1_NV_SUPPORTED ULL(0x1) 394 #define ID_AA64MMFR2_EL1_NV2_SUPPORTED ULL(0x2) 395 396 /* ID_AA64MMFR3_EL1 definitions */ 397 #define ID_AA64MMFR3_EL1 S3_0_C0_C7_3 398 399 #define ID_AA64MMFR3_EL1_S2POE_SHIFT U(20) 400 #define ID_AA64MMFR3_EL1_S2POE_MASK ULL(0xf) 401 402 #define ID_AA64MMFR3_EL1_S1POE_SHIFT U(16) 403 #define ID_AA64MMFR3_EL1_S1POE_MASK ULL(0xf) 404 405 #define ID_AA64MMFR3_EL1_S2PIE_SHIFT U(12) 406 #define ID_AA64MMFR3_EL1_S2PIE_MASK ULL(0xf) 407 408 #define ID_AA64MMFR3_EL1_S1PIE_SHIFT U(8) 409 #define ID_AA64MMFR3_EL1_S1PIE_MASK ULL(0xf) 410 411 #define ID_AA64MMFR3_EL1_TCRX_SHIFT U(0) 412 #define ID_AA64MMFR3_EL1_TCRX_MASK ULL(0xf) 413 414 /* ID_AA64PFR1_EL1 definitions */ 415 416 #define ID_AA64PFR1_EL1_BT_SHIFT U(0) 417 #define ID_AA64PFR1_EL1_BT_MASK ULL(0xf) 418 #define BTI_IMPLEMENTED ULL(1) /* The BTI mechanism is implemented */ 419 420 #define ID_AA64PFR1_EL1_SSBS_SHIFT U(4) 421 #define ID_AA64PFR1_EL1_SSBS_MASK ULL(0xf) 422 #define SSBS_UNAVAILABLE ULL(0) /* No architectural SSBS support */ 423 424 #define ID_AA64PFR1_EL1_MTE_SHIFT U(8) 425 #define ID_AA64PFR1_EL1_MTE_MASK ULL(0xf) 426 427 #define ID_AA64PFR1_EL1_RNDR_TRAP_SHIFT U(28) 428 #define ID_AA64PFR1_EL1_RNDR_TRAP_MASK U(0xf) 429 430 #define ID_AA64PFR1_EL1_NMI_SHIFT U(36) 431 #define ID_AA64PFR1_EL1_NMI_MASK ULL(0xf) 432 #define NMI_IMPLEMENTED ULL(1) 433 434 #define ID_AA64PFR1_EL1_GCS_SHIFT U(44) 435 #define ID_AA64PFR1_EL1_GCS_MASK ULL(0xf) 436 #define GCS_IMPLEMENTED ULL(1) 437 438 #define ID_AA64PFR1_EL1_RNG_TRAP_SUPPORTED ULL(0x1) 439 #define ID_AA64PFR1_EL1_RNG_TRAP_NOT_SUPPORTED ULL(0x0) 440 441 /* ID_AA64PFR2_EL1 definitions */ 442 #define ID_AA64PFR2_EL1_MTEPERM_SHIFT U(0) 443 #define ID_AA64PFR2_EL1_MTEPERM_MASK ULL(0xf) 444 445 #define ID_AA64PFR2_EL1_MTESTOREONLY_SHIFT U(4) 446 #define ID_AA64PFR2_EL1_MTESTOREONLY_MASK ULL(0xf) 447 448 #define ID_AA64PFR2_EL1_MTEFAR_SHIFT U(8) 449 #define ID_AA64PFR2_EL1_MTEFAR_MASK ULL(0xf) 450 451 #define VDISR_EL2 S3_4_C12_C1_1 452 #define VSESR_EL2 S3_4_C5_C2_3 453 454 /* Memory Tagging Extension is not implemented */ 455 #define MTE_UNIMPLEMENTED U(0) 456 /* FEAT_MTE: MTE instructions accessible at EL0 are implemented */ 457 #define MTE_IMPLEMENTED_EL0 U(1) 458 /* FEAT_MTE2: Full MTE is implemented */ 459 #define MTE_IMPLEMENTED_ELX U(2) 460 /* 461 * FEAT_MTE3: MTE is implemented with support for 462 * asymmetric Tag Check Fault handling 463 */ 464 #define MTE_IMPLEMENTED_ASY U(3) 465 466 #define ID_AA64PFR1_MPAM_FRAC_SHIFT ULL(16) 467 #define ID_AA64PFR1_MPAM_FRAC_MASK ULL(0xf) 468 469 #define ID_AA64PFR1_EL1_SME_SHIFT U(24) 470 #define ID_AA64PFR1_EL1_SME_MASK ULL(0xf) 471 #define ID_AA64PFR1_EL1_SME_WIDTH U(4) 472 #define ID_AA64PFR1_EL1_SME_NOT_SUPPORTED ULL(0x0) 473 #define ID_AA64PFR1_EL1_SME_SUPPORTED ULL(0x1) 474 #define ID_AA64PFR1_EL1_SME2_SUPPORTED ULL(0x2) 475 476 /* ID_PFR1_EL1 definitions */ 477 #define ID_PFR1_VIRTEXT_SHIFT U(12) 478 #define ID_PFR1_VIRTEXT_MASK U(0xf) 479 #define GET_VIRT_EXT(id) (((id) >> ID_PFR1_VIRTEXT_SHIFT) \ 480 & ID_PFR1_VIRTEXT_MASK) 481 482 /* SCTLR definitions */ 483 #define SCTLR_EL2_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ 484 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \ 485 (U(1) << 11) | (U(1) << 5) | (U(1) << 4)) 486 487 #define SCTLR_EL1_RES1 ((UL(1) << 29) | (UL(1) << 28) | (UL(1) << 23) | \ 488 (UL(1) << 22) | (UL(1) << 20) | (UL(1) << 11)) 489 490 #define SCTLR_AARCH32_EL1_RES1 \ 491 ((U(1) << 23) | (U(1) << 22) | (U(1) << 11) | \ 492 (U(1) << 4) | (U(1) << 3)) 493 494 #define SCTLR_EL3_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ 495 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \ 496 (U(1) << 11) | (U(1) << 5) | (U(1) << 4)) 497 498 #define SCTLR_M_BIT (ULL(1) << 0) 499 #define SCTLR_A_BIT (ULL(1) << 1) 500 #define SCTLR_C_BIT (ULL(1) << 2) 501 #define SCTLR_SA_BIT (ULL(1) << 3) 502 #define SCTLR_SA0_BIT (ULL(1) << 4) 503 #define SCTLR_CP15BEN_BIT (ULL(1) << 5) 504 #define SCTLR_nAA_BIT (ULL(1) << 6) 505 #define SCTLR_ITD_BIT (ULL(1) << 7) 506 #define SCTLR_SED_BIT (ULL(1) << 8) 507 #define SCTLR_UMA_BIT (ULL(1) << 9) 508 #define SCTLR_EnRCTX_BIT (ULL(1) << 10) 509 #define SCTLR_EOS_BIT (ULL(1) << 11) 510 #define SCTLR_I_BIT (ULL(1) << 12) 511 #define SCTLR_EnDB_BIT (ULL(1) << 13) 512 #define SCTLR_DZE_BIT (ULL(1) << 14) 513 #define SCTLR_UCT_BIT (ULL(1) << 15) 514 #define SCTLR_NTWI_BIT (ULL(1) << 16) 515 #define SCTLR_NTWE_BIT (ULL(1) << 18) 516 #define SCTLR_WXN_BIT (ULL(1) << 19) 517 #define SCTLR_TSCXT_BIT (ULL(1) << 20) 518 #define SCTLR_IESB_BIT (ULL(1) << 21) 519 #define SCTLR_EIS_BIT (ULL(1) << 22) 520 #define SCTLR_SPAN_BIT (ULL(1) << 23) 521 #define SCTLR_E0E_BIT (ULL(1) << 24) 522 #define SCTLR_EE_BIT (ULL(1) << 25) 523 #define SCTLR_UCI_BIT (ULL(1) << 26) 524 #define SCTLR_EnDA_BIT (ULL(1) << 27) 525 #define SCTLR_nTLSMD_BIT (ULL(1) << 28) 526 #define SCTLR_LSMAOE_BIT (ULL(1) << 29) 527 #define SCTLR_EnIB_BIT (ULL(1) << 30) 528 #define SCTLR_EnIA_BIT (ULL(1) << 31) 529 #define SCTLR_BT0_BIT (ULL(1) << 35) 530 #define SCTLR_BT1_BIT (ULL(1) << 36) 531 #define SCTLR_BT_BIT (ULL(1) << 36) 532 #define SCTLR_ITFSB_BIT (ULL(1) << 37) 533 #define SCTLR_TCF0_SHIFT U(38) 534 #define SCTLR_TCF0_MASK ULL(3) 535 #define SCTLR_ENTP2_BIT (ULL(1) << 60) 536 #define SCTLR_SPINTMASK_BIT (ULL(1) << 62) 537 538 /* Tag Check Faults in EL0 have no effect on the PE */ 539 #define SCTLR_TCF0_NO_EFFECT U(0) 540 /* Tag Check Faults in EL0 cause a synchronous exception */ 541 #define SCTLR_TCF0_SYNC U(1) 542 /* Tag Check Faults in EL0 are asynchronously accumulated */ 543 #define SCTLR_TCF0_ASYNC U(2) 544 /* 545 * Tag Check Faults in EL0 cause a synchronous exception on reads, 546 * and are asynchronously accumulated on writes 547 */ 548 #define SCTLR_TCF0_SYNCR_ASYNCW U(3) 549 550 #define SCTLR_TCF_SHIFT U(40) 551 #define SCTLR_TCF_MASK ULL(3) 552 553 /* Tag Check Faults in EL1 have no effect on the PE */ 554 #define SCTLR_TCF_NO_EFFECT U(0) 555 /* Tag Check Faults in EL1 cause a synchronous exception */ 556 #define SCTLR_TCF_SYNC U(1) 557 /* Tag Check Faults in EL1 are asynchronously accumulated */ 558 #define SCTLR_TCF_ASYNC U(2) 559 /* 560 * Tag Check Faults in EL1 cause a synchronous exception on reads, 561 * and are asynchronously accumulated on writes 562 */ 563 #define SCTLR_TCF_SYNCR_ASYNCW U(3) 564 565 #define SCTLR_ATA0_BIT (ULL(1) << 42) 566 #define SCTLR_ATA_BIT (ULL(1) << 43) 567 #define SCTLR_DSSBS_SHIFT U(44) 568 #define SCTLR_DSSBS_BIT (ULL(1) << SCTLR_DSSBS_SHIFT) 569 #define SCTLR_TWEDEn_BIT (ULL(1) << 45) 570 #define SCTLR_TWEDEL_SHIFT U(46) 571 #define SCTLR_TWEDEL_MASK ULL(0xf) 572 #define SCTLR_EnASR_BIT (ULL(1) << 54) 573 #define SCTLR_EnAS0_BIT (ULL(1) << 55) 574 #define SCTLR_EnALS_BIT (ULL(1) << 56) 575 #define SCTLR_EPAN_BIT (ULL(1) << 57) 576 #define SCTLR_RESET_VAL SCTLR_EL3_RES1 577 578 /* CPACR_EL1 definitions */ 579 #define CPACR_EL1_FPEN(x) ((x) << 20) 580 #define CPACR_EL1_FP_TRAP_EL0 UL(0x1) 581 #define CPACR_EL1_FP_TRAP_ALL UL(0x2) 582 #define CPACR_EL1_FP_TRAP_NONE UL(0x3) 583 #define CPACR_EL1_SMEN_SHIFT U(24) 584 #define CPACR_EL1_SMEN_MASK ULL(0x3) 585 586 /* SCR definitions */ 587 #define SCR_RES1_BITS ((U(1) << 4) | (U(1) << 5)) 588 #define SCR_NSE_SHIFT U(62) 589 #define SCR_NSE_BIT (ULL(1) << SCR_NSE_SHIFT) 590 #define SCR_GPF_BIT (UL(1) << 48) 591 #define SCR_TWEDEL_SHIFT U(30) 592 #define SCR_TWEDEL_MASK ULL(0xf) 593 #define SCR_PIEN_BIT (UL(1) << 45) 594 #define SCR_TCR2EN_BIT (UL(1) << 43) 595 #define SCR_TRNDR_BIT (UL(1) << 40) 596 #define SCR_GCSEn_BIT (UL(1) << 39) 597 #define SCR_HXEn_BIT (UL(1) << 38) 598 #define SCR_ENTP2_SHIFT U(41) 599 #define SCR_ENTP2_BIT (UL(1) << SCR_ENTP2_SHIFT) 600 #define SCR_AMVOFFEN_SHIFT U(35) 601 #define SCR_AMVOFFEN_BIT (UL(1) << SCR_AMVOFFEN_SHIFT) 602 #define SCR_TWEDEn_BIT (UL(1) << 29) 603 #define SCR_ECVEN_BIT (UL(1) << 28) 604 #define SCR_FGTEN_BIT (UL(1) << 27) 605 #define SCR_ATA_BIT (UL(1) << 26) 606 #define SCR_EnSCXT_BIT (UL(1) << 25) 607 #define SCR_FIEN_BIT (UL(1) << 21) 608 #define SCR_EEL2_BIT (UL(1) << 18) 609 #define SCR_API_BIT (UL(1) << 17) 610 #define SCR_APK_BIT (UL(1) << 16) 611 #define SCR_TERR_BIT (UL(1) << 15) 612 #define SCR_TWE_BIT (UL(1) << 13) 613 #define SCR_TWI_BIT (UL(1) << 12) 614 #define SCR_ST_BIT (UL(1) << 11) 615 #define SCR_RW_BIT (UL(1) << 10) 616 #define SCR_SIF_BIT (UL(1) << 9) 617 #define SCR_HCE_BIT (UL(1) << 8) 618 #define SCR_SMD_BIT (UL(1) << 7) 619 #define SCR_EA_BIT (UL(1) << 3) 620 #define SCR_FIQ_BIT (UL(1) << 2) 621 #define SCR_IRQ_BIT (UL(1) << 1) 622 #define SCR_NS_BIT (UL(1) << 0) 623 #define SCR_VALID_BIT_MASK U(0x24000002F8F) 624 #define SCR_RESET_VAL SCR_RES1_BITS 625 626 /* MDCR_EL3 definitions */ 627 #define MDCR_EnPMSN_BIT (ULL(1) << 36) 628 #define MDCR_MPMX_BIT (ULL(1) << 35) 629 #define MDCR_MCCD_BIT (ULL(1) << 34) 630 #define MDCR_SBRBE_SHIFT U(32) 631 #define MDCR_SBRBE_MASK ULL(0x3) 632 #define MDCR_NSTB(x) ((x) << 24) 633 #define MDCR_NSTB_EL1 ULL(0x3) 634 #define MDCR_NSTBE_BIT (ULL(1) << 26) 635 #define MDCR_MTPME_BIT (ULL(1) << 28) 636 #define MDCR_TDCC_BIT (ULL(1) << 27) 637 #define MDCR_SCCD_BIT (ULL(1) << 23) 638 #define MDCR_EPMAD_BIT (ULL(1) << 21) 639 #define MDCR_EDAD_BIT (ULL(1) << 20) 640 #define MDCR_TTRF_BIT (ULL(1) << 19) 641 #define MDCR_STE_BIT (ULL(1) << 18) 642 #define MDCR_SPME_BIT (ULL(1) << 17) 643 #define MDCR_SDD_BIT (ULL(1) << 16) 644 #define MDCR_SPD32(x) ((x) << 14) 645 #define MDCR_SPD32_LEGACY ULL(0x0) 646 #define MDCR_SPD32_DISABLE ULL(0x2) 647 #define MDCR_SPD32_ENABLE ULL(0x3) 648 #define MDCR_NSPB(x) ((x) << 12) 649 #define MDCR_NSPB_EL1 ULL(0x3) 650 #define MDCR_NSPBE_BIT (ULL(1) << 11) 651 #define MDCR_TDOSA_BIT (ULL(1) << 10) 652 #define MDCR_TDA_BIT (ULL(1) << 9) 653 #define MDCR_TPM_BIT (ULL(1) << 6) 654 #define MDCR_EL3_RESET_VAL MDCR_MTPME_BIT 655 656 /* MDCR_EL2 definitions */ 657 #define MDCR_EL2_MTPME (U(1) << 28) 658 #define MDCR_EL2_HLP_BIT (U(1) << 26) 659 #define MDCR_EL2_E2TB(x) ((x) << 24) 660 #define MDCR_EL2_E2TB_EL1 U(0x3) 661 #define MDCR_EL2_HCCD_BIT (U(1) << 23) 662 #define MDCR_EL2_TTRF (U(1) << 19) 663 #define MDCR_EL2_HPMD_BIT (U(1) << 17) 664 #define MDCR_EL2_TPMS (U(1) << 14) 665 #define MDCR_EL2_E2PB(x) ((x) << 12) 666 #define MDCR_EL2_E2PB_EL1 U(0x3) 667 #define MDCR_EL2_TDRA_BIT (U(1) << 11) 668 #define MDCR_EL2_TDOSA_BIT (U(1) << 10) 669 #define MDCR_EL2_TDA_BIT (U(1) << 9) 670 #define MDCR_EL2_TDE_BIT (U(1) << 8) 671 #define MDCR_EL2_HPME_BIT (U(1) << 7) 672 #define MDCR_EL2_TPM_BIT (U(1) << 6) 673 #define MDCR_EL2_TPMCR_BIT (U(1) << 5) 674 #define MDCR_EL2_HPMN_MASK U(0x1f) 675 #define MDCR_EL2_RESET_VAL U(0x0) 676 677 /* HSTR_EL2 definitions */ 678 #define HSTR_EL2_RESET_VAL U(0x0) 679 #define HSTR_EL2_T_MASK U(0xff) 680 681 /* CNTHP_CTL_EL2 definitions */ 682 #define CNTHP_CTL_ENABLE_BIT (U(1) << 0) 683 #define CNTHP_CTL_RESET_VAL U(0x0) 684 685 /* VTTBR_EL2 definitions */ 686 #define VTTBR_RESET_VAL ULL(0x0) 687 #define VTTBR_VMID_MASK ULL(0xff) 688 #define VTTBR_VMID_SHIFT U(48) 689 #define VTTBR_BADDR_MASK ULL(0xffffffffffff) 690 #define VTTBR_BADDR_SHIFT U(0) 691 692 /* HCR definitions */ 693 #define HCR_RESET_VAL ULL(0x0) 694 #define HCR_AMVOFFEN_SHIFT U(51) 695 #define HCR_AMVOFFEN_BIT (ULL(1) << HCR_AMVOFFEN_SHIFT) 696 #define HCR_TEA_BIT (ULL(1) << 47) 697 #define HCR_API_BIT (ULL(1) << 41) 698 #define HCR_APK_BIT (ULL(1) << 40) 699 #define HCR_E2H_BIT (ULL(1) << 34) 700 #define HCR_HCD_BIT (ULL(1) << 29) 701 #define HCR_TGE_BIT (ULL(1) << 27) 702 #define HCR_RW_SHIFT U(31) 703 #define HCR_RW_BIT (ULL(1) << HCR_RW_SHIFT) 704 #define HCR_TWE_BIT (ULL(1) << 14) 705 #define HCR_TWI_BIT (ULL(1) << 13) 706 #define HCR_AMO_BIT (ULL(1) << 5) 707 #define HCR_IMO_BIT (ULL(1) << 4) 708 #define HCR_FMO_BIT (ULL(1) << 3) 709 710 /* ISR definitions */ 711 #define ISR_A_SHIFT U(8) 712 #define ISR_I_SHIFT U(7) 713 #define ISR_F_SHIFT U(6) 714 715 /* CNTHCTL_EL2 definitions */ 716 #define CNTHCTL_RESET_VAL U(0x0) 717 #define EVNTEN_BIT (U(1) << 2) 718 #define EL1PCEN_BIT (U(1) << 1) 719 #define EL1PCTEN_BIT (U(1) << 0) 720 721 /* CNTKCTL_EL1 definitions */ 722 #define EL0PTEN_BIT (U(1) << 9) 723 #define EL0VTEN_BIT (U(1) << 8) 724 #define EL0PCTEN_BIT (U(1) << 0) 725 #define EL0VCTEN_BIT (U(1) << 1) 726 #define EVNTEN_BIT (U(1) << 2) 727 #define EVNTDIR_BIT (U(1) << 3) 728 #define EVNTI_SHIFT U(4) 729 #define EVNTI_MASK U(0xf) 730 731 /* CPTR_EL3 definitions */ 732 #define TCPAC_BIT (U(1) << 31) 733 #define TAM_SHIFT U(30) 734 #define TAM_BIT (U(1) << TAM_SHIFT) 735 #define TTA_BIT (U(1) << 20) 736 #define ESM_BIT (U(1) << 12) 737 #define TFP_BIT (U(1) << 10) 738 #define CPTR_EZ_BIT (U(1) << 8) 739 #define CPTR_EL3_RESET_VAL ((TCPAC_BIT | TAM_BIT | TTA_BIT | TFP_BIT) & \ 740 ~(CPTR_EZ_BIT | ESM_BIT)) 741 742 /* CPTR_EL2 definitions */ 743 #define CPTR_EL2_RES1 ((U(1) << 13) | (U(1) << 12) | (U(0x3ff))) 744 #define CPTR_EL2_TCPAC_BIT (U(1) << 31) 745 #define CPTR_EL2_TAM_SHIFT U(30) 746 #define CPTR_EL2_TAM_BIT (U(1) << CPTR_EL2_TAM_SHIFT) 747 #define CPTR_EL2_SMEN_MASK ULL(0x3) 748 #define CPTR_EL2_SMEN_SHIFT U(24) 749 #define CPTR_EL2_TTA_BIT (U(1) << 20) 750 #define CPTR_EL2_TSM_BIT (U(1) << 12) 751 #define CPTR_EL2_TFP_BIT (U(1) << 10) 752 #define CPTR_EL2_TZ_BIT (U(1) << 8) 753 #define CPTR_EL2_RESET_VAL CPTR_EL2_RES1 754 755 /* VTCR_EL2 definitions */ 756 #define VTCR_RESET_VAL U(0x0) 757 #define VTCR_EL2_MSA (U(1) << 31) 758 759 /* CPSR/SPSR definitions */ 760 #define DAIF_FIQ_BIT (U(1) << 0) 761 #define DAIF_IRQ_BIT (U(1) << 1) 762 #define DAIF_ABT_BIT (U(1) << 2) 763 #define DAIF_DBG_BIT (U(1) << 3) 764 #define SPSR_V_BIT (U(1) << 28) 765 #define SPSR_C_BIT (U(1) << 29) 766 #define SPSR_Z_BIT (U(1) << 30) 767 #define SPSR_N_BIT (U(1) << 31) 768 #define SPSR_DAIF_SHIFT U(6) 769 #define SPSR_DAIF_MASK U(0xf) 770 771 #define SPSR_AIF_SHIFT U(6) 772 #define SPSR_AIF_MASK U(0x7) 773 774 #define SPSR_E_SHIFT U(9) 775 #define SPSR_E_MASK U(0x1) 776 #define SPSR_E_LITTLE U(0x0) 777 #define SPSR_E_BIG U(0x1) 778 779 #define SPSR_T_SHIFT U(5) 780 #define SPSR_T_MASK U(0x1) 781 #define SPSR_T_ARM U(0x0) 782 #define SPSR_T_THUMB U(0x1) 783 784 #define SPSR_M_SHIFT U(4) 785 #define SPSR_M_MASK U(0x1) 786 #define SPSR_M_AARCH64 U(0x0) 787 #define SPSR_M_AARCH32 U(0x1) 788 #define SPSR_M_EL1H U(0x5) 789 #define SPSR_M_EL2H U(0x9) 790 791 #define SPSR_EL_SHIFT U(2) 792 #define SPSR_EL_WIDTH U(2) 793 794 #define SPSR_BTYPE_SHIFT_AARCH64 U(10) 795 #define SPSR_BTYPE_MASK_AARCH64 U(0x3) 796 #define SPSR_SSBS_SHIFT_AARCH64 U(12) 797 #define SPSR_SSBS_BIT_AARCH64 (ULL(1) << SPSR_SSBS_SHIFT_AARCH64) 798 #define SPSR_SSBS_SHIFT_AARCH32 U(23) 799 #define SPSR_SSBS_BIT_AARCH32 (ULL(1) << SPSR_SSBS_SHIFT_AARCH32) 800 #define SPSR_ALLINT_BIT_AARCH64 BIT_64(13) 801 #define SPSR_IL_BIT BIT_64(20) 802 #define SPSR_SS_BIT BIT_64(21) 803 #define SPSR_PAN_BIT BIT_64(22) 804 #define SPSR_UAO_BIT_AARCH64 BIT_64(23) 805 #define SPSR_DIT_BIT BIT(24) 806 #define SPSR_TCO_BIT_AARCH64 BIT_64(25) 807 #define SPSR_PM_BIT_AARCH64 BIT_64(32) 808 #define SPSR_PPEND_BIT BIT(33) 809 #define SPSR_EXLOCK_BIT_AARCH64 BIT_64(34) 810 #define SPSR_NZCV (SPSR_V_BIT | SPSR_C_BIT | SPSR_Z_BIT | SPSR_N_BIT) 811 812 #define DISABLE_ALL_EXCEPTIONS \ 813 (DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT | DAIF_DBG_BIT) 814 #define DISABLE_INTERRUPTS (DAIF_FIQ_BIT | DAIF_IRQ_BIT) 815 816 /* 817 * RMR_EL3 definitions 818 */ 819 #define RMR_EL3_RR_BIT (U(1) << 1) 820 #define RMR_EL3_AA64_BIT (U(1) << 0) 821 822 /* 823 * HI-VECTOR address for AArch32 state 824 */ 825 #define HI_VECTOR_BASE U(0xFFFF0000) 826 827 /* 828 * TCR definitions 829 */ 830 #define TCR_EL3_RES1 ((ULL(1) << 31) | (ULL(1) << 23)) 831 #define TCR_EL2_RES1 ((ULL(1) << 31) | (ULL(1) << 23)) 832 #define TCR_EL1_IPS_SHIFT U(32) 833 #define TCR_EL2_PS_SHIFT U(16) 834 #define TCR_EL3_PS_SHIFT U(16) 835 836 #define TCR_TxSZ_MIN ULL(16) 837 #define TCR_TxSZ_MAX ULL(39) 838 #define TCR_TxSZ_MAX_TTST ULL(48) 839 840 #define TCR_T0SZ_SHIFT U(0) 841 #define TCR_T1SZ_SHIFT U(16) 842 843 /* (internal) physical address size bits in EL3/EL1 */ 844 #define TCR_PS_BITS_4GB ULL(0x0) 845 #define TCR_PS_BITS_64GB ULL(0x1) 846 #define TCR_PS_BITS_1TB ULL(0x2) 847 #define TCR_PS_BITS_4TB ULL(0x3) 848 #define TCR_PS_BITS_16TB ULL(0x4) 849 #define TCR_PS_BITS_256TB ULL(0x5) 850 851 #define ADDR_MASK_48_TO_63 ULL(0xFFFF000000000000) 852 #define ADDR_MASK_44_TO_47 ULL(0x0000F00000000000) 853 #define ADDR_MASK_42_TO_43 ULL(0x00000C0000000000) 854 #define ADDR_MASK_40_TO_41 ULL(0x0000030000000000) 855 #define ADDR_MASK_36_TO_39 ULL(0x000000F000000000) 856 #define ADDR_MASK_32_TO_35 ULL(0x0000000F00000000) 857 858 #define TCR_RGN_INNER_NC (ULL(0x0) << 8) 859 #define TCR_RGN_INNER_WBA (ULL(0x1) << 8) 860 #define TCR_RGN_INNER_WT (ULL(0x2) << 8) 861 #define TCR_RGN_INNER_WBNA (ULL(0x3) << 8) 862 863 #define TCR_RGN_OUTER_NC (ULL(0x0) << 10) 864 #define TCR_RGN_OUTER_WBA (ULL(0x1) << 10) 865 #define TCR_RGN_OUTER_WT (ULL(0x2) << 10) 866 #define TCR_RGN_OUTER_WBNA (ULL(0x3) << 10) 867 868 #define TCR_SH_NON_SHAREABLE (ULL(0x0) << 12) 869 #define TCR_SH_OUTER_SHAREABLE (ULL(0x2) << 12) 870 #define TCR_SH_INNER_SHAREABLE (ULL(0x3) << 12) 871 872 #define TCR_RGN1_INNER_NC (ULL(0x0) << 24) 873 #define TCR_RGN1_INNER_WBA (ULL(0x1) << 24) 874 #define TCR_RGN1_INNER_WT (ULL(0x2) << 24) 875 #define TCR_RGN1_INNER_WBNA (ULL(0x3) << 24) 876 877 #define TCR_RGN1_OUTER_NC (ULL(0x0) << 26) 878 #define TCR_RGN1_OUTER_WBA (ULL(0x1) << 26) 879 #define TCR_RGN1_OUTER_WT (ULL(0x2) << 26) 880 #define TCR_RGN1_OUTER_WBNA (ULL(0x3) << 26) 881 882 #define TCR_SH1_NON_SHAREABLE (ULL(0x0) << 28) 883 #define TCR_SH1_OUTER_SHAREABLE (ULL(0x2) << 28) 884 #define TCR_SH1_INNER_SHAREABLE (ULL(0x3) << 28) 885 886 #define TCR_TG0_SHIFT U(14) 887 #define TCR_TG0_MASK ULL(3) 888 #define TCR_TG0_4K (ULL(0) << TCR_TG0_SHIFT) 889 #define TCR_TG0_64K (ULL(1) << TCR_TG0_SHIFT) 890 #define TCR_TG0_16K (ULL(2) << TCR_TG0_SHIFT) 891 892 #define TCR_TG1_SHIFT U(30) 893 #define TCR_TG1_MASK ULL(3) 894 #define TCR_TG1_16K (ULL(1) << TCR_TG1_SHIFT) 895 #define TCR_TG1_4K (ULL(2) << TCR_TG1_SHIFT) 896 #define TCR_TG1_64K (ULL(3) << TCR_TG1_SHIFT) 897 898 #define TCR_EPD0_BIT (ULL(1) << 7) 899 #define TCR_EPD1_BIT (ULL(1) << 23) 900 901 #define MODE_SP_SHIFT U(0x0) 902 #define MODE_SP_MASK U(0x1) 903 #define MODE_SP_EL0 U(0x0) 904 #define MODE_SP_ELX U(0x1) 905 906 #define MODE_RW_SHIFT U(0x4) 907 #define MODE_RW_MASK U(0x1) 908 #define MODE_RW_64 U(0x0) 909 #define MODE_RW_32 U(0x1) 910 911 #define MODE_EL_SHIFT U(0x2) 912 #define MODE_EL_MASK U(0x3) 913 #define MODE_EL_WIDTH U(0x2) 914 #define MODE_EL3 U(0x3) 915 #define MODE_EL2 U(0x2) 916 #define MODE_EL1 U(0x1) 917 #define MODE_EL0 U(0x0) 918 919 #define MODE32_SHIFT U(0) 920 #define MODE32_MASK U(0xf) 921 #define MODE32_usr U(0x0) 922 #define MODE32_fiq U(0x1) 923 #define MODE32_irq U(0x2) 924 #define MODE32_svc U(0x3) 925 #define MODE32_mon U(0x6) 926 #define MODE32_abt U(0x7) 927 #define MODE32_hyp U(0xa) 928 #define MODE32_und U(0xb) 929 #define MODE32_sys U(0xf) 930 931 #define GET_RW(mode) (((mode) >> MODE_RW_SHIFT) & MODE_RW_MASK) 932 #define GET_EL(mode) (((mode) >> MODE_EL_SHIFT) & MODE_EL_MASK) 933 #define GET_SP(mode) (((mode) >> MODE_SP_SHIFT) & MODE_SP_MASK) 934 #define GET_M32(mode) (((mode) >> MODE32_SHIFT) & MODE32_MASK) 935 936 #define SPSR_64(el, sp, daif) \ 937 (((MODE_RW_64 << MODE_RW_SHIFT) | \ 938 (((el) & MODE_EL_MASK) << MODE_EL_SHIFT) | \ 939 (((sp) & MODE_SP_MASK) << MODE_SP_SHIFT) | \ 940 (((daif) & SPSR_DAIF_MASK) << SPSR_DAIF_SHIFT)) & \ 941 (~(SPSR_SSBS_BIT_AARCH64))) 942 943 #define SPSR_MODE32(mode, isa, endian, aif) \ 944 (((MODE_RW_32 << MODE_RW_SHIFT) | \ 945 (((mode) & MODE32_MASK) << MODE32_SHIFT) | \ 946 (((isa) & SPSR_T_MASK) << SPSR_T_SHIFT) | \ 947 (((endian) & SPSR_E_MASK) << SPSR_E_SHIFT) | \ 948 (((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT)) & \ 949 (~(SPSR_SSBS_BIT_AARCH32))) 950 951 /* 952 * TTBR Definitions 953 */ 954 #define TTBR_CNP_BIT ULL(0x1) 955 956 /* 957 * CTR_EL0 definitions 958 */ 959 #define CTR_CWG_SHIFT U(24) 960 #define CTR_CWG_MASK U(0xf) 961 #define CTR_ERG_SHIFT U(20) 962 #define CTR_ERG_MASK U(0xf) 963 #define CTR_DMINLINE_SHIFT U(16) 964 #define CTR_DMINLINE_MASK U(0xf) 965 #define CTR_L1IP_SHIFT U(14) 966 #define CTR_L1IP_MASK U(0x3) 967 #define CTR_IMINLINE_SHIFT U(0) 968 #define CTR_IMINLINE_MASK U(0xf) 969 970 #define MAX_CACHE_LINE_SIZE U(0x800) /* 2KB */ 971 972 /* Physical timer control register bit fields shifts and masks */ 973 #define CNTP_CTL_ENABLE_SHIFT U(0) 974 #define CNTP_CTL_IMASK_SHIFT U(1) 975 #define CNTP_CTL_ISTATUS_SHIFT U(2) 976 977 #define CNTP_CTL_ENABLE_MASK U(1) 978 #define CNTP_CTL_IMASK_MASK U(1) 979 #define CNTP_CTL_ISTATUS_MASK U(1) 980 981 /* Physical timer control macros */ 982 #define CNTP_CTL_ENABLE_BIT (U(1) << CNTP_CTL_ENABLE_SHIFT) 983 #define CNTP_CTL_IMASK_BIT (U(1) << CNTP_CTL_IMASK_SHIFT) 984 985 /* Exception Syndrome register bits and bobs */ 986 #define ESR_EC_SHIFT U(26) 987 #define ESR_EC_MASK U(0x3f) 988 #define ESR_EC_LENGTH U(6) 989 #define ESR_ISS_SHIFT U(0) 990 #define ESR_ISS_LENGTH U(25) 991 #define ESR_IL_BIT (U(1) << 25) 992 #define EC_UNKNOWN U(0x0) 993 #define EC_WFE_WFI U(0x1) 994 #define EC_AARCH32_CP15_MRC_MCR U(0x3) 995 #define EC_AARCH32_CP15_MRRC_MCRR U(0x4) 996 #define EC_AARCH32_CP14_MRC_MCR U(0x5) 997 #define EC_AARCH32_CP14_LDC_STC U(0x6) 998 #define EC_FP_SIMD U(0x7) 999 #define EC_AARCH32_CP10_MRC U(0x8) 1000 #define EC_AARCH32_CP14_MRRC_MCRR U(0xc) 1001 #define EC_ILLEGAL U(0xe) 1002 #define EC_AARCH32_SVC U(0x11) 1003 #define EC_AARCH32_HVC U(0x12) 1004 #define EC_AARCH32_SMC U(0x13) 1005 #define EC_AARCH64_SVC U(0x15) 1006 #define EC_AARCH64_HVC U(0x16) 1007 #define EC_AARCH64_SMC U(0x17) 1008 #define EC_AARCH64_SYS U(0x18) 1009 #define EC_IMP_DEF_EL3 U(0x1f) 1010 #define EC_IABORT_LOWER_EL U(0x20) 1011 #define EC_IABORT_CUR_EL U(0x21) 1012 #define EC_PC_ALIGN U(0x22) 1013 #define EC_DABORT_LOWER_EL U(0x24) 1014 #define EC_DABORT_CUR_EL U(0x25) 1015 #define EC_SP_ALIGN U(0x26) 1016 #define EC_AARCH32_FP U(0x28) 1017 #define EC_AARCH64_FP U(0x2c) 1018 #define EC_SERROR U(0x2f) 1019 #define EC_BRK U(0x3c) 1020 1021 /* 1022 * External Abort bit in Instruction and Data Aborts synchronous exception 1023 * syndromes. 1024 */ 1025 #define ESR_ISS_EABORT_EA_BIT U(9) 1026 1027 #define EC_BITS(x) (((x) >> ESR_EC_SHIFT) & ESR_EC_MASK) 1028 1029 /* Reset bit inside the Reset management register for EL3 (RMR_EL3) */ 1030 #define RMR_RESET_REQUEST_SHIFT U(0x1) 1031 #define RMR_WARM_RESET_CPU (U(1) << RMR_RESET_REQUEST_SHIFT) 1032 1033 /******************************************************************************* 1034 * Definitions of register offsets, fields and macros for CPU system 1035 * instructions. 1036 ******************************************************************************/ 1037 1038 #define TLBI_ADDR_SHIFT U(12) 1039 #define TLBI_ADDR_MASK ULL(0x00000FFFFFFFFFFF) 1040 #define TLBI_ADDR(x) (((x) >> TLBI_ADDR_SHIFT) & TLBI_ADDR_MASK) 1041 1042 /******************************************************************************* 1043 * Definitions of register offsets and fields in the CNTCTLBase Frame of the 1044 * system level implementation of the Generic Timer. 1045 ******************************************************************************/ 1046 #define CNTCTLBASE_CNTFRQ U(0x0) 1047 #define CNTNSAR U(0x4) 1048 #define CNTNSAR_NS_SHIFT(x) (x) 1049 1050 #define CNTACR_BASE(x) (U(0x40) + ((x) << 2)) 1051 #define CNTACR_RPCT_SHIFT U(0x0) 1052 #define CNTACR_RVCT_SHIFT U(0x1) 1053 #define CNTACR_RFRQ_SHIFT U(0x2) 1054 #define CNTACR_RVOFF_SHIFT U(0x3) 1055 #define CNTACR_RWVT_SHIFT U(0x4) 1056 #define CNTACR_RWPT_SHIFT U(0x5) 1057 1058 /******************************************************************************* 1059 * Definitions of register offsets and fields in the CNTBaseN Frame of the 1060 * system level implementation of the Generic Timer. 1061 ******************************************************************************/ 1062 /* Physical Count register. */ 1063 #define CNTPCT_LO U(0x0) 1064 /* Counter Frequency register. */ 1065 #define CNTBASEN_CNTFRQ U(0x10) 1066 /* Physical Timer CompareValue register. */ 1067 #define CNTP_CVAL_LO U(0x20) 1068 /* Physical Timer Control register. */ 1069 #define CNTP_CTL U(0x2c) 1070 1071 /* PMCR_EL0 definitions */ 1072 #define PMCR_EL0_RESET_VAL U(0x0) 1073 #define PMCR_EL0_N_SHIFT U(11) 1074 #define PMCR_EL0_N_MASK U(0x1f) 1075 #define PMCR_EL0_N_BITS (PMCR_EL0_N_MASK << PMCR_EL0_N_SHIFT) 1076 #define PMCR_EL0_LP_BIT (U(1) << 7) 1077 #define PMCR_EL0_LC_BIT (U(1) << 6) 1078 #define PMCR_EL0_DP_BIT (U(1) << 5) 1079 #define PMCR_EL0_X_BIT (U(1) << 4) 1080 #define PMCR_EL0_D_BIT (U(1) << 3) 1081 #define PMCR_EL0_C_BIT (U(1) << 2) 1082 #define PMCR_EL0_P_BIT (U(1) << 1) 1083 #define PMCR_EL0_E_BIT (U(1) << 0) 1084 1085 /******************************************************************************* 1086 * Definitions for system register interface to SVE 1087 ******************************************************************************/ 1088 #define ZCR_EL3 S3_6_C1_C2_0 1089 #define ZCR_EL2 S3_4_C1_C2_0 1090 1091 /* ZCR_EL3 definitions */ 1092 #define ZCR_EL3_LEN_MASK U(0xf) 1093 1094 /* ZCR_EL2 definitions */ 1095 #define ZCR_EL2_LEN_MASK U(0xf) 1096 1097 /******************************************************************************* 1098 * Definitions for system register interface to SME as needed in EL3 1099 ******************************************************************************/ 1100 #define ID_AA64SMFR0_EL1 S3_0_C0_C4_5 1101 #define SMCR_EL3 S3_6_C1_C2_6 1102 1103 /* ID_AA64SMFR0_EL1 definitions */ 1104 #define ID_AA64SMFR0_EL1_SME_FA64_SHIFT U(63) 1105 #define ID_AA64SMFR0_EL1_SME_FA64_MASK U(0x1) 1106 #define ID_AA64SMFR0_EL1_SME_FA64_SUPPORTED U(0x1) 1107 #define ID_AA64SMFR0_EL1_SME_VER_SHIFT U(55) 1108 #define ID_AA64SMFR0_EL1_SME_VER_MASK ULL(0xf) 1109 #define ID_AA64SMFR0_EL1_SME_INST_SUPPORTED ULL(0x0) 1110 #define ID_AA64SMFR0_EL1_SME2_INST_SUPPORTED ULL(0x1) 1111 1112 /* SMCR_ELx definitions */ 1113 #define SMCR_ELX_LEN_SHIFT U(0) 1114 #define SMCR_ELX_LEN_MAX U(0x1ff) 1115 #define SMCR_ELX_FA64_BIT (U(1) << 31) 1116 #define SMCR_ELX_EZT0_BIT (U(1) << 30) 1117 1118 /******************************************************************************* 1119 * Definitions of MAIR encodings for device and normal memory 1120 ******************************************************************************/ 1121 /* 1122 * MAIR encodings for device memory attributes. 1123 */ 1124 #define MAIR_DEV_nGnRnE ULL(0x0) 1125 #define MAIR_DEV_nGnRE ULL(0x4) 1126 #define MAIR_DEV_nGRE ULL(0x8) 1127 #define MAIR_DEV_GRE ULL(0xc) 1128 1129 /* 1130 * MAIR encodings for normal memory attributes. 1131 * 1132 * Cache Policy 1133 * WT: Write Through 1134 * WB: Write Back 1135 * NC: Non-Cacheable 1136 * 1137 * Transient Hint 1138 * NTR: Non-Transient 1139 * TR: Transient 1140 * 1141 * Allocation Policy 1142 * RA: Read Allocate 1143 * WA: Write Allocate 1144 * RWA: Read and Write Allocate 1145 * NA: No Allocation 1146 */ 1147 #define MAIR_NORM_WT_TR_WA ULL(0x1) 1148 #define MAIR_NORM_WT_TR_RA ULL(0x2) 1149 #define MAIR_NORM_WT_TR_RWA ULL(0x3) 1150 #define MAIR_NORM_NC ULL(0x4) 1151 #define MAIR_NORM_WB_TR_WA ULL(0x5) 1152 #define MAIR_NORM_WB_TR_RA ULL(0x6) 1153 #define MAIR_NORM_WB_TR_RWA ULL(0x7) 1154 #define MAIR_NORM_WT_NTR_NA ULL(0x8) 1155 #define MAIR_NORM_WT_NTR_WA ULL(0x9) 1156 #define MAIR_NORM_WT_NTR_RA ULL(0xa) 1157 #define MAIR_NORM_WT_NTR_RWA ULL(0xb) 1158 #define MAIR_NORM_WB_NTR_NA ULL(0xc) 1159 #define MAIR_NORM_WB_NTR_WA ULL(0xd) 1160 #define MAIR_NORM_WB_NTR_RA ULL(0xe) 1161 #define MAIR_NORM_WB_NTR_RWA ULL(0xf) 1162 1163 #define MAIR_NORM_OUTER_SHIFT U(4) 1164 1165 #define MAKE_MAIR_NORMAL_MEMORY(inner, outer) \ 1166 ((inner) | ((outer) << MAIR_NORM_OUTER_SHIFT)) 1167 1168 /* PAR_EL1 fields */ 1169 #define PAR_F_SHIFT U(0) 1170 #define PAR_F_MASK ULL(0x1) 1171 #define PAR_ADDR_SHIFT U(12) 1172 #define PAR_ADDR_MASK (BIT(40) - ULL(1)) /* 40-bits-wide page address */ 1173 1174 /******************************************************************************* 1175 * Definitions for system register interface to SPE 1176 ******************************************************************************/ 1177 #define PMBLIMITR_EL1 S3_0_C9_C10_0 1178 1179 /******************************************************************************* 1180 * Definitions for system register interface, shifts and masks for MPAM 1181 ******************************************************************************/ 1182 #define MPAMIDR_EL1 S3_0_C10_C4_4 1183 #define MPAM2_EL2 S3_4_C10_C5_0 1184 #define MPAMHCR_EL2 S3_4_C10_C4_0 1185 #define MPAM3_EL3 S3_6_C10_C5_0 1186 1187 #define MPAMIDR_EL1_VPMR_MAX_SHIFT ULL(18) 1188 #define MPAMIDR_EL1_VPMR_MAX_MASK ULL(0x7) 1189 /******************************************************************************* 1190 * Definitions for system register interface to AMU for FEAT_AMUv1 1191 ******************************************************************************/ 1192 #define AMCR_EL0 S3_3_C13_C2_0 1193 #define AMCFGR_EL0 S3_3_C13_C2_1 1194 #define AMCGCR_EL0 S3_3_C13_C2_2 1195 #define AMUSERENR_EL0 S3_3_C13_C2_3 1196 #define AMCNTENCLR0_EL0 S3_3_C13_C2_4 1197 #define AMCNTENSET0_EL0 S3_3_C13_C2_5 1198 #define AMCNTENCLR1_EL0 S3_3_C13_C3_0 1199 #define AMCNTENSET1_EL0 S3_3_C13_C3_1 1200 1201 /* Activity Monitor Group 0 Event Counter Registers */ 1202 #define AMEVCNTR00_EL0 S3_3_C13_C4_0 1203 #define AMEVCNTR01_EL0 S3_3_C13_C4_1 1204 #define AMEVCNTR02_EL0 S3_3_C13_C4_2 1205 #define AMEVCNTR03_EL0 S3_3_C13_C4_3 1206 1207 /* Activity Monitor Group 0 Event Type Registers */ 1208 #define AMEVTYPER00_EL0 S3_3_C13_C6_0 1209 #define AMEVTYPER01_EL0 S3_3_C13_C6_1 1210 #define AMEVTYPER02_EL0 S3_3_C13_C6_2 1211 #define AMEVTYPER03_EL0 S3_3_C13_C6_3 1212 1213 /* Activity Monitor Group 1 Event Counter Registers */ 1214 #define AMEVCNTR10_EL0 S3_3_C13_C12_0 1215 #define AMEVCNTR11_EL0 S3_3_C13_C12_1 1216 #define AMEVCNTR12_EL0 S3_3_C13_C12_2 1217 #define AMEVCNTR13_EL0 S3_3_C13_C12_3 1218 #define AMEVCNTR14_EL0 S3_3_C13_C12_4 1219 #define AMEVCNTR15_EL0 S3_3_C13_C12_5 1220 #define AMEVCNTR16_EL0 S3_3_C13_C12_6 1221 #define AMEVCNTR17_EL0 S3_3_C13_C12_7 1222 #define AMEVCNTR18_EL0 S3_3_C13_C13_0 1223 #define AMEVCNTR19_EL0 S3_3_C13_C13_1 1224 #define AMEVCNTR1A_EL0 S3_3_C13_C13_2 1225 #define AMEVCNTR1B_EL0 S3_3_C13_C13_3 1226 #define AMEVCNTR1C_EL0 S3_3_C13_C13_4 1227 #define AMEVCNTR1D_EL0 S3_3_C13_C13_5 1228 #define AMEVCNTR1E_EL0 S3_3_C13_C13_6 1229 #define AMEVCNTR1F_EL0 S3_3_C13_C13_7 1230 1231 /* Activity Monitor Group 1 Event Type Registers */ 1232 #define AMEVTYPER10_EL0 S3_3_C13_C14_0 1233 #define AMEVTYPER11_EL0 S3_3_C13_C14_1 1234 #define AMEVTYPER12_EL0 S3_3_C13_C14_2 1235 #define AMEVTYPER13_EL0 S3_3_C13_C14_3 1236 #define AMEVTYPER14_EL0 S3_3_C13_C14_4 1237 #define AMEVTYPER15_EL0 S3_3_C13_C14_5 1238 #define AMEVTYPER16_EL0 S3_3_C13_C14_6 1239 #define AMEVTYPER17_EL0 S3_3_C13_C14_7 1240 #define AMEVTYPER18_EL0 S3_3_C13_C15_0 1241 #define AMEVTYPER19_EL0 S3_3_C13_C15_1 1242 #define AMEVTYPER1A_EL0 S3_3_C13_C15_2 1243 #define AMEVTYPER1B_EL0 S3_3_C13_C15_3 1244 #define AMEVTYPER1C_EL0 S3_3_C13_C15_4 1245 #define AMEVTYPER1D_EL0 S3_3_C13_C15_5 1246 #define AMEVTYPER1E_EL0 S3_3_C13_C15_6 1247 #define AMEVTYPER1F_EL0 S3_3_C13_C15_7 1248 1249 /* AMCNTENSET0_EL0 definitions */ 1250 #define AMCNTENSET0_EL0_Pn_SHIFT U(0) 1251 #define AMCNTENSET0_EL0_Pn_MASK ULL(0xffff) 1252 1253 /* AMCNTENSET1_EL0 definitions */ 1254 #define AMCNTENSET1_EL0_Pn_SHIFT U(0) 1255 #define AMCNTENSET1_EL0_Pn_MASK ULL(0xffff) 1256 1257 /* AMCNTENCLR0_EL0 definitions */ 1258 #define AMCNTENCLR0_EL0_Pn_SHIFT U(0) 1259 #define AMCNTENCLR0_EL0_Pn_MASK ULL(0xffff) 1260 1261 /* AMCNTENCLR1_EL0 definitions */ 1262 #define AMCNTENCLR1_EL0_Pn_SHIFT U(0) 1263 #define AMCNTENCLR1_EL0_Pn_MASK ULL(0xffff) 1264 1265 /* AMCFGR_EL0 definitions */ 1266 #define AMCFGR_EL0_NCG_SHIFT U(28) 1267 #define AMCFGR_EL0_NCG_MASK U(0xf) 1268 #define AMCFGR_EL0_N_SHIFT U(0) 1269 #define AMCFGR_EL0_N_MASK U(0xff) 1270 1271 /* AMCGCR_EL0 definitions */ 1272 #define AMCGCR_EL0_CG0NC_SHIFT U(0) 1273 #define AMCGCR_EL0_CG0NC_MASK U(0xff) 1274 #define AMCGCR_EL0_CG1NC_SHIFT U(8) 1275 #define AMCGCR_EL0_CG1NC_MASK U(0xff) 1276 1277 /* MPAM register definitions */ 1278 #define MPAM3_EL3_MPAMEN_BIT (ULL(1) << 63) 1279 #define MPAM3_EL3_TRAPLOWER_BIT (ULL(1) << 62) 1280 #define MPAMHCR_EL2_TRAP_MPAMIDR_EL1 (ULL(1) << 31) 1281 #define MPAM3_EL3_RESET_VAL MPAM3_EL3_TRAPLOWER_BIT 1282 1283 #define MPAM2_EL2_TRAPMPAM0EL1 (ULL(1) << 49) 1284 #define MPAM2_EL2_TRAPMPAM1EL1 (ULL(1) << 48) 1285 1286 #define MPAMIDR_HAS_HCR_BIT (ULL(1) << 17) 1287 1288 /******************************************************************************* 1289 * Definitions for system register interface to AMU for FEAT_AMUv1p1 1290 ******************************************************************************/ 1291 1292 /* Definition for register defining which virtual offsets are implemented. */ 1293 #define AMCG1IDR_EL0 S3_3_C13_C2_6 1294 #define AMCG1IDR_CTR_MASK ULL(0xffff) 1295 #define AMCG1IDR_CTR_SHIFT U(0) 1296 #define AMCG1IDR_VOFF_MASK ULL(0xffff) 1297 #define AMCG1IDR_VOFF_SHIFT U(16) 1298 1299 /* New bit added to AMCR_EL0 */ 1300 #define AMCR_CG1RZ_SHIFT U(17) 1301 #define AMCR_CG1RZ_BIT (ULL(0x1) << AMCR_CG1RZ_SHIFT) 1302 1303 /* 1304 * Definitions for virtual offset registers for architected activity monitor 1305 * event counters. 1306 * AMEVCNTVOFF01_EL2 intentionally left undefined, as it does not exist. 1307 */ 1308 #define AMEVCNTVOFF00_EL2 S3_4_C13_C8_0 1309 #define AMEVCNTVOFF02_EL2 S3_4_C13_C8_2 1310 #define AMEVCNTVOFF03_EL2 S3_4_C13_C8_3 1311 1312 /* 1313 * Definitions for virtual offset registers for auxiliary activity monitor event 1314 * counters. 1315 */ 1316 #define AMEVCNTVOFF10_EL2 S3_4_C13_C10_0 1317 #define AMEVCNTVOFF11_EL2 S3_4_C13_C10_1 1318 #define AMEVCNTVOFF12_EL2 S3_4_C13_C10_2 1319 #define AMEVCNTVOFF13_EL2 S3_4_C13_C10_3 1320 #define AMEVCNTVOFF14_EL2 S3_4_C13_C10_4 1321 #define AMEVCNTVOFF15_EL2 S3_4_C13_C10_5 1322 #define AMEVCNTVOFF16_EL2 S3_4_C13_C10_6 1323 #define AMEVCNTVOFF17_EL2 S3_4_C13_C10_7 1324 #define AMEVCNTVOFF18_EL2 S3_4_C13_C11_0 1325 #define AMEVCNTVOFF19_EL2 S3_4_C13_C11_1 1326 #define AMEVCNTVOFF1A_EL2 S3_4_C13_C11_2 1327 #define AMEVCNTVOFF1B_EL2 S3_4_C13_C11_3 1328 #define AMEVCNTVOFF1C_EL2 S3_4_C13_C11_4 1329 #define AMEVCNTVOFF1D_EL2 S3_4_C13_C11_5 1330 #define AMEVCNTVOFF1E_EL2 S3_4_C13_C11_6 1331 #define AMEVCNTVOFF1F_EL2 S3_4_C13_C11_7 1332 1333 /******************************************************************************* 1334 * Realm management extension register definitions 1335 ******************************************************************************/ 1336 #define GPCCR_EL3 S3_6_C2_C1_6 1337 #define GPTBR_EL3 S3_6_C2_C1_4 1338 1339 #define SCXTNUM_EL2 S3_4_C13_C0_7 1340 1341 /******************************************************************************* 1342 * RAS system registers 1343 ******************************************************************************/ 1344 #define DISR_EL1 S3_0_C12_C1_1 1345 #define DISR_A_BIT U(31) 1346 1347 #define ERRIDR_EL1 S3_0_C5_C3_0 1348 #define ERRIDR_MASK U(0xffff) 1349 1350 #define ERRSELR_EL1 S3_0_C5_C3_1 1351 1352 /* System register access to Standard Error Record registers */ 1353 #define ERXFR_EL1 S3_0_C5_C4_0 1354 #define ERXCTLR_EL1 S3_0_C5_C4_1 1355 #define ERXSTATUS_EL1 S3_0_C5_C4_2 1356 #define ERXADDR_EL1 S3_0_C5_C4_3 1357 #define ERXPFGF_EL1 S3_0_C5_C4_4 1358 #define ERXPFGCTL_EL1 S3_0_C5_C4_5 1359 #define ERXPFGCDN_EL1 S3_0_C5_C4_6 1360 #define ERXMISC0_EL1 S3_0_C5_C5_0 1361 #define ERXMISC1_EL1 S3_0_C5_C5_1 1362 1363 #define ERXCTLR_ED_SHIFT U(0) 1364 #define ERXCTLR_ED_BIT (U(1) << ERXCTLR_ED_SHIFT) 1365 #define ERXCTLR_UE_BIT (U(1) << 4) 1366 1367 #define ERXPFGCTL_UC_BIT (U(1) << 1) 1368 #define ERXPFGCTL_UEU_BIT (U(1) << 2) 1369 #define ERXPFGCTL_CDEN_BIT (U(1) << 31) 1370 1371 /******************************************************************************* 1372 * Armv8.3 Pointer Authentication Registers 1373 ******************************************************************************/ 1374 #define APIAKeyLo_EL1 S3_0_C2_C1_0 1375 #define APIAKeyHi_EL1 S3_0_C2_C1_1 1376 #define APIBKeyLo_EL1 S3_0_C2_C1_2 1377 #define APIBKeyHi_EL1 S3_0_C2_C1_3 1378 #define APDAKeyLo_EL1 S3_0_C2_C2_0 1379 #define APDAKeyHi_EL1 S3_0_C2_C2_1 1380 #define APDBKeyLo_EL1 S3_0_C2_C2_2 1381 #define APDBKeyHi_EL1 S3_0_C2_C2_3 1382 #define APGAKeyLo_EL1 S3_0_C2_C3_0 1383 #define APGAKeyHi_EL1 S3_0_C2_C3_1 1384 1385 /******************************************************************************* 1386 * Armv8.4 Data Independent Timing Registers 1387 ******************************************************************************/ 1388 #define DIT S3_3_C4_C2_5 1389 #define DIT_BIT BIT(24) 1390 1391 /******************************************************************************* 1392 * Armv8.5 - new MSR encoding to directly access PSTATE.SSBS field 1393 ******************************************************************************/ 1394 #define SSBS S3_3_C4_C2_6 1395 1396 /******************************************************************************* 1397 * Armv8.5 - Memory Tagging Extension Registers 1398 ******************************************************************************/ 1399 #define TFSRE0_EL1 S3_0_C5_C6_1 1400 #define TFSR_EL1 S3_0_C5_C6_0 1401 #define RGSR_EL1 S3_0_C1_C0_5 1402 #define GCR_EL1 S3_0_C1_C0_6 1403 1404 #define GCR_EL1_RRND_BIT (UL(1) << 16) 1405 1406 /******************************************************************************* 1407 * Armv8.5 - Random Number Generator Registers 1408 ******************************************************************************/ 1409 #define RNDR S3_3_C2_C4_0 1410 #define RNDRRS S3_3_C2_C4_1 1411 1412 /******************************************************************************* 1413 * FEAT_HCX - Extended Hypervisor Configuration Register 1414 ******************************************************************************/ 1415 #define HCRX_EL2 S3_4_C1_C2_2 1416 #define HCRX_EL2_MSCEn_BIT (UL(1) << 11) 1417 #define HCRX_EL2_MCE2_BIT (UL(1) << 10) 1418 #define HCRX_EL2_CMOW_BIT (UL(1) << 9) 1419 #define HCRX_EL2_VFNMI_BIT (UL(1) << 8) 1420 #define HCRX_EL2_VINMI_BIT (UL(1) << 7) 1421 #define HCRX_EL2_TALLINT_BIT (UL(1) << 6) 1422 #define HCRX_EL2_SMPME_BIT (UL(1) << 5) 1423 #define HCRX_EL2_FGTnXS_BIT (UL(1) << 4) 1424 #define HCRX_EL2_FnXS_BIT (UL(1) << 3) 1425 #define HCRX_EL2_EnASR_BIT (UL(1) << 2) 1426 #define HCRX_EL2_EnALS_BIT (UL(1) << 1) 1427 #define HCRX_EL2_EnAS0_BIT (UL(1) << 0) 1428 #define HCRX_EL2_INIT_VAL ULL(0x0) 1429 1430 /******************************************************************************* 1431 * FEAT_FGT - Definitions for Fine-Grained Trap registers 1432 ******************************************************************************/ 1433 #define HFGITR_EL2_INIT_VAL ULL(0x180000000000000) 1434 #define HFGRTR_EL2_INIT_VAL ULL(0xC4000000000000) 1435 #define HFGWTR_EL2_INIT_VAL ULL(0xC4000000000000) 1436 1437 /******************************************************************************* 1438 * FEAT_TCR2 - Extended Translation Control Register 1439 ******************************************************************************/ 1440 #define TCR2_EL2 S3_4_C2_C0_3 1441 1442 /******************************************************************************* 1443 * Permission indirection and overlay 1444 ******************************************************************************/ 1445 1446 #define PIRE0_EL2 S3_4_C10_C2_2 1447 #define PIR_EL2 S3_4_C10_C2_3 1448 #define POR_EL2 S3_4_C10_C2_4 1449 #define S2PIR_EL2 S3_4_C10_C2_5 1450 1451 /******************************************************************************* 1452 * FEAT_GCS - Guarded Control Stack Registers 1453 ******************************************************************************/ 1454 #define GCSCR_EL2 S3_4_C2_C5_0 1455 #define GCSPR_EL2 S3_4_C2_C5_1 1456 #define GCSCR_EL1 S3_0_C2_C5_0 1457 1458 #define GCSCR_EXLOCK_EN_BIT (UL(1) << 6) 1459 1460 /******************************************************************************* 1461 * Definitions for DynamicIQ Shared Unit registers 1462 ******************************************************************************/ 1463 #define CLUSTERPWRDN_EL1 S3_0_c15_c3_6 1464 1465 /* CLUSTERPWRDN_EL1 register definitions */ 1466 #define DSU_CLUSTER_PWR_OFF 0 1467 #define DSU_CLUSTER_PWR_ON 1 1468 #define DSU_CLUSTER_PWR_MASK U(1) 1469 #define DSU_CLUSTER_MEM_RET BIT(1) 1470 1471 /******************************************************************************* 1472 * Definitions for CPU Power/Performance Management registers 1473 ******************************************************************************/ 1474 1475 #define CPUPPMCR_EL3 S3_6_C15_C2_0 1476 #define CPUPPMCR_EL3_MPMMPINCTL_SHIFT UINT64_C(0) 1477 #define CPUPPMCR_EL3_MPMMPINCTL_MASK UINT64_C(0x1) 1478 1479 #define CPUMPMMCR_EL3 S3_6_C15_C2_1 1480 #define CPUMPMMCR_EL3_MPMM_EN_SHIFT UINT64_C(0) 1481 #define CPUMPMMCR_EL3_MPMM_EN_MASK UINT64_C(0x1) 1482 1483 /* alternative system register encoding for the "sb" speculation barrier */ 1484 #define SYSREG_SB S0_3_C3_C0_7 1485 1486 #endif /* ARCH_H */ 1487