1 /* 2 * Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2020-2022, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef ARCH_H 9 #define ARCH_H 10 11 #include <lib/utils_def.h> 12 13 /******************************************************************************* 14 * MIDR bit definitions 15 ******************************************************************************/ 16 #define MIDR_IMPL_MASK U(0xff) 17 #define MIDR_IMPL_SHIFT U(0x18) 18 #define MIDR_VAR_SHIFT U(20) 19 #define MIDR_VAR_BITS U(4) 20 #define MIDR_VAR_MASK U(0xf) 21 #define MIDR_REV_SHIFT U(0) 22 #define MIDR_REV_BITS U(4) 23 #define MIDR_REV_MASK U(0xf) 24 #define MIDR_PN_MASK U(0xfff) 25 #define MIDR_PN_SHIFT U(0x4) 26 27 /******************************************************************************* 28 * MPIDR macros 29 ******************************************************************************/ 30 #define MPIDR_MT_MASK (ULL(1) << 24) 31 #define MPIDR_CPU_MASK MPIDR_AFFLVL_MASK 32 #define MPIDR_CLUSTER_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS) 33 #define MPIDR_AFFINITY_BITS U(8) 34 #define MPIDR_AFFLVL_MASK ULL(0xff) 35 #define MPIDR_AFF0_SHIFT U(0) 36 #define MPIDR_AFF1_SHIFT U(8) 37 #define MPIDR_AFF2_SHIFT U(16) 38 #define MPIDR_AFF3_SHIFT U(32) 39 #define MPIDR_AFF_SHIFT(_n) MPIDR_AFF##_n##_SHIFT 40 #define MPIDR_AFFINITY_MASK ULL(0xff00ffffff) 41 #define MPIDR_AFFLVL_SHIFT U(3) 42 #define MPIDR_AFFLVL0 ULL(0x0) 43 #define MPIDR_AFFLVL1 ULL(0x1) 44 #define MPIDR_AFFLVL2 ULL(0x2) 45 #define MPIDR_AFFLVL3 ULL(0x3) 46 #define MPIDR_AFFLVL(_n) MPIDR_AFFLVL##_n 47 #define MPIDR_AFFLVL0_VAL(mpidr) \ 48 (((mpidr) >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK) 49 #define MPIDR_AFFLVL1_VAL(mpidr) \ 50 (((mpidr) >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK) 51 #define MPIDR_AFFLVL2_VAL(mpidr) \ 52 (((mpidr) >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK) 53 #define MPIDR_AFFLVL3_VAL(mpidr) \ 54 (((mpidr) >> MPIDR_AFF3_SHIFT) & MPIDR_AFFLVL_MASK) 55 /* 56 * The MPIDR_MAX_AFFLVL count starts from 0. Take care to 57 * add one while using this macro to define array sizes. 58 * TODO: Support only the first 3 affinity levels for now. 59 */ 60 #define MPIDR_MAX_AFFLVL U(2) 61 62 #define MPID_MASK (MPIDR_MT_MASK | \ 63 (MPIDR_AFFLVL_MASK << MPIDR_AFF3_SHIFT) | \ 64 (MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT) | \ 65 (MPIDR_AFFLVL_MASK << MPIDR_AFF1_SHIFT) | \ 66 (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT)) 67 68 #define MPIDR_AFF_ID(mpid, n) \ 69 (((mpid) >> MPIDR_AFF_SHIFT(n)) & MPIDR_AFFLVL_MASK) 70 71 /* 72 * An invalid MPID. This value can be used by functions that return an MPID to 73 * indicate an error. 74 */ 75 #define INVALID_MPID U(0xFFFFFFFF) 76 77 /******************************************************************************* 78 * Definitions for CPU system register interface to GICv3 79 ******************************************************************************/ 80 #define ICC_IGRPEN1_EL1 S3_0_C12_C12_7 81 #define ICC_SGI1R S3_0_C12_C11_5 82 #define ICC_SRE_EL1 S3_0_C12_C12_5 83 #define ICC_SRE_EL2 S3_4_C12_C9_5 84 #define ICC_SRE_EL3 S3_6_C12_C12_5 85 #define ICC_CTLR_EL1 S3_0_C12_C12_4 86 #define ICC_CTLR_EL3 S3_6_C12_C12_4 87 #define ICC_PMR_EL1 S3_0_C4_C6_0 88 #define ICC_RPR_EL1 S3_0_C12_C11_3 89 #define ICC_IGRPEN1_EL3 S3_6_c12_c12_7 90 #define ICC_IGRPEN0_EL1 S3_0_c12_c12_6 91 #define ICC_HPPIR0_EL1 S3_0_c12_c8_2 92 #define ICC_HPPIR1_EL1 S3_0_c12_c12_2 93 #define ICC_IAR0_EL1 S3_0_c12_c8_0 94 #define ICC_IAR1_EL1 S3_0_c12_c12_0 95 #define ICC_EOIR0_EL1 S3_0_c12_c8_1 96 #define ICC_EOIR1_EL1 S3_0_c12_c12_1 97 #define ICC_SGI0R_EL1 S3_0_c12_c11_7 98 99 /******************************************************************************* 100 * Definitions for EL2 system registers for save/restore routine 101 ******************************************************************************/ 102 #define CNTPOFF_EL2 S3_4_C14_C0_6 103 #define HAFGRTR_EL2 S3_4_C3_C1_6 104 #define HDFGRTR_EL2 S3_4_C3_C1_4 105 #define HDFGWTR_EL2 S3_4_C3_C1_5 106 #define HFGITR_EL2 S3_4_C1_C1_6 107 #define HFGRTR_EL2 S3_4_C1_C1_4 108 #define HFGWTR_EL2 S3_4_C1_C1_5 109 #define ICH_HCR_EL2 S3_4_C12_C11_0 110 #define ICH_VMCR_EL2 S3_4_C12_C11_7 111 #define MPAMVPM0_EL2 S3_4_C10_C6_0 112 #define MPAMVPM1_EL2 S3_4_C10_C6_1 113 #define MPAMVPM2_EL2 S3_4_C10_C6_2 114 #define MPAMVPM3_EL2 S3_4_C10_C6_3 115 #define MPAMVPM4_EL2 S3_4_C10_C6_4 116 #define MPAMVPM5_EL2 S3_4_C10_C6_5 117 #define MPAMVPM6_EL2 S3_4_C10_C6_6 118 #define MPAMVPM7_EL2 S3_4_C10_C6_7 119 #define MPAMVPMV_EL2 S3_4_C10_C4_1 120 #define TRFCR_EL2 S3_4_C1_C2_1 121 #define PMSCR_EL2 S3_4_C9_C9_0 122 #define TFSR_EL2 S3_4_C5_C6_0 123 124 /******************************************************************************* 125 * Generic timer memory mapped registers & offsets 126 ******************************************************************************/ 127 #define CNTCR_OFF U(0x000) 128 #define CNTCV_OFF U(0x008) 129 #define CNTFID_OFF U(0x020) 130 131 #define CNTCR_EN (U(1) << 0) 132 #define CNTCR_HDBG (U(1) << 1) 133 #define CNTCR_FCREQ(x) ((x) << 8) 134 135 /******************************************************************************* 136 * System register bit definitions 137 ******************************************************************************/ 138 /* CLIDR definitions */ 139 #define LOUIS_SHIFT U(21) 140 #define LOC_SHIFT U(24) 141 #define CTYPE_SHIFT(n) U(3 * (n - 1)) 142 #define CLIDR_FIELD_WIDTH U(3) 143 144 /* CSSELR definitions */ 145 #define LEVEL_SHIFT U(1) 146 147 /* Data cache set/way op type defines */ 148 #define DCISW U(0x0) 149 #define DCCISW U(0x1) 150 #if ERRATA_A53_827319 151 #define DCCSW DCCISW 152 #else 153 #define DCCSW U(0x2) 154 #endif 155 156 /* ID_AA64PFR0_EL1 definitions */ 157 #define ID_AA64PFR0_EL0_SHIFT U(0) 158 #define ID_AA64PFR0_EL1_SHIFT U(4) 159 #define ID_AA64PFR0_EL2_SHIFT U(8) 160 #define ID_AA64PFR0_EL3_SHIFT U(12) 161 162 #define ID_AA64PFR0_AMU_SHIFT U(44) 163 #define ID_AA64PFR0_AMU_MASK ULL(0xf) 164 #define ID_AA64PFR0_AMU_NOT_SUPPORTED U(0x0) 165 #define ID_AA64PFR0_AMU_V1 ULL(0x1) 166 #define ID_AA64PFR0_AMU_V1P1 U(0x2) 167 168 #define ID_AA64PFR0_ELX_MASK ULL(0xf) 169 170 #define ID_AA64PFR0_GIC_SHIFT U(24) 171 #define ID_AA64PFR0_GIC_WIDTH U(4) 172 #define ID_AA64PFR0_GIC_MASK ULL(0xf) 173 174 #define ID_AA64PFR0_SVE_SHIFT U(32) 175 #define ID_AA64PFR0_SVE_MASK ULL(0xf) 176 #define ID_AA64PFR0_SVE_SUPPORTED ULL(0x1) 177 #define ID_AA64PFR0_SVE_LENGTH U(4) 178 179 #define ID_AA64PFR0_SEL2_SHIFT U(36) 180 #define ID_AA64PFR0_SEL2_MASK ULL(0xf) 181 182 #define ID_AA64PFR0_MPAM_SHIFT U(40) 183 #define ID_AA64PFR0_MPAM_MASK ULL(0xf) 184 185 #define ID_AA64PFR0_DIT_SHIFT U(48) 186 #define ID_AA64PFR0_DIT_MASK ULL(0xf) 187 #define ID_AA64PFR0_DIT_LENGTH U(4) 188 #define ID_AA64PFR0_DIT_SUPPORTED U(1) 189 190 #define ID_AA64PFR0_CSV2_SHIFT U(56) 191 #define ID_AA64PFR0_CSV2_MASK ULL(0xf) 192 #define ID_AA64PFR0_CSV2_LENGTH U(4) 193 #define ID_AA64PFR0_CSV2_2_SUPPORTED ULL(0x2) 194 195 #define ID_AA64PFR0_FEAT_RME_SHIFT U(52) 196 #define ID_AA64PFR0_FEAT_RME_MASK ULL(0xf) 197 #define ID_AA64PFR0_FEAT_RME_LENGTH U(4) 198 #define ID_AA64PFR0_FEAT_RME_NOT_SUPPORTED U(0) 199 #define ID_AA64PFR0_FEAT_RME_V1 U(1) 200 201 #define ID_AA64PFR0_RAS_SHIFT U(28) 202 #define ID_AA64PFR0_RAS_MASK ULL(0xf) 203 #define ID_AA64PFR0_RAS_NOT_SUPPORTED ULL(0x0) 204 #define ID_AA64PFR0_RAS_LENGTH U(4) 205 206 /* Exception level handling */ 207 #define EL_IMPL_NONE ULL(0) 208 #define EL_IMPL_A64ONLY ULL(1) 209 #define EL_IMPL_A64_A32 ULL(2) 210 211 /* ID_AA64DFR0_EL1.TraceVer definitions */ 212 #define ID_AA64DFR0_TRACEVER_SHIFT U(4) 213 #define ID_AA64DFR0_TRACEVER_MASK ULL(0xf) 214 #define ID_AA64DFR0_TRACEVER_SUPPORTED ULL(1) 215 #define ID_AA64DFR0_TRACEVER_LENGTH U(4) 216 #define ID_AA64DFR0_TRACEFILT_SHIFT U(40) 217 #define ID_AA64DFR0_TRACEFILT_MASK U(0xf) 218 #define ID_AA64DFR0_TRACEFILT_SUPPORTED U(1) 219 #define ID_AA64DFR0_TRACEFILT_LENGTH U(4) 220 221 /* ID_AA64DFR0_EL1.PMS definitions (for ARMv8.2+) */ 222 #define ID_AA64DFR0_PMS_SHIFT U(32) 223 #define ID_AA64DFR0_PMS_MASK ULL(0xf) 224 #define ID_AA64DFR0_SPE_SUPPORTED ULL(0x1) 225 #define ID_AA64DFR0_SPE_NOT_SUPPORTED ULL(0x0) 226 227 /* ID_AA64DFR0_EL1.TraceBuffer definitions */ 228 #define ID_AA64DFR0_TRACEBUFFER_SHIFT U(44) 229 #define ID_AA64DFR0_TRACEBUFFER_MASK ULL(0xf) 230 #define ID_AA64DFR0_TRACEBUFFER_SUPPORTED ULL(1) 231 232 /* ID_AA64DFR0_EL1.MTPMU definitions (for ARMv8.6+) */ 233 #define ID_AA64DFR0_MTPMU_SHIFT U(48) 234 #define ID_AA64DFR0_MTPMU_MASK ULL(0xf) 235 #define ID_AA64DFR0_MTPMU_SUPPORTED ULL(1) 236 237 /* ID_AA64DFR0_EL1.BRBE definitions */ 238 #define ID_AA64DFR0_BRBE_SHIFT U(52) 239 #define ID_AA64DFR0_BRBE_MASK ULL(0xf) 240 #define ID_AA64DFR0_BRBE_SUPPORTED ULL(1) 241 242 /* ID_AA64ISAR0_EL1 definitions */ 243 #define ID_AA64ISAR0_RNDR_SHIFT U(60) 244 #define ID_AA64ISAR0_RNDR_MASK ULL(0xf) 245 246 /* ID_AA64ISAR1_EL1 definitions */ 247 #define ID_AA64ISAR1_EL1 S3_0_C0_C6_1 248 249 #define ID_AA64ISAR1_GPI_SHIFT U(28) 250 #define ID_AA64ISAR1_GPI_MASK ULL(0xf) 251 #define ID_AA64ISAR1_GPA_SHIFT U(24) 252 #define ID_AA64ISAR1_GPA_MASK ULL(0xf) 253 254 #define ID_AA64ISAR1_API_SHIFT U(8) 255 #define ID_AA64ISAR1_API_MASK ULL(0xf) 256 #define ID_AA64ISAR1_APA_SHIFT U(4) 257 #define ID_AA64ISAR1_APA_MASK ULL(0xf) 258 259 #define ID_AA64ISAR1_SB_SHIFT U(36) 260 #define ID_AA64ISAR1_SB_MASK ULL(0xf) 261 #define ID_AA64ISAR1_SB_SUPPORTED ULL(0x1) 262 #define ID_AA64ISAR1_SB_NOT_SUPPORTED ULL(0x0) 263 264 /* ID_AA64MMFR0_EL1 definitions */ 265 #define ID_AA64MMFR0_EL1_PARANGE_SHIFT U(0) 266 #define ID_AA64MMFR0_EL1_PARANGE_MASK ULL(0xf) 267 268 #define PARANGE_0000 U(32) 269 #define PARANGE_0001 U(36) 270 #define PARANGE_0010 U(40) 271 #define PARANGE_0011 U(42) 272 #define PARANGE_0100 U(44) 273 #define PARANGE_0101 U(48) 274 #define PARANGE_0110 U(52) 275 276 #define ID_AA64MMFR0_EL1_ECV_SHIFT U(60) 277 #define ID_AA64MMFR0_EL1_ECV_MASK ULL(0xf) 278 #define ID_AA64MMFR0_EL1_ECV_NOT_SUPPORTED ULL(0x0) 279 #define ID_AA64MMFR0_EL1_ECV_SUPPORTED ULL(0x1) 280 #define ID_AA64MMFR0_EL1_ECV_SELF_SYNCH ULL(0x2) 281 282 #define ID_AA64MMFR0_EL1_FGT_SHIFT U(56) 283 #define ID_AA64MMFR0_EL1_FGT_MASK ULL(0xf) 284 #define ID_AA64MMFR0_EL1_FGT_SUPPORTED ULL(0x1) 285 #define ID_AA64MMFR0_EL1_FGT_NOT_SUPPORTED ULL(0x0) 286 287 #define ID_AA64MMFR0_EL1_TGRAN4_SHIFT U(28) 288 #define ID_AA64MMFR0_EL1_TGRAN4_MASK ULL(0xf) 289 #define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED ULL(0x0) 290 #define ID_AA64MMFR0_EL1_TGRAN4_NOT_SUPPORTED ULL(0xf) 291 292 #define ID_AA64MMFR0_EL1_TGRAN64_SHIFT U(24) 293 #define ID_AA64MMFR0_EL1_TGRAN64_MASK ULL(0xf) 294 #define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED ULL(0x0) 295 #define ID_AA64MMFR0_EL1_TGRAN64_NOT_SUPPORTED ULL(0xf) 296 297 #define ID_AA64MMFR0_EL1_TGRAN16_SHIFT U(20) 298 #define ID_AA64MMFR0_EL1_TGRAN16_MASK ULL(0xf) 299 #define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED ULL(0x1) 300 #define ID_AA64MMFR0_EL1_TGRAN16_NOT_SUPPORTED ULL(0x0) 301 302 /* ID_AA64MMFR1_EL1 definitions */ 303 #define ID_AA64MMFR1_EL1_TWED_SHIFT U(32) 304 #define ID_AA64MMFR1_EL1_TWED_MASK ULL(0xf) 305 #define ID_AA64MMFR1_EL1_TWED_SUPPORTED ULL(0x1) 306 #define ID_AA64MMFR1_EL1_TWED_NOT_SUPPORTED ULL(0x0) 307 308 #define ID_AA64MMFR1_EL1_PAN_SHIFT U(20) 309 #define ID_AA64MMFR1_EL1_PAN_MASK ULL(0xf) 310 #define ID_AA64MMFR1_EL1_PAN_NOT_SUPPORTED ULL(0x0) 311 #define ID_AA64MMFR1_EL1_PAN_SUPPORTED ULL(0x1) 312 #define ID_AA64MMFR1_EL1_PAN2_SUPPORTED ULL(0x2) 313 #define ID_AA64MMFR1_EL1_PAN3_SUPPORTED ULL(0x3) 314 315 #define ID_AA64MMFR1_EL1_VHE_SHIFT U(8) 316 #define ID_AA64MMFR1_EL1_VHE_MASK ULL(0xf) 317 318 #define ID_AA64MMFR1_EL1_HCX_SHIFT U(40) 319 #define ID_AA64MMFR1_EL1_HCX_MASK ULL(0xf) 320 #define ID_AA64MMFR1_EL1_HCX_SUPPORTED ULL(0x1) 321 #define ID_AA64MMFR1_EL1_HCX_NOT_SUPPORTED ULL(0x0) 322 323 /* ID_AA64MMFR2_EL1 definitions */ 324 #define ID_AA64MMFR2_EL1 S3_0_C0_C7_2 325 326 #define ID_AA64MMFR2_EL1_ST_SHIFT U(28) 327 #define ID_AA64MMFR2_EL1_ST_MASK ULL(0xf) 328 329 #define ID_AA64MMFR2_EL1_CCIDX_SHIFT U(20) 330 #define ID_AA64MMFR2_EL1_CCIDX_MASK ULL(0xf) 331 #define ID_AA64MMFR2_EL1_CCIDX_LENGTH U(4) 332 333 #define ID_AA64MMFR2_EL1_CNP_SHIFT U(0) 334 #define ID_AA64MMFR2_EL1_CNP_MASK ULL(0xf) 335 336 #define ID_AA64MMFR2_EL1_NV_SHIFT U(24) 337 #define ID_AA64MMFR2_EL1_NV_MASK ULL(0xf) 338 #define ID_AA64MMFR2_EL1_NV_NOT_SUPPORTED ULL(0x0) 339 #define ID_AA64MMFR2_EL1_NV_SUPPORTED ULL(0x1) 340 #define ID_AA64MMFR2_EL1_NV2_SUPPORTED ULL(0x2) 341 342 /* ID_AA64PFR1_EL1 definitions */ 343 #define ID_AA64PFR1_EL1_SSBS_SHIFT U(4) 344 #define ID_AA64PFR1_EL1_SSBS_MASK ULL(0xf) 345 346 #define SSBS_UNAVAILABLE ULL(0) /* No architectural SSBS support */ 347 348 #define ID_AA64PFR1_EL1_BT_SHIFT U(0) 349 #define ID_AA64PFR1_EL1_BT_MASK ULL(0xf) 350 351 #define BTI_IMPLEMENTED ULL(1) /* The BTI mechanism is implemented */ 352 353 #define ID_AA64PFR1_EL1_MTE_SHIFT U(8) 354 #define ID_AA64PFR1_EL1_MTE_MASK ULL(0xf) 355 356 #define ID_AA64PFR1_EL1_RNDR_TRAP_SHIFT U(28) 357 #define ID_AA64PFR1_EL1_RNDR_TRAP_MASK U(0xf) 358 359 #define ID_AA64PFR1_EL1_RNG_TRAP_SUPPORTED ULL(0x1) 360 #define ID_AA64PFR1_EL1_RNG_TRAP_NOT_SUPPORTED ULL(0x0) 361 362 /* Memory Tagging Extension is not implemented */ 363 #define MTE_UNIMPLEMENTED U(0) 364 /* FEAT_MTE: MTE instructions accessible at EL0 are implemented */ 365 #define MTE_IMPLEMENTED_EL0 U(1) 366 /* FEAT_MTE2: Full MTE is implemented */ 367 #define MTE_IMPLEMENTED_ELX U(2) 368 /* 369 * FEAT_MTE3: MTE is implemented with support for 370 * asymmetric Tag Check Fault handling 371 */ 372 #define MTE_IMPLEMENTED_ASY U(3) 373 374 #define ID_AA64PFR1_MPAM_FRAC_SHIFT ULL(16) 375 #define ID_AA64PFR1_MPAM_FRAC_MASK ULL(0xf) 376 377 #define ID_AA64PFR1_EL1_SME_SHIFT U(24) 378 #define ID_AA64PFR1_EL1_SME_MASK ULL(0xf) 379 380 /* ID_PFR1_EL1 definitions */ 381 #define ID_PFR1_VIRTEXT_SHIFT U(12) 382 #define ID_PFR1_VIRTEXT_MASK U(0xf) 383 #define GET_VIRT_EXT(id) (((id) >> ID_PFR1_VIRTEXT_SHIFT) \ 384 & ID_PFR1_VIRTEXT_MASK) 385 386 /* SCTLR definitions */ 387 #define SCTLR_EL2_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ 388 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \ 389 (U(1) << 11) | (U(1) << 5) | (U(1) << 4)) 390 391 #define SCTLR_EL1_RES1 ((UL(1) << 29) | (UL(1) << 28) | (UL(1) << 23) | \ 392 (UL(1) << 22) | (UL(1) << 20) | (UL(1) << 11)) 393 394 #define SCTLR_AARCH32_EL1_RES1 \ 395 ((U(1) << 23) | (U(1) << 22) | (U(1) << 11) | \ 396 (U(1) << 4) | (U(1) << 3)) 397 398 #define SCTLR_EL3_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ 399 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \ 400 (U(1) << 11) | (U(1) << 5) | (U(1) << 4)) 401 402 #define SCTLR_M_BIT (ULL(1) << 0) 403 #define SCTLR_A_BIT (ULL(1) << 1) 404 #define SCTLR_C_BIT (ULL(1) << 2) 405 #define SCTLR_SA_BIT (ULL(1) << 3) 406 #define SCTLR_SA0_BIT (ULL(1) << 4) 407 #define SCTLR_CP15BEN_BIT (ULL(1) << 5) 408 #define SCTLR_nAA_BIT (ULL(1) << 6) 409 #define SCTLR_ITD_BIT (ULL(1) << 7) 410 #define SCTLR_SED_BIT (ULL(1) << 8) 411 #define SCTLR_UMA_BIT (ULL(1) << 9) 412 #define SCTLR_EnRCTX_BIT (ULL(1) << 10) 413 #define SCTLR_EOS_BIT (ULL(1) << 11) 414 #define SCTLR_I_BIT (ULL(1) << 12) 415 #define SCTLR_EnDB_BIT (ULL(1) << 13) 416 #define SCTLR_DZE_BIT (ULL(1) << 14) 417 #define SCTLR_UCT_BIT (ULL(1) << 15) 418 #define SCTLR_NTWI_BIT (ULL(1) << 16) 419 #define SCTLR_NTWE_BIT (ULL(1) << 18) 420 #define SCTLR_WXN_BIT (ULL(1) << 19) 421 #define SCTLR_TSCXT_BIT (ULL(1) << 20) 422 #define SCTLR_IESB_BIT (ULL(1) << 21) 423 #define SCTLR_EIS_BIT (ULL(1) << 22) 424 #define SCTLR_SPAN_BIT (ULL(1) << 23) 425 #define SCTLR_E0E_BIT (ULL(1) << 24) 426 #define SCTLR_EE_BIT (ULL(1) << 25) 427 #define SCTLR_UCI_BIT (ULL(1) << 26) 428 #define SCTLR_EnDA_BIT (ULL(1) << 27) 429 #define SCTLR_nTLSMD_BIT (ULL(1) << 28) 430 #define SCTLR_LSMAOE_BIT (ULL(1) << 29) 431 #define SCTLR_EnIB_BIT (ULL(1) << 30) 432 #define SCTLR_EnIA_BIT (ULL(1) << 31) 433 #define SCTLR_BT0_BIT (ULL(1) << 35) 434 #define SCTLR_BT1_BIT (ULL(1) << 36) 435 #define SCTLR_BT_BIT (ULL(1) << 36) 436 #define SCTLR_ITFSB_BIT (ULL(1) << 37) 437 #define SCTLR_TCF0_SHIFT U(38) 438 #define SCTLR_TCF0_MASK ULL(3) 439 #define SCTLR_ENTP2_BIT (ULL(1) << 60) 440 441 /* Tag Check Faults in EL0 have no effect on the PE */ 442 #define SCTLR_TCF0_NO_EFFECT U(0) 443 /* Tag Check Faults in EL0 cause a synchronous exception */ 444 #define SCTLR_TCF0_SYNC U(1) 445 /* Tag Check Faults in EL0 are asynchronously accumulated */ 446 #define SCTLR_TCF0_ASYNC U(2) 447 /* 448 * Tag Check Faults in EL0 cause a synchronous exception on reads, 449 * and are asynchronously accumulated on writes 450 */ 451 #define SCTLR_TCF0_SYNCR_ASYNCW U(3) 452 453 #define SCTLR_TCF_SHIFT U(40) 454 #define SCTLR_TCF_MASK ULL(3) 455 456 /* Tag Check Faults in EL1 have no effect on the PE */ 457 #define SCTLR_TCF_NO_EFFECT U(0) 458 /* Tag Check Faults in EL1 cause a synchronous exception */ 459 #define SCTLR_TCF_SYNC U(1) 460 /* Tag Check Faults in EL1 are asynchronously accumulated */ 461 #define SCTLR_TCF_ASYNC U(2) 462 /* 463 * Tag Check Faults in EL1 cause a synchronous exception on reads, 464 * and are asynchronously accumulated on writes 465 */ 466 #define SCTLR_TCF_SYNCR_ASYNCW U(3) 467 468 #define SCTLR_ATA0_BIT (ULL(1) << 42) 469 #define SCTLR_ATA_BIT (ULL(1) << 43) 470 #define SCTLR_DSSBS_SHIFT U(44) 471 #define SCTLR_DSSBS_BIT (ULL(1) << SCTLR_DSSBS_SHIFT) 472 #define SCTLR_TWEDEn_BIT (ULL(1) << 45) 473 #define SCTLR_TWEDEL_SHIFT U(46) 474 #define SCTLR_TWEDEL_MASK ULL(0xf) 475 #define SCTLR_EnASR_BIT (ULL(1) << 54) 476 #define SCTLR_EnAS0_BIT (ULL(1) << 55) 477 #define SCTLR_EnALS_BIT (ULL(1) << 56) 478 #define SCTLR_EPAN_BIT (ULL(1) << 57) 479 #define SCTLR_RESET_VAL SCTLR_EL3_RES1 480 481 /* CPACR_EL1 definitions */ 482 #define CPACR_EL1_FPEN(x) ((x) << 20) 483 #define CPACR_EL1_FP_TRAP_EL0 UL(0x1) 484 #define CPACR_EL1_FP_TRAP_ALL UL(0x2) 485 #define CPACR_EL1_FP_TRAP_NONE UL(0x3) 486 487 /* SCR definitions */ 488 #define SCR_RES1_BITS ((U(1) << 4) | (U(1) << 5)) 489 #define SCR_NSE_SHIFT U(62) 490 #define SCR_NSE_BIT (ULL(1) << SCR_NSE_SHIFT) 491 #define SCR_GPF_BIT (UL(1) << 48) 492 #define SCR_TWEDEL_SHIFT U(30) 493 #define SCR_TWEDEL_MASK ULL(0xf) 494 #define SCR_TRNDR_BIT (UL(1) << 40) 495 #define SCR_HXEn_BIT (UL(1) << 38) 496 #define SCR_ENTP2_SHIFT U(41) 497 #define SCR_ENTP2_BIT (UL(1) << SCR_ENTP2_SHIFT) 498 #define SCR_AMVOFFEN_SHIFT U(35) 499 #define SCR_AMVOFFEN_BIT (UL(1) << SCR_AMVOFFEN_SHIFT) 500 #define SCR_TWEDEn_BIT (UL(1) << 29) 501 #define SCR_ECVEN_BIT (UL(1) << 28) 502 #define SCR_FGTEN_BIT (UL(1) << 27) 503 #define SCR_ATA_BIT (UL(1) << 26) 504 #define SCR_EnSCXT_BIT (UL(1) << 25) 505 #define SCR_FIEN_BIT (UL(1) << 21) 506 #define SCR_EEL2_BIT (UL(1) << 18) 507 #define SCR_API_BIT (UL(1) << 17) 508 #define SCR_APK_BIT (UL(1) << 16) 509 #define SCR_TERR_BIT (UL(1) << 15) 510 #define SCR_TWE_BIT (UL(1) << 13) 511 #define SCR_TWI_BIT (UL(1) << 12) 512 #define SCR_ST_BIT (UL(1) << 11) 513 #define SCR_RW_BIT (UL(1) << 10) 514 #define SCR_SIF_BIT (UL(1) << 9) 515 #define SCR_HCE_BIT (UL(1) << 8) 516 #define SCR_SMD_BIT (UL(1) << 7) 517 #define SCR_EA_BIT (UL(1) << 3) 518 #define SCR_FIQ_BIT (UL(1) << 2) 519 #define SCR_IRQ_BIT (UL(1) << 1) 520 #define SCR_NS_BIT (UL(1) << 0) 521 #define SCR_VALID_BIT_MASK U(0x24000002F8F) 522 #define SCR_RESET_VAL SCR_RES1_BITS 523 524 /* MDCR_EL3 definitions */ 525 #define MDCR_EnPMSN_BIT (ULL(1) << 36) 526 #define MDCR_MPMX_BIT (ULL(1) << 35) 527 #define MDCR_MCCD_BIT (ULL(1) << 34) 528 #define MDCR_SBRBE_SHIFT U(32) 529 #define MDCR_SBRBE_MASK ULL(0x3) 530 #define MDCR_NSTB(x) ((x) << 24) 531 #define MDCR_NSTB_EL1 ULL(0x3) 532 #define MDCR_NSTBE (ULL(1) << 26) 533 #define MDCR_MTPME_BIT (ULL(1) << 28) 534 #define MDCR_TDCC_BIT (ULL(1) << 27) 535 #define MDCR_SCCD_BIT (ULL(1) << 23) 536 #define MDCR_EPMAD_BIT (ULL(1) << 21) 537 #define MDCR_EDAD_BIT (ULL(1) << 20) 538 #define MDCR_TTRF_BIT (ULL(1) << 19) 539 #define MDCR_STE_BIT (ULL(1) << 18) 540 #define MDCR_SPME_BIT (ULL(1) << 17) 541 #define MDCR_SDD_BIT (ULL(1) << 16) 542 #define MDCR_SPD32(x) ((x) << 14) 543 #define MDCR_SPD32_LEGACY ULL(0x0) 544 #define MDCR_SPD32_DISABLE ULL(0x2) 545 #define MDCR_SPD32_ENABLE ULL(0x3) 546 #define MDCR_NSPB(x) ((x) << 12) 547 #define MDCR_NSPB_EL1 ULL(0x3) 548 #define MDCR_TDOSA_BIT (ULL(1) << 10) 549 #define MDCR_TDA_BIT (ULL(1) << 9) 550 #define MDCR_TPM_BIT (ULL(1) << 6) 551 #define MDCR_EL3_RESET_VAL ULL(0x0) 552 553 /* MDCR_EL2 definitions */ 554 #define MDCR_EL2_MTPME (U(1) << 28) 555 #define MDCR_EL2_HLP (U(1) << 26) 556 #define MDCR_EL2_E2TB(x) ((x) << 24) 557 #define MDCR_EL2_E2TB_EL1 U(0x3) 558 #define MDCR_EL2_HCCD (U(1) << 23) 559 #define MDCR_EL2_TTRF (U(1) << 19) 560 #define MDCR_EL2_HPMD (U(1) << 17) 561 #define MDCR_EL2_TPMS (U(1) << 14) 562 #define MDCR_EL2_E2PB(x) ((x) << 12) 563 #define MDCR_EL2_E2PB_EL1 U(0x3) 564 #define MDCR_EL2_TDRA_BIT (U(1) << 11) 565 #define MDCR_EL2_TDOSA_BIT (U(1) << 10) 566 #define MDCR_EL2_TDA_BIT (U(1) << 9) 567 #define MDCR_EL2_TDE_BIT (U(1) << 8) 568 #define MDCR_EL2_HPME_BIT (U(1) << 7) 569 #define MDCR_EL2_TPM_BIT (U(1) << 6) 570 #define MDCR_EL2_TPMCR_BIT (U(1) << 5) 571 #define MDCR_EL2_RESET_VAL U(0x0) 572 573 /* HSTR_EL2 definitions */ 574 #define HSTR_EL2_RESET_VAL U(0x0) 575 #define HSTR_EL2_T_MASK U(0xff) 576 577 /* CNTHP_CTL_EL2 definitions */ 578 #define CNTHP_CTL_ENABLE_BIT (U(1) << 0) 579 #define CNTHP_CTL_RESET_VAL U(0x0) 580 581 /* VTTBR_EL2 definitions */ 582 #define VTTBR_RESET_VAL ULL(0x0) 583 #define VTTBR_VMID_MASK ULL(0xff) 584 #define VTTBR_VMID_SHIFT U(48) 585 #define VTTBR_BADDR_MASK ULL(0xffffffffffff) 586 #define VTTBR_BADDR_SHIFT U(0) 587 588 /* HCR definitions */ 589 #define HCR_RESET_VAL ULL(0x0) 590 #define HCR_AMVOFFEN_SHIFT U(51) 591 #define HCR_AMVOFFEN_BIT (ULL(1) << HCR_AMVOFFEN_SHIFT) 592 #define HCR_TEA_BIT (ULL(1) << 47) 593 #define HCR_API_BIT (ULL(1) << 41) 594 #define HCR_APK_BIT (ULL(1) << 40) 595 #define HCR_E2H_BIT (ULL(1) << 34) 596 #define HCR_HCD_BIT (ULL(1) << 29) 597 #define HCR_TGE_BIT (ULL(1) << 27) 598 #define HCR_RW_SHIFT U(31) 599 #define HCR_RW_BIT (ULL(1) << HCR_RW_SHIFT) 600 #define HCR_TWE_BIT (ULL(1) << 14) 601 #define HCR_TWI_BIT (ULL(1) << 13) 602 #define HCR_AMO_BIT (ULL(1) << 5) 603 #define HCR_IMO_BIT (ULL(1) << 4) 604 #define HCR_FMO_BIT (ULL(1) << 3) 605 606 /* ISR definitions */ 607 #define ISR_A_SHIFT U(8) 608 #define ISR_I_SHIFT U(7) 609 #define ISR_F_SHIFT U(6) 610 611 /* CNTHCTL_EL2 definitions */ 612 #define CNTHCTL_RESET_VAL U(0x0) 613 #define EVNTEN_BIT (U(1) << 2) 614 #define EL1PCEN_BIT (U(1) << 1) 615 #define EL1PCTEN_BIT (U(1) << 0) 616 617 /* CNTKCTL_EL1 definitions */ 618 #define EL0PTEN_BIT (U(1) << 9) 619 #define EL0VTEN_BIT (U(1) << 8) 620 #define EL0PCTEN_BIT (U(1) << 0) 621 #define EL0VCTEN_BIT (U(1) << 1) 622 #define EVNTEN_BIT (U(1) << 2) 623 #define EVNTDIR_BIT (U(1) << 3) 624 #define EVNTI_SHIFT U(4) 625 #define EVNTI_MASK U(0xf) 626 627 /* CPTR_EL3 definitions */ 628 #define TCPAC_BIT (U(1) << 31) 629 #define TAM_SHIFT U(30) 630 #define TAM_BIT (U(1) << TAM_SHIFT) 631 #define TTA_BIT (U(1) << 20) 632 #define ESM_BIT (U(1) << 12) 633 #define TFP_BIT (U(1) << 10) 634 #define CPTR_EZ_BIT (U(1) << 8) 635 #define CPTR_EL3_RESET_VAL ((TCPAC_BIT | TAM_BIT | TTA_BIT | TFP_BIT) & \ 636 ~(CPTR_EZ_BIT | ESM_BIT)) 637 638 /* CPTR_EL2 definitions */ 639 #define CPTR_EL2_RES1 ((U(1) << 13) | (U(1) << 12) | (U(0x3ff))) 640 #define CPTR_EL2_TCPAC_BIT (U(1) << 31) 641 #define CPTR_EL2_TAM_SHIFT U(30) 642 #define CPTR_EL2_TAM_BIT (U(1) << CPTR_EL2_TAM_SHIFT) 643 #define CPTR_EL2_SMEN_MASK ULL(0x3) 644 #define CPTR_EL2_SMEN_SHIFT U(24) 645 #define CPTR_EL2_TTA_BIT (U(1) << 20) 646 #define CPTR_EL2_TSM_BIT (U(1) << 12) 647 #define CPTR_EL2_TFP_BIT (U(1) << 10) 648 #define CPTR_EL2_TZ_BIT (U(1) << 8) 649 #define CPTR_EL2_RESET_VAL CPTR_EL2_RES1 650 651 /* VTCR_EL2 definitions */ 652 #define VTCR_RESET_VAL U(0x0) 653 #define VTCR_EL2_MSA (U(1) << 31) 654 655 /* CPSR/SPSR definitions */ 656 #define DAIF_FIQ_BIT (U(1) << 0) 657 #define DAIF_IRQ_BIT (U(1) << 1) 658 #define DAIF_ABT_BIT (U(1) << 2) 659 #define DAIF_DBG_BIT (U(1) << 3) 660 #define SPSR_DAIF_SHIFT U(6) 661 #define SPSR_DAIF_MASK U(0xf) 662 663 #define SPSR_AIF_SHIFT U(6) 664 #define SPSR_AIF_MASK U(0x7) 665 666 #define SPSR_E_SHIFT U(9) 667 #define SPSR_E_MASK U(0x1) 668 #define SPSR_E_LITTLE U(0x0) 669 #define SPSR_E_BIG U(0x1) 670 671 #define SPSR_T_SHIFT U(5) 672 #define SPSR_T_MASK U(0x1) 673 #define SPSR_T_ARM U(0x0) 674 #define SPSR_T_THUMB U(0x1) 675 676 #define SPSR_M_SHIFT U(4) 677 #define SPSR_M_MASK U(0x1) 678 #define SPSR_M_AARCH64 U(0x0) 679 #define SPSR_M_AARCH32 U(0x1) 680 #define SPSR_M_EL2H U(0x9) 681 682 #define SPSR_EL_SHIFT U(2) 683 #define SPSR_EL_WIDTH U(2) 684 685 #define SPSR_SSBS_SHIFT_AARCH64 U(12) 686 #define SPSR_SSBS_BIT_AARCH64 (ULL(1) << SPSR_SSBS_SHIFT_AARCH64) 687 #define SPSR_SSBS_SHIFT_AARCH32 U(23) 688 #define SPSR_SSBS_BIT_AARCH32 (ULL(1) << SPSR_SSBS_SHIFT_AARCH32) 689 690 #define SPSR_PAN_BIT BIT_64(22) 691 692 #define SPSR_DIT_BIT BIT(24) 693 694 #define SPSR_TCO_BIT_AARCH64 BIT_64(25) 695 696 #define DISABLE_ALL_EXCEPTIONS \ 697 (DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT | DAIF_DBG_BIT) 698 699 #define DISABLE_INTERRUPTS (DAIF_FIQ_BIT | DAIF_IRQ_BIT) 700 701 /* 702 * RMR_EL3 definitions 703 */ 704 #define RMR_EL3_RR_BIT (U(1) << 1) 705 #define RMR_EL3_AA64_BIT (U(1) << 0) 706 707 /* 708 * HI-VECTOR address for AArch32 state 709 */ 710 #define HI_VECTOR_BASE U(0xFFFF0000) 711 712 /* 713 * TCR defintions 714 */ 715 #define TCR_EL3_RES1 ((ULL(1) << 31) | (ULL(1) << 23)) 716 #define TCR_EL2_RES1 ((ULL(1) << 31) | (ULL(1) << 23)) 717 #define TCR_EL1_IPS_SHIFT U(32) 718 #define TCR_EL2_PS_SHIFT U(16) 719 #define TCR_EL3_PS_SHIFT U(16) 720 721 #define TCR_TxSZ_MIN ULL(16) 722 #define TCR_TxSZ_MAX ULL(39) 723 #define TCR_TxSZ_MAX_TTST ULL(48) 724 725 #define TCR_T0SZ_SHIFT U(0) 726 #define TCR_T1SZ_SHIFT U(16) 727 728 /* (internal) physical address size bits in EL3/EL1 */ 729 #define TCR_PS_BITS_4GB ULL(0x0) 730 #define TCR_PS_BITS_64GB ULL(0x1) 731 #define TCR_PS_BITS_1TB ULL(0x2) 732 #define TCR_PS_BITS_4TB ULL(0x3) 733 #define TCR_PS_BITS_16TB ULL(0x4) 734 #define TCR_PS_BITS_256TB ULL(0x5) 735 736 #define ADDR_MASK_48_TO_63 ULL(0xFFFF000000000000) 737 #define ADDR_MASK_44_TO_47 ULL(0x0000F00000000000) 738 #define ADDR_MASK_42_TO_43 ULL(0x00000C0000000000) 739 #define ADDR_MASK_40_TO_41 ULL(0x0000030000000000) 740 #define ADDR_MASK_36_TO_39 ULL(0x000000F000000000) 741 #define ADDR_MASK_32_TO_35 ULL(0x0000000F00000000) 742 743 #define TCR_RGN_INNER_NC (ULL(0x0) << 8) 744 #define TCR_RGN_INNER_WBA (ULL(0x1) << 8) 745 #define TCR_RGN_INNER_WT (ULL(0x2) << 8) 746 #define TCR_RGN_INNER_WBNA (ULL(0x3) << 8) 747 748 #define TCR_RGN_OUTER_NC (ULL(0x0) << 10) 749 #define TCR_RGN_OUTER_WBA (ULL(0x1) << 10) 750 #define TCR_RGN_OUTER_WT (ULL(0x2) << 10) 751 #define TCR_RGN_OUTER_WBNA (ULL(0x3) << 10) 752 753 #define TCR_SH_NON_SHAREABLE (ULL(0x0) << 12) 754 #define TCR_SH_OUTER_SHAREABLE (ULL(0x2) << 12) 755 #define TCR_SH_INNER_SHAREABLE (ULL(0x3) << 12) 756 757 #define TCR_RGN1_INNER_NC (ULL(0x0) << 24) 758 #define TCR_RGN1_INNER_WBA (ULL(0x1) << 24) 759 #define TCR_RGN1_INNER_WT (ULL(0x2) << 24) 760 #define TCR_RGN1_INNER_WBNA (ULL(0x3) << 24) 761 762 #define TCR_RGN1_OUTER_NC (ULL(0x0) << 26) 763 #define TCR_RGN1_OUTER_WBA (ULL(0x1) << 26) 764 #define TCR_RGN1_OUTER_WT (ULL(0x2) << 26) 765 #define TCR_RGN1_OUTER_WBNA (ULL(0x3) << 26) 766 767 #define TCR_SH1_NON_SHAREABLE (ULL(0x0) << 28) 768 #define TCR_SH1_OUTER_SHAREABLE (ULL(0x2) << 28) 769 #define TCR_SH1_INNER_SHAREABLE (ULL(0x3) << 28) 770 771 #define TCR_TG0_SHIFT U(14) 772 #define TCR_TG0_MASK ULL(3) 773 #define TCR_TG0_4K (ULL(0) << TCR_TG0_SHIFT) 774 #define TCR_TG0_64K (ULL(1) << TCR_TG0_SHIFT) 775 #define TCR_TG0_16K (ULL(2) << TCR_TG0_SHIFT) 776 777 #define TCR_TG1_SHIFT U(30) 778 #define TCR_TG1_MASK ULL(3) 779 #define TCR_TG1_16K (ULL(1) << TCR_TG1_SHIFT) 780 #define TCR_TG1_4K (ULL(2) << TCR_TG1_SHIFT) 781 #define TCR_TG1_64K (ULL(3) << TCR_TG1_SHIFT) 782 783 #define TCR_EPD0_BIT (ULL(1) << 7) 784 #define TCR_EPD1_BIT (ULL(1) << 23) 785 786 #define MODE_SP_SHIFT U(0x0) 787 #define MODE_SP_MASK U(0x1) 788 #define MODE_SP_EL0 U(0x0) 789 #define MODE_SP_ELX U(0x1) 790 791 #define MODE_RW_SHIFT U(0x4) 792 #define MODE_RW_MASK U(0x1) 793 #define MODE_RW_64 U(0x0) 794 #define MODE_RW_32 U(0x1) 795 796 #define MODE_EL_SHIFT U(0x2) 797 #define MODE_EL_MASK U(0x3) 798 #define MODE_EL_WIDTH U(0x2) 799 #define MODE_EL3 U(0x3) 800 #define MODE_EL2 U(0x2) 801 #define MODE_EL1 U(0x1) 802 #define MODE_EL0 U(0x0) 803 804 #define MODE32_SHIFT U(0) 805 #define MODE32_MASK U(0xf) 806 #define MODE32_usr U(0x0) 807 #define MODE32_fiq U(0x1) 808 #define MODE32_irq U(0x2) 809 #define MODE32_svc U(0x3) 810 #define MODE32_mon U(0x6) 811 #define MODE32_abt U(0x7) 812 #define MODE32_hyp U(0xa) 813 #define MODE32_und U(0xb) 814 #define MODE32_sys U(0xf) 815 816 #define GET_RW(mode) (((mode) >> MODE_RW_SHIFT) & MODE_RW_MASK) 817 #define GET_EL(mode) (((mode) >> MODE_EL_SHIFT) & MODE_EL_MASK) 818 #define GET_SP(mode) (((mode) >> MODE_SP_SHIFT) & MODE_SP_MASK) 819 #define GET_M32(mode) (((mode) >> MODE32_SHIFT) & MODE32_MASK) 820 821 #define SPSR_64(el, sp, daif) \ 822 (((MODE_RW_64 << MODE_RW_SHIFT) | \ 823 (((el) & MODE_EL_MASK) << MODE_EL_SHIFT) | \ 824 (((sp) & MODE_SP_MASK) << MODE_SP_SHIFT) | \ 825 (((daif) & SPSR_DAIF_MASK) << SPSR_DAIF_SHIFT)) & \ 826 (~(SPSR_SSBS_BIT_AARCH64))) 827 828 #define SPSR_MODE32(mode, isa, endian, aif) \ 829 (((MODE_RW_32 << MODE_RW_SHIFT) | \ 830 (((mode) & MODE32_MASK) << MODE32_SHIFT) | \ 831 (((isa) & SPSR_T_MASK) << SPSR_T_SHIFT) | \ 832 (((endian) & SPSR_E_MASK) << SPSR_E_SHIFT) | \ 833 (((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT)) & \ 834 (~(SPSR_SSBS_BIT_AARCH32))) 835 836 /* 837 * TTBR Definitions 838 */ 839 #define TTBR_CNP_BIT ULL(0x1) 840 841 /* 842 * CTR_EL0 definitions 843 */ 844 #define CTR_CWG_SHIFT U(24) 845 #define CTR_CWG_MASK U(0xf) 846 #define CTR_ERG_SHIFT U(20) 847 #define CTR_ERG_MASK U(0xf) 848 #define CTR_DMINLINE_SHIFT U(16) 849 #define CTR_DMINLINE_MASK U(0xf) 850 #define CTR_L1IP_SHIFT U(14) 851 #define CTR_L1IP_MASK U(0x3) 852 #define CTR_IMINLINE_SHIFT U(0) 853 #define CTR_IMINLINE_MASK U(0xf) 854 855 #define MAX_CACHE_LINE_SIZE U(0x800) /* 2KB */ 856 857 /* Physical timer control register bit fields shifts and masks */ 858 #define CNTP_CTL_ENABLE_SHIFT U(0) 859 #define CNTP_CTL_IMASK_SHIFT U(1) 860 #define CNTP_CTL_ISTATUS_SHIFT U(2) 861 862 #define CNTP_CTL_ENABLE_MASK U(1) 863 #define CNTP_CTL_IMASK_MASK U(1) 864 #define CNTP_CTL_ISTATUS_MASK U(1) 865 866 /* Physical timer control macros */ 867 #define CNTP_CTL_ENABLE_BIT (U(1) << CNTP_CTL_ENABLE_SHIFT) 868 #define CNTP_CTL_IMASK_BIT (U(1) << CNTP_CTL_IMASK_SHIFT) 869 870 /* Exception Syndrome register bits and bobs */ 871 #define ESR_EC_SHIFT U(26) 872 #define ESR_EC_MASK U(0x3f) 873 #define ESR_EC_LENGTH U(6) 874 #define ESR_ISS_SHIFT U(0) 875 #define ESR_ISS_LENGTH U(25) 876 #define EC_UNKNOWN U(0x0) 877 #define EC_WFE_WFI U(0x1) 878 #define EC_AARCH32_CP15_MRC_MCR U(0x3) 879 #define EC_AARCH32_CP15_MRRC_MCRR U(0x4) 880 #define EC_AARCH32_CP14_MRC_MCR U(0x5) 881 #define EC_AARCH32_CP14_LDC_STC U(0x6) 882 #define EC_FP_SIMD U(0x7) 883 #define EC_AARCH32_CP10_MRC U(0x8) 884 #define EC_AARCH32_CP14_MRRC_MCRR U(0xc) 885 #define EC_ILLEGAL U(0xe) 886 #define EC_AARCH32_SVC U(0x11) 887 #define EC_AARCH32_HVC U(0x12) 888 #define EC_AARCH32_SMC U(0x13) 889 #define EC_AARCH64_SVC U(0x15) 890 #define EC_AARCH64_HVC U(0x16) 891 #define EC_AARCH64_SMC U(0x17) 892 #define EC_AARCH64_SYS U(0x18) 893 #define EC_IABORT_LOWER_EL U(0x20) 894 #define EC_IABORT_CUR_EL U(0x21) 895 #define EC_PC_ALIGN U(0x22) 896 #define EC_DABORT_LOWER_EL U(0x24) 897 #define EC_DABORT_CUR_EL U(0x25) 898 #define EC_SP_ALIGN U(0x26) 899 #define EC_AARCH32_FP U(0x28) 900 #define EC_AARCH64_FP U(0x2c) 901 #define EC_SERROR U(0x2f) 902 #define EC_BRK U(0x3c) 903 904 /* 905 * External Abort bit in Instruction and Data Aborts synchronous exception 906 * syndromes. 907 */ 908 #define ESR_ISS_EABORT_EA_BIT U(9) 909 910 #define EC_BITS(x) (((x) >> ESR_EC_SHIFT) & ESR_EC_MASK) 911 912 /* Reset bit inside the Reset management register for EL3 (RMR_EL3) */ 913 #define RMR_RESET_REQUEST_SHIFT U(0x1) 914 #define RMR_WARM_RESET_CPU (U(1) << RMR_RESET_REQUEST_SHIFT) 915 916 /******************************************************************************* 917 * Definitions of register offsets, fields and macros for CPU system 918 * instructions. 919 ******************************************************************************/ 920 921 #define TLBI_ADDR_SHIFT U(12) 922 #define TLBI_ADDR_MASK ULL(0x00000FFFFFFFFFFF) 923 #define TLBI_ADDR(x) (((x) >> TLBI_ADDR_SHIFT) & TLBI_ADDR_MASK) 924 925 /******************************************************************************* 926 * Definitions of register offsets and fields in the CNTCTLBase Frame of the 927 * system level implementation of the Generic Timer. 928 ******************************************************************************/ 929 #define CNTCTLBASE_CNTFRQ U(0x0) 930 #define CNTNSAR U(0x4) 931 #define CNTNSAR_NS_SHIFT(x) (x) 932 933 #define CNTACR_BASE(x) (U(0x40) + ((x) << 2)) 934 #define CNTACR_RPCT_SHIFT U(0x0) 935 #define CNTACR_RVCT_SHIFT U(0x1) 936 #define CNTACR_RFRQ_SHIFT U(0x2) 937 #define CNTACR_RVOFF_SHIFT U(0x3) 938 #define CNTACR_RWVT_SHIFT U(0x4) 939 #define CNTACR_RWPT_SHIFT U(0x5) 940 941 /******************************************************************************* 942 * Definitions of register offsets and fields in the CNTBaseN Frame of the 943 * system level implementation of the Generic Timer. 944 ******************************************************************************/ 945 /* Physical Count register. */ 946 #define CNTPCT_LO U(0x0) 947 /* Counter Frequency register. */ 948 #define CNTBASEN_CNTFRQ U(0x10) 949 /* Physical Timer CompareValue register. */ 950 #define CNTP_CVAL_LO U(0x20) 951 /* Physical Timer Control register. */ 952 #define CNTP_CTL U(0x2c) 953 954 /* PMCR_EL0 definitions */ 955 #define PMCR_EL0_RESET_VAL U(0x0) 956 #define PMCR_EL0_N_SHIFT U(11) 957 #define PMCR_EL0_N_MASK U(0x1f) 958 #define PMCR_EL0_N_BITS (PMCR_EL0_N_MASK << PMCR_EL0_N_SHIFT) 959 #define PMCR_EL0_LP_BIT (U(1) << 7) 960 #define PMCR_EL0_LC_BIT (U(1) << 6) 961 #define PMCR_EL0_DP_BIT (U(1) << 5) 962 #define PMCR_EL0_X_BIT (U(1) << 4) 963 #define PMCR_EL0_D_BIT (U(1) << 3) 964 #define PMCR_EL0_C_BIT (U(1) << 2) 965 #define PMCR_EL0_P_BIT (U(1) << 1) 966 #define PMCR_EL0_E_BIT (U(1) << 0) 967 968 /******************************************************************************* 969 * Definitions for system register interface to SVE 970 ******************************************************************************/ 971 #define ZCR_EL3 S3_6_C1_C2_0 972 #define ZCR_EL2 S3_4_C1_C2_0 973 974 /* ZCR_EL3 definitions */ 975 #define ZCR_EL3_LEN_MASK U(0xf) 976 977 /* ZCR_EL2 definitions */ 978 #define ZCR_EL2_LEN_MASK U(0xf) 979 980 /******************************************************************************* 981 * Definitions for system register interface to SME as needed in EL3 982 ******************************************************************************/ 983 #define ID_AA64SMFR0_EL1 S3_0_C0_C4_5 984 #define SMCR_EL3 S3_6_C1_C2_6 985 986 /* ID_AA64SMFR0_EL1 definitions */ 987 #define ID_AA64SMFR0_EL1_FA64_BIT (UL(1) << 63) 988 989 /* SMCR_ELx definitions */ 990 #define SMCR_ELX_LEN_SHIFT U(0) 991 #define SMCR_ELX_LEN_MASK U(0x1ff) 992 #define SMCR_ELX_FA64_BIT (U(1) << 31) 993 994 /******************************************************************************* 995 * Definitions of MAIR encodings for device and normal memory 996 ******************************************************************************/ 997 /* 998 * MAIR encodings for device memory attributes. 999 */ 1000 #define MAIR_DEV_nGnRnE ULL(0x0) 1001 #define MAIR_DEV_nGnRE ULL(0x4) 1002 #define MAIR_DEV_nGRE ULL(0x8) 1003 #define MAIR_DEV_GRE ULL(0xc) 1004 1005 /* 1006 * MAIR encodings for normal memory attributes. 1007 * 1008 * Cache Policy 1009 * WT: Write Through 1010 * WB: Write Back 1011 * NC: Non-Cacheable 1012 * 1013 * Transient Hint 1014 * NTR: Non-Transient 1015 * TR: Transient 1016 * 1017 * Allocation Policy 1018 * RA: Read Allocate 1019 * WA: Write Allocate 1020 * RWA: Read and Write Allocate 1021 * NA: No Allocation 1022 */ 1023 #define MAIR_NORM_WT_TR_WA ULL(0x1) 1024 #define MAIR_NORM_WT_TR_RA ULL(0x2) 1025 #define MAIR_NORM_WT_TR_RWA ULL(0x3) 1026 #define MAIR_NORM_NC ULL(0x4) 1027 #define MAIR_NORM_WB_TR_WA ULL(0x5) 1028 #define MAIR_NORM_WB_TR_RA ULL(0x6) 1029 #define MAIR_NORM_WB_TR_RWA ULL(0x7) 1030 #define MAIR_NORM_WT_NTR_NA ULL(0x8) 1031 #define MAIR_NORM_WT_NTR_WA ULL(0x9) 1032 #define MAIR_NORM_WT_NTR_RA ULL(0xa) 1033 #define MAIR_NORM_WT_NTR_RWA ULL(0xb) 1034 #define MAIR_NORM_WB_NTR_NA ULL(0xc) 1035 #define MAIR_NORM_WB_NTR_WA ULL(0xd) 1036 #define MAIR_NORM_WB_NTR_RA ULL(0xe) 1037 #define MAIR_NORM_WB_NTR_RWA ULL(0xf) 1038 1039 #define MAIR_NORM_OUTER_SHIFT U(4) 1040 1041 #define MAKE_MAIR_NORMAL_MEMORY(inner, outer) \ 1042 ((inner) | ((outer) << MAIR_NORM_OUTER_SHIFT)) 1043 1044 /* PAR_EL1 fields */ 1045 #define PAR_F_SHIFT U(0) 1046 #define PAR_F_MASK ULL(0x1) 1047 #define PAR_ADDR_SHIFT U(12) 1048 #define PAR_ADDR_MASK (BIT(40) - ULL(1)) /* 40-bits-wide page address */ 1049 1050 /******************************************************************************* 1051 * Definitions for system register interface to SPE 1052 ******************************************************************************/ 1053 #define PMBLIMITR_EL1 S3_0_C9_C10_0 1054 1055 /******************************************************************************* 1056 * Definitions for system register interface to MPAM 1057 ******************************************************************************/ 1058 #define MPAMIDR_EL1 S3_0_C10_C4_4 1059 #define MPAM2_EL2 S3_4_C10_C5_0 1060 #define MPAMHCR_EL2 S3_4_C10_C4_0 1061 #define MPAM3_EL3 S3_6_C10_C5_0 1062 1063 /******************************************************************************* 1064 * Definitions for system register interface to AMU for FEAT_AMUv1 1065 ******************************************************************************/ 1066 #define AMCR_EL0 S3_3_C13_C2_0 1067 #define AMCFGR_EL0 S3_3_C13_C2_1 1068 #define AMCGCR_EL0 S3_3_C13_C2_2 1069 #define AMUSERENR_EL0 S3_3_C13_C2_3 1070 #define AMCNTENCLR0_EL0 S3_3_C13_C2_4 1071 #define AMCNTENSET0_EL0 S3_3_C13_C2_5 1072 #define AMCNTENCLR1_EL0 S3_3_C13_C3_0 1073 #define AMCNTENSET1_EL0 S3_3_C13_C3_1 1074 1075 /* Activity Monitor Group 0 Event Counter Registers */ 1076 #define AMEVCNTR00_EL0 S3_3_C13_C4_0 1077 #define AMEVCNTR01_EL0 S3_3_C13_C4_1 1078 #define AMEVCNTR02_EL0 S3_3_C13_C4_2 1079 #define AMEVCNTR03_EL0 S3_3_C13_C4_3 1080 1081 /* Activity Monitor Group 0 Event Type Registers */ 1082 #define AMEVTYPER00_EL0 S3_3_C13_C6_0 1083 #define AMEVTYPER01_EL0 S3_3_C13_C6_1 1084 #define AMEVTYPER02_EL0 S3_3_C13_C6_2 1085 #define AMEVTYPER03_EL0 S3_3_C13_C6_3 1086 1087 /* Activity Monitor Group 1 Event Counter Registers */ 1088 #define AMEVCNTR10_EL0 S3_3_C13_C12_0 1089 #define AMEVCNTR11_EL0 S3_3_C13_C12_1 1090 #define AMEVCNTR12_EL0 S3_3_C13_C12_2 1091 #define AMEVCNTR13_EL0 S3_3_C13_C12_3 1092 #define AMEVCNTR14_EL0 S3_3_C13_C12_4 1093 #define AMEVCNTR15_EL0 S3_3_C13_C12_5 1094 #define AMEVCNTR16_EL0 S3_3_C13_C12_6 1095 #define AMEVCNTR17_EL0 S3_3_C13_C12_7 1096 #define AMEVCNTR18_EL0 S3_3_C13_C13_0 1097 #define AMEVCNTR19_EL0 S3_3_C13_C13_1 1098 #define AMEVCNTR1A_EL0 S3_3_C13_C13_2 1099 #define AMEVCNTR1B_EL0 S3_3_C13_C13_3 1100 #define AMEVCNTR1C_EL0 S3_3_C13_C13_4 1101 #define AMEVCNTR1D_EL0 S3_3_C13_C13_5 1102 #define AMEVCNTR1E_EL0 S3_3_C13_C13_6 1103 #define AMEVCNTR1F_EL0 S3_3_C13_C13_7 1104 1105 /* Activity Monitor Group 1 Event Type Registers */ 1106 #define AMEVTYPER10_EL0 S3_3_C13_C14_0 1107 #define AMEVTYPER11_EL0 S3_3_C13_C14_1 1108 #define AMEVTYPER12_EL0 S3_3_C13_C14_2 1109 #define AMEVTYPER13_EL0 S3_3_C13_C14_3 1110 #define AMEVTYPER14_EL0 S3_3_C13_C14_4 1111 #define AMEVTYPER15_EL0 S3_3_C13_C14_5 1112 #define AMEVTYPER16_EL0 S3_3_C13_C14_6 1113 #define AMEVTYPER17_EL0 S3_3_C13_C14_7 1114 #define AMEVTYPER18_EL0 S3_3_C13_C15_0 1115 #define AMEVTYPER19_EL0 S3_3_C13_C15_1 1116 #define AMEVTYPER1A_EL0 S3_3_C13_C15_2 1117 #define AMEVTYPER1B_EL0 S3_3_C13_C15_3 1118 #define AMEVTYPER1C_EL0 S3_3_C13_C15_4 1119 #define AMEVTYPER1D_EL0 S3_3_C13_C15_5 1120 #define AMEVTYPER1E_EL0 S3_3_C13_C15_6 1121 #define AMEVTYPER1F_EL0 S3_3_C13_C15_7 1122 1123 /* AMCNTENSET0_EL0 definitions */ 1124 #define AMCNTENSET0_EL0_Pn_SHIFT U(0) 1125 #define AMCNTENSET0_EL0_Pn_MASK ULL(0xffff) 1126 1127 /* AMCNTENSET1_EL0 definitions */ 1128 #define AMCNTENSET1_EL0_Pn_SHIFT U(0) 1129 #define AMCNTENSET1_EL0_Pn_MASK ULL(0xffff) 1130 1131 /* AMCNTENCLR0_EL0 definitions */ 1132 #define AMCNTENCLR0_EL0_Pn_SHIFT U(0) 1133 #define AMCNTENCLR0_EL0_Pn_MASK ULL(0xffff) 1134 1135 /* AMCNTENCLR1_EL0 definitions */ 1136 #define AMCNTENCLR1_EL0_Pn_SHIFT U(0) 1137 #define AMCNTENCLR1_EL0_Pn_MASK ULL(0xffff) 1138 1139 /* AMCFGR_EL0 definitions */ 1140 #define AMCFGR_EL0_NCG_SHIFT U(28) 1141 #define AMCFGR_EL0_NCG_MASK U(0xf) 1142 #define AMCFGR_EL0_N_SHIFT U(0) 1143 #define AMCFGR_EL0_N_MASK U(0xff) 1144 1145 /* AMCGCR_EL0 definitions */ 1146 #define AMCGCR_EL0_CG0NC_SHIFT U(0) 1147 #define AMCGCR_EL0_CG0NC_MASK U(0xff) 1148 #define AMCGCR_EL0_CG1NC_SHIFT U(8) 1149 #define AMCGCR_EL0_CG1NC_MASK U(0xff) 1150 1151 /* MPAM register definitions */ 1152 #define MPAM3_EL3_MPAMEN_BIT (ULL(1) << 63) 1153 #define MPAMHCR_EL2_TRAP_MPAMIDR_EL1 (ULL(1) << 31) 1154 1155 #define MPAM2_EL2_TRAPMPAM0EL1 (ULL(1) << 49) 1156 #define MPAM2_EL2_TRAPMPAM1EL1 (ULL(1) << 48) 1157 1158 #define MPAMIDR_HAS_HCR_BIT (ULL(1) << 17) 1159 1160 /******************************************************************************* 1161 * Definitions for system register interface to AMU for FEAT_AMUv1p1 1162 ******************************************************************************/ 1163 1164 /* Definition for register defining which virtual offsets are implemented. */ 1165 #define AMCG1IDR_EL0 S3_3_C13_C2_6 1166 #define AMCG1IDR_CTR_MASK ULL(0xffff) 1167 #define AMCG1IDR_CTR_SHIFT U(0) 1168 #define AMCG1IDR_VOFF_MASK ULL(0xffff) 1169 #define AMCG1IDR_VOFF_SHIFT U(16) 1170 1171 /* New bit added to AMCR_EL0 */ 1172 #define AMCR_CG1RZ_SHIFT U(17) 1173 #define AMCR_CG1RZ_BIT (ULL(0x1) << AMCR_CG1RZ_SHIFT) 1174 1175 /* 1176 * Definitions for virtual offset registers for architected activity monitor 1177 * event counters. 1178 * AMEVCNTVOFF01_EL2 intentionally left undefined, as it does not exist. 1179 */ 1180 #define AMEVCNTVOFF00_EL2 S3_4_C13_C8_0 1181 #define AMEVCNTVOFF02_EL2 S3_4_C13_C8_2 1182 #define AMEVCNTVOFF03_EL2 S3_4_C13_C8_3 1183 1184 /* 1185 * Definitions for virtual offset registers for auxiliary activity monitor event 1186 * counters. 1187 */ 1188 #define AMEVCNTVOFF10_EL2 S3_4_C13_C10_0 1189 #define AMEVCNTVOFF11_EL2 S3_4_C13_C10_1 1190 #define AMEVCNTVOFF12_EL2 S3_4_C13_C10_2 1191 #define AMEVCNTVOFF13_EL2 S3_4_C13_C10_3 1192 #define AMEVCNTVOFF14_EL2 S3_4_C13_C10_4 1193 #define AMEVCNTVOFF15_EL2 S3_4_C13_C10_5 1194 #define AMEVCNTVOFF16_EL2 S3_4_C13_C10_6 1195 #define AMEVCNTVOFF17_EL2 S3_4_C13_C10_7 1196 #define AMEVCNTVOFF18_EL2 S3_4_C13_C11_0 1197 #define AMEVCNTVOFF19_EL2 S3_4_C13_C11_1 1198 #define AMEVCNTVOFF1A_EL2 S3_4_C13_C11_2 1199 #define AMEVCNTVOFF1B_EL2 S3_4_C13_C11_3 1200 #define AMEVCNTVOFF1C_EL2 S3_4_C13_C11_4 1201 #define AMEVCNTVOFF1D_EL2 S3_4_C13_C11_5 1202 #define AMEVCNTVOFF1E_EL2 S3_4_C13_C11_6 1203 #define AMEVCNTVOFF1F_EL2 S3_4_C13_C11_7 1204 1205 /******************************************************************************* 1206 * Realm management extension register definitions 1207 ******************************************************************************/ 1208 #define GPCCR_EL3 S3_6_C2_C1_6 1209 #define GPTBR_EL3 S3_6_C2_C1_4 1210 1211 /******************************************************************************* 1212 * RAS system registers 1213 ******************************************************************************/ 1214 #define DISR_EL1 S3_0_C12_C1_1 1215 #define DISR_A_BIT U(31) 1216 1217 #define ERRIDR_EL1 S3_0_C5_C3_0 1218 #define ERRIDR_MASK U(0xffff) 1219 1220 #define ERRSELR_EL1 S3_0_C5_C3_1 1221 1222 /* System register access to Standard Error Record registers */ 1223 #define ERXFR_EL1 S3_0_C5_C4_0 1224 #define ERXCTLR_EL1 S3_0_C5_C4_1 1225 #define ERXSTATUS_EL1 S3_0_C5_C4_2 1226 #define ERXADDR_EL1 S3_0_C5_C4_3 1227 #define ERXPFGF_EL1 S3_0_C5_C4_4 1228 #define ERXPFGCTL_EL1 S3_0_C5_C4_5 1229 #define ERXPFGCDN_EL1 S3_0_C5_C4_6 1230 #define ERXMISC0_EL1 S3_0_C5_C5_0 1231 #define ERXMISC1_EL1 S3_0_C5_C5_1 1232 1233 #define ERXCTLR_ED_SHIFT U(0) 1234 #define ERXCTLR_ED_BIT (U(1) << ERXCTLR_ED_SHIFT) 1235 #define ERXCTLR_UE_BIT (U(1) << 4) 1236 1237 #define ERXPFGCTL_UC_BIT (U(1) << 1) 1238 #define ERXPFGCTL_UEU_BIT (U(1) << 2) 1239 #define ERXPFGCTL_CDEN_BIT (U(1) << 31) 1240 1241 /******************************************************************************* 1242 * Armv8.3 Pointer Authentication Registers 1243 ******************************************************************************/ 1244 #define APIAKeyLo_EL1 S3_0_C2_C1_0 1245 #define APIAKeyHi_EL1 S3_0_C2_C1_1 1246 #define APIBKeyLo_EL1 S3_0_C2_C1_2 1247 #define APIBKeyHi_EL1 S3_0_C2_C1_3 1248 #define APDAKeyLo_EL1 S3_0_C2_C2_0 1249 #define APDAKeyHi_EL1 S3_0_C2_C2_1 1250 #define APDBKeyLo_EL1 S3_0_C2_C2_2 1251 #define APDBKeyHi_EL1 S3_0_C2_C2_3 1252 #define APGAKeyLo_EL1 S3_0_C2_C3_0 1253 #define APGAKeyHi_EL1 S3_0_C2_C3_1 1254 1255 /******************************************************************************* 1256 * Armv8.4 Data Independent Timing Registers 1257 ******************************************************************************/ 1258 #define DIT S3_3_C4_C2_5 1259 #define DIT_BIT BIT(24) 1260 1261 /******************************************************************************* 1262 * Armv8.5 - new MSR encoding to directly access PSTATE.SSBS field 1263 ******************************************************************************/ 1264 #define SSBS S3_3_C4_C2_6 1265 1266 /******************************************************************************* 1267 * Armv8.5 - Memory Tagging Extension Registers 1268 ******************************************************************************/ 1269 #define TFSRE0_EL1 S3_0_C5_C6_1 1270 #define TFSR_EL1 S3_0_C5_C6_0 1271 #define RGSR_EL1 S3_0_C1_C0_5 1272 #define GCR_EL1 S3_0_C1_C0_6 1273 1274 /******************************************************************************* 1275 * FEAT_HCX - Extended Hypervisor Configuration Register 1276 ******************************************************************************/ 1277 #define HCRX_EL2 S3_4_C1_C2_2 1278 #define HCRX_EL2_FGTnXS_BIT (UL(1) << 4) 1279 #define HCRX_EL2_FnXS_BIT (UL(1) << 3) 1280 #define HCRX_EL2_EnASR_BIT (UL(1) << 2) 1281 #define HCRX_EL2_EnALS_BIT (UL(1) << 1) 1282 #define HCRX_EL2_EnAS0_BIT (UL(1) << 0) 1283 1284 /******************************************************************************* 1285 * Definitions for DynamicIQ Shared Unit registers 1286 ******************************************************************************/ 1287 #define CLUSTERPWRDN_EL1 S3_0_c15_c3_6 1288 1289 /* CLUSTERPWRDN_EL1 register definitions */ 1290 #define DSU_CLUSTER_PWR_OFF 0 1291 #define DSU_CLUSTER_PWR_ON 1 1292 #define DSU_CLUSTER_PWR_MASK U(1) 1293 1294 /******************************************************************************* 1295 * Definitions for CPU Power/Performance Management registers 1296 ******************************************************************************/ 1297 1298 #define CPUPPMCR_EL3 S3_6_C15_C2_0 1299 #define CPUPPMCR_EL3_MPMMPINCTL_SHIFT UINT64_C(0) 1300 #define CPUPPMCR_EL3_MPMMPINCTL_MASK UINT64_C(0x1) 1301 1302 #define CPUMPMMCR_EL3 S3_6_C15_C2_1 1303 #define CPUMPMMCR_EL3_MPMM_EN_SHIFT UINT64_C(0) 1304 #define CPUMPMMCR_EL3_MPMM_EN_MASK UINT64_C(0x1) 1305 1306 #endif /* ARCH_H */ 1307