1 /* 2 * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef ARCH_H 8 #define ARCH_H 9 10 #include <lib/utils_def.h> 11 12 /******************************************************************************* 13 * MIDR bit definitions 14 ******************************************************************************/ 15 #define MIDR_IMPL_MASK U(0xff) 16 #define MIDR_IMPL_SHIFT U(0x18) 17 #define MIDR_VAR_SHIFT U(20) 18 #define MIDR_VAR_BITS U(4) 19 #define MIDR_VAR_MASK U(0xf) 20 #define MIDR_REV_SHIFT U(0) 21 #define MIDR_REV_BITS U(4) 22 #define MIDR_REV_MASK U(0xf) 23 #define MIDR_PN_MASK U(0xfff) 24 #define MIDR_PN_SHIFT U(0x4) 25 26 /******************************************************************************* 27 * MPIDR macros 28 ******************************************************************************/ 29 #define MPIDR_MT_MASK (ULL(1) << 24) 30 #define MPIDR_CPU_MASK MPIDR_AFFLVL_MASK 31 #define MPIDR_CLUSTER_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS) 32 #define MPIDR_AFFINITY_BITS U(8) 33 #define MPIDR_AFFLVL_MASK ULL(0xff) 34 #define MPIDR_AFF0_SHIFT U(0) 35 #define MPIDR_AFF1_SHIFT U(8) 36 #define MPIDR_AFF2_SHIFT U(16) 37 #define MPIDR_AFF3_SHIFT U(32) 38 #define MPIDR_AFF_SHIFT(_n) MPIDR_AFF##_n##_SHIFT 39 #define MPIDR_AFFINITY_MASK ULL(0xff00ffffff) 40 #define MPIDR_AFFLVL_SHIFT U(3) 41 #define MPIDR_AFFLVL0 ULL(0x0) 42 #define MPIDR_AFFLVL1 ULL(0x1) 43 #define MPIDR_AFFLVL2 ULL(0x2) 44 #define MPIDR_AFFLVL3 ULL(0x3) 45 #define MPIDR_AFFLVL(_n) MPIDR_AFFLVL##_n 46 #define MPIDR_AFFLVL0_VAL(mpidr) \ 47 (((mpidr) >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK) 48 #define MPIDR_AFFLVL1_VAL(mpidr) \ 49 (((mpidr) >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK) 50 #define MPIDR_AFFLVL2_VAL(mpidr) \ 51 (((mpidr) >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK) 52 #define MPIDR_AFFLVL3_VAL(mpidr) \ 53 (((mpidr) >> MPIDR_AFF3_SHIFT) & MPIDR_AFFLVL_MASK) 54 /* 55 * The MPIDR_MAX_AFFLVL count starts from 0. Take care to 56 * add one while using this macro to define array sizes. 57 * TODO: Support only the first 3 affinity levels for now. 58 */ 59 #define MPIDR_MAX_AFFLVL U(2) 60 61 #define MPID_MASK (MPIDR_MT_MASK | \ 62 (MPIDR_AFFLVL_MASK << MPIDR_AFF3_SHIFT) | \ 63 (MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT) | \ 64 (MPIDR_AFFLVL_MASK << MPIDR_AFF1_SHIFT) | \ 65 (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT)) 66 67 #define MPIDR_AFF_ID(mpid, n) \ 68 (((mpid) >> MPIDR_AFF_SHIFT(n)) & MPIDR_AFFLVL_MASK) 69 70 /* 71 * An invalid MPID. This value can be used by functions that return an MPID to 72 * indicate an error. 73 */ 74 #define INVALID_MPID U(0xFFFFFFFF) 75 76 /******************************************************************************* 77 * Definitions for CPU system register interface to GICv3 78 ******************************************************************************/ 79 #define ICC_IGRPEN1_EL1 S3_0_C12_C12_7 80 #define ICC_SGI1R S3_0_C12_C11_5 81 #define ICC_SRE_EL1 S3_0_C12_C12_5 82 #define ICC_SRE_EL2 S3_4_C12_C9_5 83 #define ICC_SRE_EL3 S3_6_C12_C12_5 84 #define ICC_CTLR_EL1 S3_0_C12_C12_4 85 #define ICC_CTLR_EL3 S3_6_C12_C12_4 86 #define ICC_PMR_EL1 S3_0_C4_C6_0 87 #define ICC_RPR_EL1 S3_0_C12_C11_3 88 #define ICC_IGRPEN1_EL3 S3_6_c12_c12_7 89 #define ICC_IGRPEN0_EL1 S3_0_c12_c12_6 90 #define ICC_HPPIR0_EL1 S3_0_c12_c8_2 91 #define ICC_HPPIR1_EL1 S3_0_c12_c12_2 92 #define ICC_IAR0_EL1 S3_0_c12_c8_0 93 #define ICC_IAR1_EL1 S3_0_c12_c12_0 94 #define ICC_EOIR0_EL1 S3_0_c12_c8_1 95 #define ICC_EOIR1_EL1 S3_0_c12_c12_1 96 #define ICC_SGI0R_EL1 S3_0_c12_c11_7 97 98 /******************************************************************************* 99 * Generic timer memory mapped registers & offsets 100 ******************************************************************************/ 101 #define CNTCR_OFF U(0x000) 102 #define CNTCV_OFF U(0x008) 103 #define CNTFID_OFF U(0x020) 104 105 #define CNTCR_EN (U(1) << 0) 106 #define CNTCR_HDBG (U(1) << 1) 107 #define CNTCR_FCREQ(x) ((x) << 8) 108 109 /******************************************************************************* 110 * System register bit definitions 111 ******************************************************************************/ 112 /* CLIDR definitions */ 113 #define LOUIS_SHIFT U(21) 114 #define LOC_SHIFT U(24) 115 #define CLIDR_FIELD_WIDTH U(3) 116 117 /* CSSELR definitions */ 118 #define LEVEL_SHIFT U(1) 119 120 /* Data cache set/way op type defines */ 121 #define DCISW U(0x0) 122 #define DCCISW U(0x1) 123 #if ERRATA_A53_827319 124 #define DCCSW DCCISW 125 #else 126 #define DCCSW U(0x2) 127 #endif 128 129 /* ID_AA64PFR0_EL1 definitions */ 130 #define ID_AA64PFR0_EL0_SHIFT U(0) 131 #define ID_AA64PFR0_EL1_SHIFT U(4) 132 #define ID_AA64PFR0_EL2_SHIFT U(8) 133 #define ID_AA64PFR0_EL3_SHIFT U(12) 134 #define ID_AA64PFR0_AMU_SHIFT U(44) 135 #define ID_AA64PFR0_AMU_LENGTH U(4) 136 #define ID_AA64PFR0_AMU_MASK ULL(0xf) 137 #define ID_AA64PFR0_ELX_MASK ULL(0xf) 138 #define ID_AA64PFR0_SVE_SHIFT U(32) 139 #define ID_AA64PFR0_SVE_MASK ULL(0xf) 140 #define ID_AA64PFR0_SVE_LENGTH U(4) 141 #define ID_AA64PFR0_MPAM_SHIFT U(40) 142 #define ID_AA64PFR0_MPAM_MASK ULL(0xf) 143 #define ID_AA64PFR0_DIT_SHIFT U(48) 144 #define ID_AA64PFR0_DIT_MASK ULL(0xf) 145 #define ID_AA64PFR0_DIT_LENGTH U(4) 146 #define ID_AA64PFR0_DIT_SUPPORTED U(1) 147 #define ID_AA64PFR0_CSV2_SHIFT U(56) 148 #define ID_AA64PFR0_CSV2_MASK ULL(0xf) 149 #define ID_AA64PFR0_CSV2_LENGTH U(4) 150 151 /* ID_AA64DFR0_EL1.PMS definitions (for ARMv8.2+) */ 152 #define ID_AA64DFR0_PMS_SHIFT U(32) 153 #define ID_AA64DFR0_PMS_LENGTH U(4) 154 #define ID_AA64DFR0_PMS_MASK ULL(0xf) 155 156 #define EL_IMPL_NONE ULL(0) 157 #define EL_IMPL_A64ONLY ULL(1) 158 #define EL_IMPL_A64_A32 ULL(2) 159 160 #define ID_AA64PFR0_GIC_SHIFT U(24) 161 #define ID_AA64PFR0_GIC_WIDTH U(4) 162 #define ID_AA64PFR0_GIC_MASK ULL(0xf) 163 164 /* ID_AA64ISAR1_EL1 definitions */ 165 #define ID_AA64ISAR1_EL1 S3_0_C0_C6_1 166 #define ID_AA64ISAR1_GPI_SHIFT U(28) 167 #define ID_AA64ISAR1_GPI_MASK ULL(0xf) 168 #define ID_AA64ISAR1_GPA_SHIFT U(24) 169 #define ID_AA64ISAR1_GPA_MASK ULL(0xf) 170 #define ID_AA64ISAR1_API_SHIFT U(8) 171 #define ID_AA64ISAR1_API_MASK ULL(0xf) 172 #define ID_AA64ISAR1_APA_SHIFT U(4) 173 #define ID_AA64ISAR1_APA_MASK ULL(0xf) 174 175 /* ID_AA64MMFR0_EL1 definitions */ 176 #define ID_AA64MMFR0_EL1_PARANGE_SHIFT U(0) 177 #define ID_AA64MMFR0_EL1_PARANGE_MASK ULL(0xf) 178 179 #define PARANGE_0000 U(32) 180 #define PARANGE_0001 U(36) 181 #define PARANGE_0010 U(40) 182 #define PARANGE_0011 U(42) 183 #define PARANGE_0100 U(44) 184 #define PARANGE_0101 U(48) 185 #define PARANGE_0110 U(52) 186 187 #define ID_AA64MMFR0_EL1_TGRAN4_SHIFT U(28) 188 #define ID_AA64MMFR0_EL1_TGRAN4_MASK ULL(0xf) 189 #define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED ULL(0x0) 190 #define ID_AA64MMFR0_EL1_TGRAN4_NOT_SUPPORTED ULL(0xf) 191 192 #define ID_AA64MMFR0_EL1_TGRAN64_SHIFT U(24) 193 #define ID_AA64MMFR0_EL1_TGRAN64_MASK ULL(0xf) 194 #define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED ULL(0x0) 195 #define ID_AA64MMFR0_EL1_TGRAN64_NOT_SUPPORTED ULL(0xf) 196 197 #define ID_AA64MMFR0_EL1_TGRAN16_SHIFT U(20) 198 #define ID_AA64MMFR0_EL1_TGRAN16_MASK ULL(0xf) 199 #define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED ULL(0x1) 200 #define ID_AA64MMFR0_EL1_TGRAN16_NOT_SUPPORTED ULL(0x0) 201 202 /* ID_AA64MMFR2_EL1 definitions */ 203 #define ID_AA64MMFR2_EL1 S3_0_C0_C7_2 204 205 #define ID_AA64MMFR2_EL1_ST_SHIFT U(28) 206 #define ID_AA64MMFR2_EL1_ST_MASK ULL(0xf) 207 208 #define ID_AA64MMFR2_EL1_CNP_SHIFT U(0) 209 #define ID_AA64MMFR2_EL1_CNP_MASK ULL(0xf) 210 211 /* ID_AA64PFR1_EL1 definitions */ 212 #define ID_AA64PFR1_EL1_SSBS_SHIFT U(4) 213 #define ID_AA64PFR1_EL1_SSBS_MASK ULL(0xf) 214 215 #define SSBS_UNAVAILABLE ULL(0) /* No architectural SSBS support */ 216 217 #define ID_AA64PFR1_EL1_BT_SHIFT U(0) 218 #define ID_AA64PFR1_EL1_BT_MASK ULL(0xf) 219 220 #define BTI_IMPLEMENTED ULL(1) /* The BTI mechanism is implemented */ 221 222 #define ID_AA64PFR1_EL1_MTE_SHIFT U(8) 223 #define ID_AA64PFR1_EL1_MTE_MASK ULL(0xf) 224 225 #define MTE_UNIMPLEMENTED ULL(0) 226 #define MTE_IMPLEMENTED_EL0 ULL(1) /* MTE is only implemented at EL0 */ 227 #define MTE_IMPLEMENTED_ELX ULL(2) /* MTE is implemented at all ELs */ 228 229 /* ID_PFR1_EL1 definitions */ 230 #define ID_PFR1_VIRTEXT_SHIFT U(12) 231 #define ID_PFR1_VIRTEXT_MASK U(0xf) 232 #define GET_VIRT_EXT(id) (((id) >> ID_PFR1_VIRTEXT_SHIFT) \ 233 & ID_PFR1_VIRTEXT_MASK) 234 235 /* SCTLR definitions */ 236 #define SCTLR_EL2_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ 237 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \ 238 (U(1) << 11) | (U(1) << 5) | (U(1) << 4)) 239 240 #define SCTLR_EL1_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ 241 (U(1) << 22) | (U(1) << 20) | (U(1) << 11)) 242 #define SCTLR_AARCH32_EL1_RES1 \ 243 ((U(1) << 23) | (U(1) << 22) | (U(1) << 11) | \ 244 (U(1) << 4) | (U(1) << 3)) 245 246 #define SCTLR_EL3_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ 247 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \ 248 (U(1) << 11) | (U(1) << 5) | (U(1) << 4)) 249 250 #define SCTLR_M_BIT (ULL(1) << 0) 251 #define SCTLR_A_BIT (ULL(1) << 1) 252 #define SCTLR_C_BIT (ULL(1) << 2) 253 #define SCTLR_SA_BIT (ULL(1) << 3) 254 #define SCTLR_SA0_BIT (ULL(1) << 4) 255 #define SCTLR_CP15BEN_BIT (ULL(1) << 5) 256 #define SCTLR_ITD_BIT (ULL(1) << 7) 257 #define SCTLR_SED_BIT (ULL(1) << 8) 258 #define SCTLR_UMA_BIT (ULL(1) << 9) 259 #define SCTLR_I_BIT (ULL(1) << 12) 260 #define SCTLR_EnDB_BIT (ULL(1) << 13) 261 #define SCTLR_DZE_BIT (ULL(1) << 14) 262 #define SCTLR_UCT_BIT (ULL(1) << 15) 263 #define SCTLR_NTWI_BIT (ULL(1) << 16) 264 #define SCTLR_NTWE_BIT (ULL(1) << 18) 265 #define SCTLR_WXN_BIT (ULL(1) << 19) 266 #define SCTLR_UWXN_BIT (ULL(1) << 20) 267 #define SCTLR_IESB_BIT (ULL(1) << 21) 268 #define SCTLR_E0E_BIT (ULL(1) << 24) 269 #define SCTLR_EE_BIT (ULL(1) << 25) 270 #define SCTLR_UCI_BIT (ULL(1) << 26) 271 #define SCTLR_EnDA_BIT (ULL(1) << 27) 272 #define SCTLR_EnIB_BIT (ULL(1) << 30) 273 #define SCTLR_EnIA_BIT (ULL(1) << 31) 274 #define SCTLR_BT0_BIT (ULL(1) << 35) 275 #define SCTLR_BT1_BIT (ULL(1) << 36) 276 #define SCTLR_BT_BIT (ULL(1) << 36) 277 #define SCTLR_DSSBS_BIT (ULL(1) << 44) 278 #define SCTLR_RESET_VAL SCTLR_EL3_RES1 279 280 /* CPACR_El1 definitions */ 281 #define CPACR_EL1_FPEN(x) ((x) << 20) 282 #define CPACR_EL1_FP_TRAP_EL0 U(0x1) 283 #define CPACR_EL1_FP_TRAP_ALL U(0x2) 284 #define CPACR_EL1_FP_TRAP_NONE U(0x3) 285 286 /* SCR definitions */ 287 #define SCR_RES1_BITS ((U(1) << 4) | (U(1) << 5)) 288 #define SCR_ATA_BIT (U(1) << 26) 289 #define SCR_FIEN_BIT (U(1) << 21) 290 #define SCR_API_BIT (U(1) << 17) 291 #define SCR_APK_BIT (U(1) << 16) 292 #define SCR_TWE_BIT (U(1) << 13) 293 #define SCR_TWI_BIT (U(1) << 12) 294 #define SCR_ST_BIT (U(1) << 11) 295 #define SCR_RW_BIT (U(1) << 10) 296 #define SCR_SIF_BIT (U(1) << 9) 297 #define SCR_HCE_BIT (U(1) << 8) 298 #define SCR_SMD_BIT (U(1) << 7) 299 #define SCR_EA_BIT (U(1) << 3) 300 #define SCR_FIQ_BIT (U(1) << 2) 301 #define SCR_IRQ_BIT (U(1) << 1) 302 #define SCR_NS_BIT (U(1) << 0) 303 #define SCR_VALID_BIT_MASK U(0x2f8f) 304 #define SCR_RESET_VAL SCR_RES1_BITS 305 306 /* MDCR_EL3 definitions */ 307 #define MDCR_SPD32(x) ((x) << 14) 308 #define MDCR_SPD32_LEGACY ULL(0x0) 309 #define MDCR_SPD32_DISABLE ULL(0x2) 310 #define MDCR_SPD32_ENABLE ULL(0x3) 311 #define MDCR_SDD_BIT (ULL(1) << 16) 312 #define MDCR_NSPB(x) ((x) << 12) 313 #define MDCR_NSPB_EL1 ULL(0x3) 314 #define MDCR_TDOSA_BIT (ULL(1) << 10) 315 #define MDCR_TDA_BIT (ULL(1) << 9) 316 #define MDCR_TPM_BIT (ULL(1) << 6) 317 #define MDCR_SCCD_BIT (ULL(1) << 23) 318 #define MDCR_EL3_RESET_VAL ULL(0x0) 319 320 /* MDCR_EL2 definitions */ 321 #define MDCR_EL2_TPMS (U(1) << 14) 322 #define MDCR_EL2_E2PB(x) ((x) << 12) 323 #define MDCR_EL2_E2PB_EL1 U(0x3) 324 #define MDCR_EL2_TDRA_BIT (U(1) << 11) 325 #define MDCR_EL2_TDOSA_BIT (U(1) << 10) 326 #define MDCR_EL2_TDA_BIT (U(1) << 9) 327 #define MDCR_EL2_TDE_BIT (U(1) << 8) 328 #define MDCR_EL2_HPME_BIT (U(1) << 7) 329 #define MDCR_EL2_TPM_BIT (U(1) << 6) 330 #define MDCR_EL2_TPMCR_BIT (U(1) << 5) 331 #define MDCR_EL2_RESET_VAL U(0x0) 332 333 /* HSTR_EL2 definitions */ 334 #define HSTR_EL2_RESET_VAL U(0x0) 335 #define HSTR_EL2_T_MASK U(0xff) 336 337 /* CNTHP_CTL_EL2 definitions */ 338 #define CNTHP_CTL_ENABLE_BIT (U(1) << 0) 339 #define CNTHP_CTL_RESET_VAL U(0x0) 340 341 /* VTTBR_EL2 definitions */ 342 #define VTTBR_RESET_VAL ULL(0x0) 343 #define VTTBR_VMID_MASK ULL(0xff) 344 #define VTTBR_VMID_SHIFT U(48) 345 #define VTTBR_BADDR_MASK ULL(0xffffffffffff) 346 #define VTTBR_BADDR_SHIFT U(0) 347 348 /* HCR definitions */ 349 #define HCR_API_BIT (ULL(1) << 41) 350 #define HCR_APK_BIT (ULL(1) << 40) 351 #define HCR_TGE_BIT (ULL(1) << 27) 352 #define HCR_RW_SHIFT U(31) 353 #define HCR_RW_BIT (ULL(1) << HCR_RW_SHIFT) 354 #define HCR_AMO_BIT (ULL(1) << 5) 355 #define HCR_IMO_BIT (ULL(1) << 4) 356 #define HCR_FMO_BIT (ULL(1) << 3) 357 358 /* ISR definitions */ 359 #define ISR_A_SHIFT U(8) 360 #define ISR_I_SHIFT U(7) 361 #define ISR_F_SHIFT U(6) 362 363 /* CNTHCTL_EL2 definitions */ 364 #define CNTHCTL_RESET_VAL U(0x0) 365 #define EVNTEN_BIT (U(1) << 2) 366 #define EL1PCEN_BIT (U(1) << 1) 367 #define EL1PCTEN_BIT (U(1) << 0) 368 369 /* CNTKCTL_EL1 definitions */ 370 #define EL0PTEN_BIT (U(1) << 9) 371 #define EL0VTEN_BIT (U(1) << 8) 372 #define EL0PCTEN_BIT (U(1) << 0) 373 #define EL0VCTEN_BIT (U(1) << 1) 374 #define EVNTEN_BIT (U(1) << 2) 375 #define EVNTDIR_BIT (U(1) << 3) 376 #define EVNTI_SHIFT U(4) 377 #define EVNTI_MASK U(0xf) 378 379 /* CPTR_EL3 definitions */ 380 #define TCPAC_BIT (U(1) << 31) 381 #define TAM_BIT (U(1) << 30) 382 #define TTA_BIT (U(1) << 20) 383 #define TFP_BIT (U(1) << 10) 384 #define CPTR_EZ_BIT (U(1) << 8) 385 #define CPTR_EL3_RESET_VAL U(0x0) 386 387 /* CPTR_EL2 definitions */ 388 #define CPTR_EL2_RES1 ((U(1) << 13) | (U(1) << 12) | (U(0x3ff))) 389 #define CPTR_EL2_TCPAC_BIT (U(1) << 31) 390 #define CPTR_EL2_TAM_BIT (U(1) << 30) 391 #define CPTR_EL2_TTA_BIT (U(1) << 20) 392 #define CPTR_EL2_TFP_BIT (U(1) << 10) 393 #define CPTR_EL2_TZ_BIT (U(1) << 8) 394 #define CPTR_EL2_RESET_VAL CPTR_EL2_RES1 395 396 /* CPSR/SPSR definitions */ 397 #define DAIF_FIQ_BIT (U(1) << 0) 398 #define DAIF_IRQ_BIT (U(1) << 1) 399 #define DAIF_ABT_BIT (U(1) << 2) 400 #define DAIF_DBG_BIT (U(1) << 3) 401 #define SPSR_DAIF_SHIFT U(6) 402 #define SPSR_DAIF_MASK U(0xf) 403 404 #define SPSR_AIF_SHIFT U(6) 405 #define SPSR_AIF_MASK U(0x7) 406 407 #define SPSR_E_SHIFT U(9) 408 #define SPSR_E_MASK U(0x1) 409 #define SPSR_E_LITTLE U(0x0) 410 #define SPSR_E_BIG U(0x1) 411 412 #define SPSR_T_SHIFT U(5) 413 #define SPSR_T_MASK U(0x1) 414 #define SPSR_T_ARM U(0x0) 415 #define SPSR_T_THUMB U(0x1) 416 417 #define SPSR_M_SHIFT U(4) 418 #define SPSR_M_MASK U(0x1) 419 #define SPSR_M_AARCH64 U(0x0) 420 #define SPSR_M_AARCH32 U(0x1) 421 422 #define SPSR_SSBS_BIT_AARCH64 BIT_64(12) 423 #define SPSR_SSBS_BIT_AARCH32 BIT_64(23) 424 425 #define DISABLE_ALL_EXCEPTIONS \ 426 (DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT | DAIF_DBG_BIT) 427 428 #define DISABLE_INTERRUPTS (DAIF_FIQ_BIT | DAIF_IRQ_BIT) 429 430 /* 431 * RMR_EL3 definitions 432 */ 433 #define RMR_EL3_RR_BIT (U(1) << 1) 434 #define RMR_EL3_AA64_BIT (U(1) << 0) 435 436 /* 437 * HI-VECTOR address for AArch32 state 438 */ 439 #define HI_VECTOR_BASE U(0xFFFF0000) 440 441 /* 442 * TCR defintions 443 */ 444 #define TCR_EL3_RES1 ((ULL(1) << 31) | (ULL(1) << 23)) 445 #define TCR_EL2_RES1 ((ULL(1) << 31) | (ULL(1) << 23)) 446 #define TCR_EL1_IPS_SHIFT U(32) 447 #define TCR_EL2_PS_SHIFT U(16) 448 #define TCR_EL3_PS_SHIFT U(16) 449 450 #define TCR_TxSZ_MIN ULL(16) 451 #define TCR_TxSZ_MAX ULL(39) 452 #define TCR_TxSZ_MAX_TTST ULL(48) 453 454 #define TCR_T0SZ_SHIFT U(0) 455 #define TCR_T1SZ_SHIFT U(16) 456 457 /* (internal) physical address size bits in EL3/EL1 */ 458 #define TCR_PS_BITS_4GB ULL(0x0) 459 #define TCR_PS_BITS_64GB ULL(0x1) 460 #define TCR_PS_BITS_1TB ULL(0x2) 461 #define TCR_PS_BITS_4TB ULL(0x3) 462 #define TCR_PS_BITS_16TB ULL(0x4) 463 #define TCR_PS_BITS_256TB ULL(0x5) 464 465 #define ADDR_MASK_48_TO_63 ULL(0xFFFF000000000000) 466 #define ADDR_MASK_44_TO_47 ULL(0x0000F00000000000) 467 #define ADDR_MASK_42_TO_43 ULL(0x00000C0000000000) 468 #define ADDR_MASK_40_TO_41 ULL(0x0000030000000000) 469 #define ADDR_MASK_36_TO_39 ULL(0x000000F000000000) 470 #define ADDR_MASK_32_TO_35 ULL(0x0000000F00000000) 471 472 #define TCR_RGN_INNER_NC (ULL(0x0) << 8) 473 #define TCR_RGN_INNER_WBA (ULL(0x1) << 8) 474 #define TCR_RGN_INNER_WT (ULL(0x2) << 8) 475 #define TCR_RGN_INNER_WBNA (ULL(0x3) << 8) 476 477 #define TCR_RGN_OUTER_NC (ULL(0x0) << 10) 478 #define TCR_RGN_OUTER_WBA (ULL(0x1) << 10) 479 #define TCR_RGN_OUTER_WT (ULL(0x2) << 10) 480 #define TCR_RGN_OUTER_WBNA (ULL(0x3) << 10) 481 482 #define TCR_SH_NON_SHAREABLE (ULL(0x0) << 12) 483 #define TCR_SH_OUTER_SHAREABLE (ULL(0x2) << 12) 484 #define TCR_SH_INNER_SHAREABLE (ULL(0x3) << 12) 485 486 #define TCR_RGN1_INNER_NC (ULL(0x0) << 24) 487 #define TCR_RGN1_INNER_WBA (ULL(0x1) << 24) 488 #define TCR_RGN1_INNER_WT (ULL(0x2) << 24) 489 #define TCR_RGN1_INNER_WBNA (ULL(0x3) << 24) 490 491 #define TCR_RGN1_OUTER_NC (ULL(0x0) << 26) 492 #define TCR_RGN1_OUTER_WBA (ULL(0x1) << 26) 493 #define TCR_RGN1_OUTER_WT (ULL(0x2) << 26) 494 #define TCR_RGN1_OUTER_WBNA (ULL(0x3) << 26) 495 496 #define TCR_SH1_NON_SHAREABLE (ULL(0x0) << 28) 497 #define TCR_SH1_OUTER_SHAREABLE (ULL(0x2) << 28) 498 #define TCR_SH1_INNER_SHAREABLE (ULL(0x3) << 28) 499 500 #define TCR_TG0_SHIFT U(14) 501 #define TCR_TG0_MASK ULL(3) 502 #define TCR_TG0_4K (ULL(0) << TCR_TG0_SHIFT) 503 #define TCR_TG0_64K (ULL(1) << TCR_TG0_SHIFT) 504 #define TCR_TG0_16K (ULL(2) << TCR_TG0_SHIFT) 505 506 #define TCR_TG1_SHIFT U(30) 507 #define TCR_TG1_MASK ULL(3) 508 #define TCR_TG1_16K (ULL(1) << TCR_TG1_SHIFT) 509 #define TCR_TG1_4K (ULL(2) << TCR_TG1_SHIFT) 510 #define TCR_TG1_64K (ULL(3) << TCR_TG1_SHIFT) 511 512 #define TCR_EPD0_BIT (ULL(1) << 7) 513 #define TCR_EPD1_BIT (ULL(1) << 23) 514 515 #define MODE_SP_SHIFT U(0x0) 516 #define MODE_SP_MASK U(0x1) 517 #define MODE_SP_EL0 U(0x0) 518 #define MODE_SP_ELX U(0x1) 519 520 #define MODE_RW_SHIFT U(0x4) 521 #define MODE_RW_MASK U(0x1) 522 #define MODE_RW_64 U(0x0) 523 #define MODE_RW_32 U(0x1) 524 525 #define MODE_EL_SHIFT U(0x2) 526 #define MODE_EL_MASK U(0x3) 527 #define MODE_EL3 U(0x3) 528 #define MODE_EL2 U(0x2) 529 #define MODE_EL1 U(0x1) 530 #define MODE_EL0 U(0x0) 531 532 #define MODE32_SHIFT U(0) 533 #define MODE32_MASK U(0xf) 534 #define MODE32_usr U(0x0) 535 #define MODE32_fiq U(0x1) 536 #define MODE32_irq U(0x2) 537 #define MODE32_svc U(0x3) 538 #define MODE32_mon U(0x6) 539 #define MODE32_abt U(0x7) 540 #define MODE32_hyp U(0xa) 541 #define MODE32_und U(0xb) 542 #define MODE32_sys U(0xf) 543 544 #define GET_RW(mode) (((mode) >> MODE_RW_SHIFT) & MODE_RW_MASK) 545 #define GET_EL(mode) (((mode) >> MODE_EL_SHIFT) & MODE_EL_MASK) 546 #define GET_SP(mode) (((mode) >> MODE_SP_SHIFT) & MODE_SP_MASK) 547 #define GET_M32(mode) (((mode) >> MODE32_SHIFT) & MODE32_MASK) 548 549 #define SPSR_64(el, sp, daif) \ 550 (((MODE_RW_64 << MODE_RW_SHIFT) | \ 551 (((el) & MODE_EL_MASK) << MODE_EL_SHIFT) | \ 552 (((sp) & MODE_SP_MASK) << MODE_SP_SHIFT) | \ 553 (((daif) & SPSR_DAIF_MASK) << SPSR_DAIF_SHIFT)) & \ 554 (~(SPSR_SSBS_BIT_AARCH64))) 555 556 #define SPSR_MODE32(mode, isa, endian, aif) \ 557 (((MODE_RW_32 << MODE_RW_SHIFT) | \ 558 (((mode) & MODE32_MASK) << MODE32_SHIFT) | \ 559 (((isa) & SPSR_T_MASK) << SPSR_T_SHIFT) | \ 560 (((endian) & SPSR_E_MASK) << SPSR_E_SHIFT) | \ 561 (((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT)) & \ 562 (~(SPSR_SSBS_BIT_AARCH32))) 563 564 /* 565 * TTBR Definitions 566 */ 567 #define TTBR_CNP_BIT ULL(0x1) 568 569 /* 570 * CTR_EL0 definitions 571 */ 572 #define CTR_CWG_SHIFT U(24) 573 #define CTR_CWG_MASK U(0xf) 574 #define CTR_ERG_SHIFT U(20) 575 #define CTR_ERG_MASK U(0xf) 576 #define CTR_DMINLINE_SHIFT U(16) 577 #define CTR_DMINLINE_MASK U(0xf) 578 #define CTR_L1IP_SHIFT U(14) 579 #define CTR_L1IP_MASK U(0x3) 580 #define CTR_IMINLINE_SHIFT U(0) 581 #define CTR_IMINLINE_MASK U(0xf) 582 583 #define MAX_CACHE_LINE_SIZE U(0x800) /* 2KB */ 584 585 /* Physical timer control register bit fields shifts and masks */ 586 #define CNTP_CTL_ENABLE_SHIFT U(0) 587 #define CNTP_CTL_IMASK_SHIFT U(1) 588 #define CNTP_CTL_ISTATUS_SHIFT U(2) 589 590 #define CNTP_CTL_ENABLE_MASK U(1) 591 #define CNTP_CTL_IMASK_MASK U(1) 592 #define CNTP_CTL_ISTATUS_MASK U(1) 593 594 /* Exception Syndrome register bits and bobs */ 595 #define ESR_EC_SHIFT U(26) 596 #define ESR_EC_MASK U(0x3f) 597 #define ESR_EC_LENGTH U(6) 598 #define EC_UNKNOWN U(0x0) 599 #define EC_WFE_WFI U(0x1) 600 #define EC_AARCH32_CP15_MRC_MCR U(0x3) 601 #define EC_AARCH32_CP15_MRRC_MCRR U(0x4) 602 #define EC_AARCH32_CP14_MRC_MCR U(0x5) 603 #define EC_AARCH32_CP14_LDC_STC U(0x6) 604 #define EC_FP_SIMD U(0x7) 605 #define EC_AARCH32_CP10_MRC U(0x8) 606 #define EC_AARCH32_CP14_MRRC_MCRR U(0xc) 607 #define EC_ILLEGAL U(0xe) 608 #define EC_AARCH32_SVC U(0x11) 609 #define EC_AARCH32_HVC U(0x12) 610 #define EC_AARCH32_SMC U(0x13) 611 #define EC_AARCH64_SVC U(0x15) 612 #define EC_AARCH64_HVC U(0x16) 613 #define EC_AARCH64_SMC U(0x17) 614 #define EC_AARCH64_SYS U(0x18) 615 #define EC_IABORT_LOWER_EL U(0x20) 616 #define EC_IABORT_CUR_EL U(0x21) 617 #define EC_PC_ALIGN U(0x22) 618 #define EC_DABORT_LOWER_EL U(0x24) 619 #define EC_DABORT_CUR_EL U(0x25) 620 #define EC_SP_ALIGN U(0x26) 621 #define EC_AARCH32_FP U(0x28) 622 #define EC_AARCH64_FP U(0x2c) 623 #define EC_SERROR U(0x2f) 624 625 /* 626 * External Abort bit in Instruction and Data Aborts synchronous exception 627 * syndromes. 628 */ 629 #define ESR_ISS_EABORT_EA_BIT U(9) 630 631 #define EC_BITS(x) (((x) >> ESR_EC_SHIFT) & ESR_EC_MASK) 632 633 /* Reset bit inside the Reset management register for EL3 (RMR_EL3) */ 634 #define RMR_RESET_REQUEST_SHIFT U(0x1) 635 #define RMR_WARM_RESET_CPU (U(1) << RMR_RESET_REQUEST_SHIFT) 636 637 /******************************************************************************* 638 * Definitions of register offsets, fields and macros for CPU system 639 * instructions. 640 ******************************************************************************/ 641 642 #define TLBI_ADDR_SHIFT U(12) 643 #define TLBI_ADDR_MASK ULL(0x00000FFFFFFFFFFF) 644 #define TLBI_ADDR(x) (((x) >> TLBI_ADDR_SHIFT) & TLBI_ADDR_MASK) 645 646 /******************************************************************************* 647 * Definitions of register offsets and fields in the CNTCTLBase Frame of the 648 * system level implementation of the Generic Timer. 649 ******************************************************************************/ 650 #define CNTCTLBASE_CNTFRQ U(0x0) 651 #define CNTNSAR U(0x4) 652 #define CNTNSAR_NS_SHIFT(x) (x) 653 654 #define CNTACR_BASE(x) (U(0x40) + ((x) << 2)) 655 #define CNTACR_RPCT_SHIFT U(0x0) 656 #define CNTACR_RVCT_SHIFT U(0x1) 657 #define CNTACR_RFRQ_SHIFT U(0x2) 658 #define CNTACR_RVOFF_SHIFT U(0x3) 659 #define CNTACR_RWVT_SHIFT U(0x4) 660 #define CNTACR_RWPT_SHIFT U(0x5) 661 662 /******************************************************************************* 663 * Definitions of register offsets and fields in the CNTBaseN Frame of the 664 * system level implementation of the Generic Timer. 665 ******************************************************************************/ 666 /* Physical Count register. */ 667 #define CNTPCT_LO U(0x0) 668 /* Counter Frequency register. */ 669 #define CNTBASEN_CNTFRQ U(0x10) 670 /* Physical Timer CompareValue register. */ 671 #define CNTP_CVAL_LO U(0x20) 672 /* Physical Timer Control register. */ 673 #define CNTP_CTL U(0x2c) 674 675 /* PMCR_EL0 definitions */ 676 #define PMCR_EL0_RESET_VAL U(0x0) 677 #define PMCR_EL0_N_SHIFT U(11) 678 #define PMCR_EL0_N_MASK U(0x1f) 679 #define PMCR_EL0_N_BITS (PMCR_EL0_N_MASK << PMCR_EL0_N_SHIFT) 680 #define PMCR_EL0_LC_BIT (U(1) << 6) 681 #define PMCR_EL0_DP_BIT (U(1) << 5) 682 #define PMCR_EL0_X_BIT (U(1) << 4) 683 #define PMCR_EL0_D_BIT (U(1) << 3) 684 685 /******************************************************************************* 686 * Definitions for system register interface to SVE 687 ******************************************************************************/ 688 #define ZCR_EL3 S3_6_C1_C2_0 689 #define ZCR_EL2 S3_4_C1_C2_0 690 691 /* ZCR_EL3 definitions */ 692 #define ZCR_EL3_LEN_MASK U(0xf) 693 694 /* ZCR_EL2 definitions */ 695 #define ZCR_EL2_LEN_MASK U(0xf) 696 697 /******************************************************************************* 698 * Definitions of MAIR encodings for device and normal memory 699 ******************************************************************************/ 700 /* 701 * MAIR encodings for device memory attributes. 702 */ 703 #define MAIR_DEV_nGnRnE ULL(0x0) 704 #define MAIR_DEV_nGnRE ULL(0x4) 705 #define MAIR_DEV_nGRE ULL(0x8) 706 #define MAIR_DEV_GRE ULL(0xc) 707 708 /* 709 * MAIR encodings for normal memory attributes. 710 * 711 * Cache Policy 712 * WT: Write Through 713 * WB: Write Back 714 * NC: Non-Cacheable 715 * 716 * Transient Hint 717 * NTR: Non-Transient 718 * TR: Transient 719 * 720 * Allocation Policy 721 * RA: Read Allocate 722 * WA: Write Allocate 723 * RWA: Read and Write Allocate 724 * NA: No Allocation 725 */ 726 #define MAIR_NORM_WT_TR_WA ULL(0x1) 727 #define MAIR_NORM_WT_TR_RA ULL(0x2) 728 #define MAIR_NORM_WT_TR_RWA ULL(0x3) 729 #define MAIR_NORM_NC ULL(0x4) 730 #define MAIR_NORM_WB_TR_WA ULL(0x5) 731 #define MAIR_NORM_WB_TR_RA ULL(0x6) 732 #define MAIR_NORM_WB_TR_RWA ULL(0x7) 733 #define MAIR_NORM_WT_NTR_NA ULL(0x8) 734 #define MAIR_NORM_WT_NTR_WA ULL(0x9) 735 #define MAIR_NORM_WT_NTR_RA ULL(0xa) 736 #define MAIR_NORM_WT_NTR_RWA ULL(0xb) 737 #define MAIR_NORM_WB_NTR_NA ULL(0xc) 738 #define MAIR_NORM_WB_NTR_WA ULL(0xd) 739 #define MAIR_NORM_WB_NTR_RA ULL(0xe) 740 #define MAIR_NORM_WB_NTR_RWA ULL(0xf) 741 742 #define MAIR_NORM_OUTER_SHIFT U(4) 743 744 #define MAKE_MAIR_NORMAL_MEMORY(inner, outer) \ 745 ((inner) | ((outer) << MAIR_NORM_OUTER_SHIFT)) 746 747 /* PAR_EL1 fields */ 748 #define PAR_F_SHIFT U(0) 749 #define PAR_F_MASK ULL(0x1) 750 #define PAR_ADDR_SHIFT U(12) 751 #define PAR_ADDR_MASK (BIT(40) - ULL(1)) /* 40-bits-wide page address */ 752 753 /******************************************************************************* 754 * Definitions for system register interface to SPE 755 ******************************************************************************/ 756 #define PMBLIMITR_EL1 S3_0_C9_C10_0 757 758 /******************************************************************************* 759 * Definitions for system register interface to MPAM 760 ******************************************************************************/ 761 #define MPAMIDR_EL1 S3_0_C10_C4_4 762 #define MPAM2_EL2 S3_4_C10_C5_0 763 #define MPAMHCR_EL2 S3_4_C10_C4_0 764 #define MPAM3_EL3 S3_6_C10_C5_0 765 766 /******************************************************************************* 767 * Definitions for system register interface to AMU for ARMv8.4 onwards 768 ******************************************************************************/ 769 #define AMCR_EL0 S3_3_C13_C2_0 770 #define AMCFGR_EL0 S3_3_C13_C2_1 771 #define AMCGCR_EL0 S3_3_C13_C2_2 772 #define AMUSERENR_EL0 S3_3_C13_C2_3 773 #define AMCNTENCLR0_EL0 S3_3_C13_C2_4 774 #define AMCNTENSET0_EL0 S3_3_C13_C2_5 775 #define AMCNTENCLR1_EL0 S3_3_C13_C3_0 776 #define AMCNTENSET1_EL0 S3_3_C13_C3_1 777 778 /* Activity Monitor Group 0 Event Counter Registers */ 779 #define AMEVCNTR00_EL0 S3_3_C13_C4_0 780 #define AMEVCNTR01_EL0 S3_3_C13_C4_1 781 #define AMEVCNTR02_EL0 S3_3_C13_C4_2 782 #define AMEVCNTR03_EL0 S3_3_C13_C4_3 783 784 /* Activity Monitor Group 0 Event Type Registers */ 785 #define AMEVTYPER00_EL0 S3_3_C13_C6_0 786 #define AMEVTYPER01_EL0 S3_3_C13_C6_1 787 #define AMEVTYPER02_EL0 S3_3_C13_C6_2 788 #define AMEVTYPER03_EL0 S3_3_C13_C6_3 789 790 /* Activity Monitor Group 1 Event Counter Registers */ 791 #define AMEVCNTR10_EL0 S3_3_C13_C12_0 792 #define AMEVCNTR11_EL0 S3_3_C13_C12_1 793 #define AMEVCNTR12_EL0 S3_3_C13_C12_2 794 #define AMEVCNTR13_EL0 S3_3_C13_C12_3 795 #define AMEVCNTR14_EL0 S3_3_C13_C12_4 796 #define AMEVCNTR15_EL0 S3_3_C13_C12_5 797 #define AMEVCNTR16_EL0 S3_3_C13_C12_6 798 #define AMEVCNTR17_EL0 S3_3_C13_C12_7 799 #define AMEVCNTR18_EL0 S3_3_C13_C13_0 800 #define AMEVCNTR19_EL0 S3_3_C13_C13_1 801 #define AMEVCNTR1A_EL0 S3_3_C13_C13_2 802 #define AMEVCNTR1B_EL0 S3_3_C13_C13_3 803 #define AMEVCNTR1C_EL0 S3_3_C13_C13_4 804 #define AMEVCNTR1D_EL0 S3_3_C13_C13_5 805 #define AMEVCNTR1E_EL0 S3_3_C13_C13_6 806 #define AMEVCNTR1F_EL0 S3_3_C13_C13_7 807 808 /* Activity Monitor Group 1 Event Type Registers */ 809 #define AMEVTYPER10_EL0 S3_3_C13_C14_0 810 #define AMEVTYPER11_EL0 S3_3_C13_C14_1 811 #define AMEVTYPER12_EL0 S3_3_C13_C14_2 812 #define AMEVTYPER13_EL0 S3_3_C13_C14_3 813 #define AMEVTYPER14_EL0 S3_3_C13_C14_4 814 #define AMEVTYPER15_EL0 S3_3_C13_C14_5 815 #define AMEVTYPER16_EL0 S3_3_C13_C14_6 816 #define AMEVTYPER17_EL0 S3_3_C13_C14_7 817 #define AMEVTYPER18_EL0 S3_3_C13_C15_0 818 #define AMEVTYPER19_EL0 S3_3_C13_C15_1 819 #define AMEVTYPER1A_EL0 S3_3_C13_C15_2 820 #define AMEVTYPER1B_EL0 S3_3_C13_C15_3 821 #define AMEVTYPER1C_EL0 S3_3_C13_C15_4 822 #define AMEVTYPER1D_EL0 S3_3_C13_C15_5 823 #define AMEVTYPER1E_EL0 S3_3_C13_C15_6 824 #define AMEVTYPER1F_EL0 S3_3_C13_C15_7 825 826 /* AMCGCR_EL0 definitions */ 827 #define AMCGCR_EL0_CG1NC_SHIFT U(8) 828 #define AMCGCR_EL0_CG1NC_LENGTH U(8) 829 #define AMCGCR_EL0_CG1NC_MASK U(0xff) 830 831 /* MPAM register definitions */ 832 #define MPAM3_EL3_MPAMEN_BIT (ULL(1) << 63) 833 #define MPAMHCR_EL2_TRAP_MPAMIDR_EL1 (ULL(1) << 31) 834 835 #define MPAM2_EL2_TRAPMPAM0EL1 (ULL(1) << 49) 836 #define MPAM2_EL2_TRAPMPAM1EL1 (ULL(1) << 48) 837 838 #define MPAMIDR_HAS_HCR_BIT (ULL(1) << 17) 839 840 /******************************************************************************* 841 * RAS system registers 842 ******************************************************************************/ 843 #define DISR_EL1 S3_0_C12_C1_1 844 #define DISR_A_BIT U(31) 845 846 #define ERRIDR_EL1 S3_0_C5_C3_0 847 #define ERRIDR_MASK U(0xffff) 848 849 #define ERRSELR_EL1 S3_0_C5_C3_1 850 851 /* System register access to Standard Error Record registers */ 852 #define ERXFR_EL1 S3_0_C5_C4_0 853 #define ERXCTLR_EL1 S3_0_C5_C4_1 854 #define ERXSTATUS_EL1 S3_0_C5_C4_2 855 #define ERXADDR_EL1 S3_0_C5_C4_3 856 #define ERXPFGF_EL1 S3_0_C5_C4_4 857 #define ERXPFGCTL_EL1 S3_0_C5_C4_5 858 #define ERXPFGCDN_EL1 S3_0_C5_C4_6 859 #define ERXMISC0_EL1 S3_0_C5_C5_0 860 #define ERXMISC1_EL1 S3_0_C5_C5_1 861 862 #define ERXCTLR_ED_BIT (U(1) << 0) 863 #define ERXCTLR_UE_BIT (U(1) << 4) 864 865 #define ERXPFGCTL_UC_BIT (U(1) << 1) 866 #define ERXPFGCTL_UEU_BIT (U(1) << 2) 867 #define ERXPFGCTL_CDEN_BIT (U(1) << 31) 868 869 /******************************************************************************* 870 * Armv8.3 Pointer Authentication Registers 871 ******************************************************************************/ 872 #define APIAKeyLo_EL1 S3_0_C2_C1_0 873 #define APIAKeyHi_EL1 S3_0_C2_C1_1 874 #define APIBKeyLo_EL1 S3_0_C2_C1_2 875 #define APIBKeyHi_EL1 S3_0_C2_C1_3 876 #define APDAKeyLo_EL1 S3_0_C2_C2_0 877 #define APDAKeyHi_EL1 S3_0_C2_C2_1 878 #define APDBKeyLo_EL1 S3_0_C2_C2_2 879 #define APDBKeyHi_EL1 S3_0_C2_C2_3 880 #define APGAKeyLo_EL1 S3_0_C2_C3_0 881 #define APGAKeyHi_EL1 S3_0_C2_C3_1 882 883 /******************************************************************************* 884 * Armv8.4 Data Independent Timing Registers 885 ******************************************************************************/ 886 #define DIT S3_3_C4_C2_5 887 #define DIT_BIT BIT(24) 888 889 /******************************************************************************* 890 * Armv8.5 - new MSR encoding to directly access PSTATE.SSBS field 891 ******************************************************************************/ 892 #define SSBS S3_3_C4_C2_6 893 894 #endif /* ARCH_H */ 895