1 /* 2 * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2020-2022, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef ARCH_H 9 #define ARCH_H 10 11 #include <lib/utils_def.h> 12 13 /******************************************************************************* 14 * MIDR bit definitions 15 ******************************************************************************/ 16 #define MIDR_IMPL_MASK U(0xff) 17 #define MIDR_IMPL_SHIFT U(0x18) 18 #define MIDR_VAR_SHIFT U(20) 19 #define MIDR_VAR_BITS U(4) 20 #define MIDR_VAR_MASK U(0xf) 21 #define MIDR_REV_SHIFT U(0) 22 #define MIDR_REV_BITS U(4) 23 #define MIDR_REV_MASK U(0xf) 24 #define MIDR_PN_MASK U(0xfff) 25 #define MIDR_PN_SHIFT U(0x4) 26 27 /******************************************************************************* 28 * MPIDR macros 29 ******************************************************************************/ 30 #define MPIDR_MT_MASK (ULL(1) << 24) 31 #define MPIDR_CPU_MASK MPIDR_AFFLVL_MASK 32 #define MPIDR_CLUSTER_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS) 33 #define MPIDR_AFFINITY_BITS U(8) 34 #define MPIDR_AFFLVL_MASK ULL(0xff) 35 #define MPIDR_AFF0_SHIFT U(0) 36 #define MPIDR_AFF1_SHIFT U(8) 37 #define MPIDR_AFF2_SHIFT U(16) 38 #define MPIDR_AFF3_SHIFT U(32) 39 #define MPIDR_AFF_SHIFT(_n) MPIDR_AFF##_n##_SHIFT 40 #define MPIDR_AFFINITY_MASK ULL(0xff00ffffff) 41 #define MPIDR_AFFLVL_SHIFT U(3) 42 #define MPIDR_AFFLVL0 ULL(0x0) 43 #define MPIDR_AFFLVL1 ULL(0x1) 44 #define MPIDR_AFFLVL2 ULL(0x2) 45 #define MPIDR_AFFLVL3 ULL(0x3) 46 #define MPIDR_AFFLVL(_n) MPIDR_AFFLVL##_n 47 #define MPIDR_AFFLVL0_VAL(mpidr) \ 48 (((mpidr) >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK) 49 #define MPIDR_AFFLVL1_VAL(mpidr) \ 50 (((mpidr) >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK) 51 #define MPIDR_AFFLVL2_VAL(mpidr) \ 52 (((mpidr) >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK) 53 #define MPIDR_AFFLVL3_VAL(mpidr) \ 54 (((mpidr) >> MPIDR_AFF3_SHIFT) & MPIDR_AFFLVL_MASK) 55 /* 56 * The MPIDR_MAX_AFFLVL count starts from 0. Take care to 57 * add one while using this macro to define array sizes. 58 * TODO: Support only the first 3 affinity levels for now. 59 */ 60 #define MPIDR_MAX_AFFLVL U(2) 61 62 #define MPID_MASK (MPIDR_MT_MASK | \ 63 (MPIDR_AFFLVL_MASK << MPIDR_AFF3_SHIFT) | \ 64 (MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT) | \ 65 (MPIDR_AFFLVL_MASK << MPIDR_AFF1_SHIFT) | \ 66 (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT)) 67 68 #define MPIDR_AFF_ID(mpid, n) \ 69 (((mpid) >> MPIDR_AFF_SHIFT(n)) & MPIDR_AFFLVL_MASK) 70 71 /* 72 * An invalid MPID. This value can be used by functions that return an MPID to 73 * indicate an error. 74 */ 75 #define INVALID_MPID U(0xFFFFFFFF) 76 77 /******************************************************************************* 78 * Definitions for CPU system register interface to GICv3 79 ******************************************************************************/ 80 #define ICC_IGRPEN1_EL1 S3_0_C12_C12_7 81 #define ICC_SGI1R S3_0_C12_C11_5 82 #define ICC_ASGI1R S3_0_C12_C11_6 83 #define ICC_SRE_EL1 S3_0_C12_C12_5 84 #define ICC_SRE_EL2 S3_4_C12_C9_5 85 #define ICC_SRE_EL3 S3_6_C12_C12_5 86 #define ICC_CTLR_EL1 S3_0_C12_C12_4 87 #define ICC_CTLR_EL3 S3_6_C12_C12_4 88 #define ICC_PMR_EL1 S3_0_C4_C6_0 89 #define ICC_RPR_EL1 S3_0_C12_C11_3 90 #define ICC_IGRPEN1_EL3 S3_6_c12_c12_7 91 #define ICC_IGRPEN0_EL1 S3_0_c12_c12_6 92 #define ICC_HPPIR0_EL1 S3_0_c12_c8_2 93 #define ICC_HPPIR1_EL1 S3_0_c12_c12_2 94 #define ICC_IAR0_EL1 S3_0_c12_c8_0 95 #define ICC_IAR1_EL1 S3_0_c12_c12_0 96 #define ICC_EOIR0_EL1 S3_0_c12_c8_1 97 #define ICC_EOIR1_EL1 S3_0_c12_c12_1 98 #define ICC_SGI0R_EL1 S3_0_c12_c11_7 99 100 /******************************************************************************* 101 * Definitions for EL2 system registers for save/restore routine 102 ******************************************************************************/ 103 #define CNTPOFF_EL2 S3_4_C14_C0_6 104 #define HAFGRTR_EL2 S3_4_C3_C1_6 105 #define HDFGRTR_EL2 S3_4_C3_C1_4 106 #define HDFGWTR_EL2 S3_4_C3_C1_5 107 #define HFGITR_EL2 S3_4_C1_C1_6 108 #define HFGRTR_EL2 S3_4_C1_C1_4 109 #define HFGWTR_EL2 S3_4_C1_C1_5 110 #define ICH_HCR_EL2 S3_4_C12_C11_0 111 #define ICH_VMCR_EL2 S3_4_C12_C11_7 112 #define MPAMVPM0_EL2 S3_4_C10_C6_0 113 #define MPAMVPM1_EL2 S3_4_C10_C6_1 114 #define MPAMVPM2_EL2 S3_4_C10_C6_2 115 #define MPAMVPM3_EL2 S3_4_C10_C6_3 116 #define MPAMVPM4_EL2 S3_4_C10_C6_4 117 #define MPAMVPM5_EL2 S3_4_C10_C6_5 118 #define MPAMVPM6_EL2 S3_4_C10_C6_6 119 #define MPAMVPM7_EL2 S3_4_C10_C6_7 120 #define MPAMVPMV_EL2 S3_4_C10_C4_1 121 #define TRFCR_EL2 S3_4_C1_C2_1 122 #define VNCR_EL2 S3_4_C2_C2_0 123 #define PMSCR_EL2 S3_4_C9_C9_0 124 #define TFSR_EL2 S3_4_C5_C6_0 125 #define CONTEXTIDR_EL2 S3_4_C13_C0_1 126 #define TTBR1_EL2 S3_4_C2_C0_1 127 128 /******************************************************************************* 129 * Generic timer memory mapped registers & offsets 130 ******************************************************************************/ 131 #define CNTCR_OFF U(0x000) 132 #define CNTCV_OFF U(0x008) 133 #define CNTFID_OFF U(0x020) 134 135 #define CNTCR_EN (U(1) << 0) 136 #define CNTCR_HDBG (U(1) << 1) 137 #define CNTCR_FCREQ(x) ((x) << 8) 138 139 /******************************************************************************* 140 * System register bit definitions 141 ******************************************************************************/ 142 /* CLIDR definitions */ 143 #define LOUIS_SHIFT U(21) 144 #define LOC_SHIFT U(24) 145 #define CTYPE_SHIFT(n) U(3 * (n - 1)) 146 #define CLIDR_FIELD_WIDTH U(3) 147 148 /* CSSELR definitions */ 149 #define LEVEL_SHIFT U(1) 150 151 /* Data cache set/way op type defines */ 152 #define DCISW U(0x0) 153 #define DCCISW U(0x1) 154 #if ERRATA_A53_827319 155 #define DCCSW DCCISW 156 #else 157 #define DCCSW U(0x2) 158 #endif 159 160 /* ID_AA64PFR0_EL1 definitions */ 161 #define ID_AA64PFR0_EL0_SHIFT U(0) 162 #define ID_AA64PFR0_EL1_SHIFT U(4) 163 #define ID_AA64PFR0_EL2_SHIFT U(8) 164 #define ID_AA64PFR0_EL3_SHIFT U(12) 165 166 #define ID_AA64PFR0_AMU_SHIFT U(44) 167 #define ID_AA64PFR0_AMU_MASK ULL(0xf) 168 #define ID_AA64PFR0_AMU_NOT_SUPPORTED U(0x0) 169 #define ID_AA64PFR0_AMU_V1 ULL(0x1) 170 #define ID_AA64PFR0_AMU_V1P1 U(0x2) 171 172 #define ID_AA64PFR0_ELX_MASK ULL(0xf) 173 174 #define ID_AA64PFR0_GIC_SHIFT U(24) 175 #define ID_AA64PFR0_GIC_WIDTH U(4) 176 #define ID_AA64PFR0_GIC_MASK ULL(0xf) 177 178 #define ID_AA64PFR0_SVE_SHIFT U(32) 179 #define ID_AA64PFR0_SVE_MASK ULL(0xf) 180 #define ID_AA64PFR0_SVE_SUPPORTED ULL(0x1) 181 #define ID_AA64PFR0_SVE_LENGTH U(4) 182 183 #define ID_AA64PFR0_SEL2_SHIFT U(36) 184 #define ID_AA64PFR0_SEL2_MASK ULL(0xf) 185 186 #define ID_AA64PFR0_MPAM_SHIFT U(40) 187 #define ID_AA64PFR0_MPAM_MASK ULL(0xf) 188 189 #define ID_AA64PFR0_DIT_SHIFT U(48) 190 #define ID_AA64PFR0_DIT_MASK ULL(0xf) 191 #define ID_AA64PFR0_DIT_LENGTH U(4) 192 #define ID_AA64PFR0_DIT_SUPPORTED U(1) 193 194 #define ID_AA64PFR0_CSV2_SHIFT U(56) 195 #define ID_AA64PFR0_CSV2_MASK ULL(0xf) 196 #define ID_AA64PFR0_CSV2_LENGTH U(4) 197 #define ID_AA64PFR0_CSV2_2_SUPPORTED ULL(0x2) 198 199 #define ID_AA64PFR0_FEAT_RME_SHIFT U(52) 200 #define ID_AA64PFR0_FEAT_RME_MASK ULL(0xf) 201 #define ID_AA64PFR0_FEAT_RME_LENGTH U(4) 202 #define ID_AA64PFR0_FEAT_RME_NOT_SUPPORTED U(0) 203 #define ID_AA64PFR0_FEAT_RME_V1 U(1) 204 205 #define ID_AA64PFR0_RAS_SHIFT U(28) 206 #define ID_AA64PFR0_RAS_MASK ULL(0xf) 207 #define ID_AA64PFR0_RAS_NOT_SUPPORTED ULL(0x0) 208 #define ID_AA64PFR0_RAS_LENGTH U(4) 209 210 /* Exception level handling */ 211 #define EL_IMPL_NONE ULL(0) 212 #define EL_IMPL_A64ONLY ULL(1) 213 #define EL_IMPL_A64_A32 ULL(2) 214 215 /* ID_AA64DFR0_EL1.TraceVer definitions */ 216 #define ID_AA64DFR0_TRACEVER_SHIFT U(4) 217 #define ID_AA64DFR0_TRACEVER_MASK ULL(0xf) 218 #define ID_AA64DFR0_TRACEVER_SUPPORTED ULL(1) 219 #define ID_AA64DFR0_TRACEVER_LENGTH U(4) 220 #define ID_AA64DFR0_TRACEFILT_SHIFT U(40) 221 #define ID_AA64DFR0_TRACEFILT_MASK U(0xf) 222 #define ID_AA64DFR0_TRACEFILT_SUPPORTED U(1) 223 #define ID_AA64DFR0_TRACEFILT_LENGTH U(4) 224 #define ID_AA64DFR0_PMUVER_LENGTH U(4) 225 #define ID_AA64DFR0_PMUVER_SHIFT U(8) 226 #define ID_AA64DFR0_PMUVER_MASK U(0xf) 227 #define ID_AA64DFR0_PMUVER_PMUV3 U(1) 228 #define ID_AA64DFR0_PMUVER_PMUV3P7 U(7) 229 #define ID_AA64DFR0_PMUVER_IMP_DEF U(0xf) 230 231 /* ID_AA64DFR0_EL1.PMS definitions (for ARMv8.2+) */ 232 #define ID_AA64DFR0_PMS_SHIFT U(32) 233 #define ID_AA64DFR0_PMS_MASK ULL(0xf) 234 #define ID_AA64DFR0_SPE_SUPPORTED ULL(0x1) 235 #define ID_AA64DFR0_SPE_NOT_SUPPORTED ULL(0x0) 236 237 /* ID_AA64DFR0_EL1.TraceBuffer definitions */ 238 #define ID_AA64DFR0_TRACEBUFFER_SHIFT U(44) 239 #define ID_AA64DFR0_TRACEBUFFER_MASK ULL(0xf) 240 #define ID_AA64DFR0_TRACEBUFFER_SUPPORTED ULL(1) 241 242 /* ID_AA64DFR0_EL1.MTPMU definitions (for ARMv8.6+) */ 243 #define ID_AA64DFR0_MTPMU_SHIFT U(48) 244 #define ID_AA64DFR0_MTPMU_MASK ULL(0xf) 245 #define ID_AA64DFR0_MTPMU_SUPPORTED ULL(1) 246 #define ID_AA64DFR0_MTPMU_DISABLED ULL(15) 247 248 /* ID_AA64DFR0_EL1.BRBE definitions */ 249 #define ID_AA64DFR0_BRBE_SHIFT U(52) 250 #define ID_AA64DFR0_BRBE_MASK ULL(0xf) 251 #define ID_AA64DFR0_BRBE_SUPPORTED ULL(1) 252 253 /* ID_AA64ISAR0_EL1 definitions */ 254 #define ID_AA64ISAR0_RNDR_SHIFT U(60) 255 #define ID_AA64ISAR0_RNDR_MASK ULL(0xf) 256 257 /* ID_AA64ISAR1_EL1 definitions */ 258 #define ID_AA64ISAR1_EL1 S3_0_C0_C6_1 259 260 #define ID_AA64ISAR1_GPI_SHIFT U(28) 261 #define ID_AA64ISAR1_GPI_MASK ULL(0xf) 262 #define ID_AA64ISAR1_GPA_SHIFT U(24) 263 #define ID_AA64ISAR1_GPA_MASK ULL(0xf) 264 265 #define ID_AA64ISAR1_API_SHIFT U(8) 266 #define ID_AA64ISAR1_API_MASK ULL(0xf) 267 #define ID_AA64ISAR1_APA_SHIFT U(4) 268 #define ID_AA64ISAR1_APA_MASK ULL(0xf) 269 270 #define ID_AA64ISAR1_SB_SHIFT U(36) 271 #define ID_AA64ISAR1_SB_MASK ULL(0xf) 272 #define ID_AA64ISAR1_SB_SUPPORTED ULL(0x1) 273 #define ID_AA64ISAR1_SB_NOT_SUPPORTED ULL(0x0) 274 275 /* ID_AA64ISAR2_EL1 definitions */ 276 #define ID_AA64ISAR2_EL1 S3_0_C0_C6_2 277 278 #define ID_AA64ISAR2_GPA3_SHIFT U(8) 279 #define ID_AA64ISAR2_GPA3_MASK ULL(0xf) 280 281 #define ID_AA64ISAR2_APA3_SHIFT U(12) 282 #define ID_AA64ISAR2_APA3_MASK ULL(0xf) 283 284 /* ID_AA64MMFR0_EL1 definitions */ 285 #define ID_AA64MMFR0_EL1_PARANGE_SHIFT U(0) 286 #define ID_AA64MMFR0_EL1_PARANGE_MASK ULL(0xf) 287 288 #define PARANGE_0000 U(32) 289 #define PARANGE_0001 U(36) 290 #define PARANGE_0010 U(40) 291 #define PARANGE_0011 U(42) 292 #define PARANGE_0100 U(44) 293 #define PARANGE_0101 U(48) 294 #define PARANGE_0110 U(52) 295 296 #define ID_AA64MMFR0_EL1_ECV_SHIFT U(60) 297 #define ID_AA64MMFR0_EL1_ECV_MASK ULL(0xf) 298 #define ID_AA64MMFR0_EL1_ECV_NOT_SUPPORTED ULL(0x0) 299 #define ID_AA64MMFR0_EL1_ECV_SUPPORTED ULL(0x1) 300 #define ID_AA64MMFR0_EL1_ECV_SELF_SYNCH ULL(0x2) 301 302 #define ID_AA64MMFR0_EL1_FGT_SHIFT U(56) 303 #define ID_AA64MMFR0_EL1_FGT_MASK ULL(0xf) 304 #define ID_AA64MMFR0_EL1_FGT_SUPPORTED ULL(0x1) 305 #define ID_AA64MMFR0_EL1_FGT_NOT_SUPPORTED ULL(0x0) 306 307 #define ID_AA64MMFR0_EL1_TGRAN4_SHIFT U(28) 308 #define ID_AA64MMFR0_EL1_TGRAN4_MASK ULL(0xf) 309 #define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED ULL(0x0) 310 #define ID_AA64MMFR0_EL1_TGRAN4_52B_SUPPORTED ULL(0x1) 311 #define ID_AA64MMFR0_EL1_TGRAN4_NOT_SUPPORTED ULL(0xf) 312 313 #define ID_AA64MMFR0_EL1_TGRAN64_SHIFT U(24) 314 #define ID_AA64MMFR0_EL1_TGRAN64_MASK ULL(0xf) 315 #define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED ULL(0x0) 316 #define ID_AA64MMFR0_EL1_TGRAN64_NOT_SUPPORTED ULL(0xf) 317 318 #define ID_AA64MMFR0_EL1_TGRAN16_SHIFT U(20) 319 #define ID_AA64MMFR0_EL1_TGRAN16_MASK ULL(0xf) 320 #define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED ULL(0x1) 321 #define ID_AA64MMFR0_EL1_TGRAN16_NOT_SUPPORTED ULL(0x0) 322 #define ID_AA64MMFR0_EL1_TGRAN16_52B_SUPPORTED ULL(0x2) 323 324 /* ID_AA64MMFR1_EL1 definitions */ 325 #define ID_AA64MMFR1_EL1_TWED_SHIFT U(32) 326 #define ID_AA64MMFR1_EL1_TWED_MASK ULL(0xf) 327 #define ID_AA64MMFR1_EL1_TWED_SUPPORTED ULL(0x1) 328 #define ID_AA64MMFR1_EL1_TWED_NOT_SUPPORTED ULL(0x0) 329 330 #define ID_AA64MMFR1_EL1_PAN_SHIFT U(20) 331 #define ID_AA64MMFR1_EL1_PAN_MASK ULL(0xf) 332 #define ID_AA64MMFR1_EL1_PAN_NOT_SUPPORTED ULL(0x0) 333 #define ID_AA64MMFR1_EL1_PAN_SUPPORTED ULL(0x1) 334 #define ID_AA64MMFR1_EL1_PAN2_SUPPORTED ULL(0x2) 335 #define ID_AA64MMFR1_EL1_PAN3_SUPPORTED ULL(0x3) 336 337 #define ID_AA64MMFR1_EL1_VHE_SHIFT U(8) 338 #define ID_AA64MMFR1_EL1_VHE_MASK ULL(0xf) 339 340 #define ID_AA64MMFR1_EL1_HCX_SHIFT U(40) 341 #define ID_AA64MMFR1_EL1_HCX_MASK ULL(0xf) 342 #define ID_AA64MMFR1_EL1_HCX_SUPPORTED ULL(0x1) 343 #define ID_AA64MMFR1_EL1_HCX_NOT_SUPPORTED ULL(0x0) 344 345 /* ID_AA64MMFR2_EL1 definitions */ 346 #define ID_AA64MMFR2_EL1 S3_0_C0_C7_2 347 348 #define ID_AA64MMFR2_EL1_ST_SHIFT U(28) 349 #define ID_AA64MMFR2_EL1_ST_MASK ULL(0xf) 350 351 #define ID_AA64MMFR2_EL1_CCIDX_SHIFT U(20) 352 #define ID_AA64MMFR2_EL1_CCIDX_MASK ULL(0xf) 353 #define ID_AA64MMFR2_EL1_CCIDX_LENGTH U(4) 354 355 #define ID_AA64MMFR2_EL1_CNP_SHIFT U(0) 356 #define ID_AA64MMFR2_EL1_CNP_MASK ULL(0xf) 357 358 #define ID_AA64MMFR2_EL1_NV_SHIFT U(24) 359 #define ID_AA64MMFR2_EL1_NV_MASK ULL(0xf) 360 #define ID_AA64MMFR2_EL1_NV_NOT_SUPPORTED ULL(0x0) 361 #define ID_AA64MMFR2_EL1_NV_SUPPORTED ULL(0x1) 362 #define ID_AA64MMFR2_EL1_NV2_SUPPORTED ULL(0x2) 363 364 /* ID_AA64MMFR3_EL1 definitions */ 365 #define ID_AA64MMFR3_EL1 S3_0_C0_C7_3 366 367 #define ID_AA64MMFR3_EL1_S2POE_SHIFT U(20) 368 #define ID_AA64MMFR3_EL1_S2POE_MASK ULL(0xf) 369 370 #define ID_AA64MMFR3_EL1_S1POE_SHIFT U(16) 371 #define ID_AA64MMFR3_EL1_S1POE_MASK ULL(0xf) 372 373 #define ID_AA64MMFR3_EL1_S2PIE_SHIFT U(12) 374 #define ID_AA64MMFR3_EL1_S2PIE_MASK ULL(0xf) 375 376 #define ID_AA64MMFR3_EL1_S1PIE_SHIFT U(8) 377 #define ID_AA64MMFR3_EL1_S1PIE_MASK ULL(0xf) 378 379 #define ID_AA64MMFR3_EL1_TCRX_SHIFT U(0) 380 #define ID_AA64MMFR3_EL1_TCRX_MASK ULL(0xf) 381 382 /* ID_AA64PFR1_EL1 definitions */ 383 #define ID_AA64PFR1_EL1_GCS_SHIFT U(44) 384 #define ID_AA64PFR1_EL1_GCS_MASK ULL(0xf) 385 386 #define ID_AA64PFR1_EL1_SSBS_SHIFT U(4) 387 #define ID_AA64PFR1_EL1_SSBS_MASK ULL(0xf) 388 389 #define SSBS_UNAVAILABLE ULL(0) /* No architectural SSBS support */ 390 391 #define ID_AA64PFR1_EL1_BT_SHIFT U(0) 392 #define ID_AA64PFR1_EL1_BT_MASK ULL(0xf) 393 394 #define BTI_IMPLEMENTED ULL(1) /* The BTI mechanism is implemented */ 395 396 #define ID_AA64PFR1_EL1_MTE_SHIFT U(8) 397 #define ID_AA64PFR1_EL1_MTE_MASK ULL(0xf) 398 399 #define ID_AA64PFR1_EL1_RNDR_TRAP_SHIFT U(28) 400 #define ID_AA64PFR1_EL1_RNDR_TRAP_MASK U(0xf) 401 402 #define ID_AA64PFR1_EL1_RNG_TRAP_SUPPORTED ULL(0x1) 403 #define ID_AA64PFR1_EL1_RNG_TRAP_NOT_SUPPORTED ULL(0x0) 404 405 #define VDISR_EL2 S3_4_C12_C1_1 406 #define VSESR_EL2 S3_4_C5_C2_3 407 408 /* Memory Tagging Extension is not implemented */ 409 #define MTE_UNIMPLEMENTED U(0) 410 /* FEAT_MTE: MTE instructions accessible at EL0 are implemented */ 411 #define MTE_IMPLEMENTED_EL0 U(1) 412 /* FEAT_MTE2: Full MTE is implemented */ 413 #define MTE_IMPLEMENTED_ELX U(2) 414 /* 415 * FEAT_MTE3: MTE is implemented with support for 416 * asymmetric Tag Check Fault handling 417 */ 418 #define MTE_IMPLEMENTED_ASY U(3) 419 420 #define ID_AA64PFR1_MPAM_FRAC_SHIFT ULL(16) 421 #define ID_AA64PFR1_MPAM_FRAC_MASK ULL(0xf) 422 423 #define ID_AA64PFR1_EL1_SME_SHIFT U(24) 424 #define ID_AA64PFR1_EL1_SME_MASK ULL(0xf) 425 #define ID_AA64PFR1_EL1_SME_NOT_SUPPORTED ULL(0x0) 426 #define ID_AA64PFR1_EL1_SME_SUPPORTED ULL(0x1) 427 #define ID_AA64PFR1_EL1_SME2_SUPPORTED ULL(0x2) 428 429 /* ID_PFR1_EL1 definitions */ 430 #define ID_PFR1_VIRTEXT_SHIFT U(12) 431 #define ID_PFR1_VIRTEXT_MASK U(0xf) 432 #define GET_VIRT_EXT(id) (((id) >> ID_PFR1_VIRTEXT_SHIFT) \ 433 & ID_PFR1_VIRTEXT_MASK) 434 435 /* SCTLR definitions */ 436 #define SCTLR_EL2_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ 437 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \ 438 (U(1) << 11) | (U(1) << 5) | (U(1) << 4)) 439 440 #define SCTLR_EL1_RES1 ((UL(1) << 29) | (UL(1) << 28) | (UL(1) << 23) | \ 441 (UL(1) << 22) | (UL(1) << 20) | (UL(1) << 11)) 442 443 #define SCTLR_AARCH32_EL1_RES1 \ 444 ((U(1) << 23) | (U(1) << 22) | (U(1) << 11) | \ 445 (U(1) << 4) | (U(1) << 3)) 446 447 #define SCTLR_EL3_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ 448 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \ 449 (U(1) << 11) | (U(1) << 5) | (U(1) << 4)) 450 451 #define SCTLR_M_BIT (ULL(1) << 0) 452 #define SCTLR_A_BIT (ULL(1) << 1) 453 #define SCTLR_C_BIT (ULL(1) << 2) 454 #define SCTLR_SA_BIT (ULL(1) << 3) 455 #define SCTLR_SA0_BIT (ULL(1) << 4) 456 #define SCTLR_CP15BEN_BIT (ULL(1) << 5) 457 #define SCTLR_nAA_BIT (ULL(1) << 6) 458 #define SCTLR_ITD_BIT (ULL(1) << 7) 459 #define SCTLR_SED_BIT (ULL(1) << 8) 460 #define SCTLR_UMA_BIT (ULL(1) << 9) 461 #define SCTLR_EnRCTX_BIT (ULL(1) << 10) 462 #define SCTLR_EOS_BIT (ULL(1) << 11) 463 #define SCTLR_I_BIT (ULL(1) << 12) 464 #define SCTLR_EnDB_BIT (ULL(1) << 13) 465 #define SCTLR_DZE_BIT (ULL(1) << 14) 466 #define SCTLR_UCT_BIT (ULL(1) << 15) 467 #define SCTLR_NTWI_BIT (ULL(1) << 16) 468 #define SCTLR_NTWE_BIT (ULL(1) << 18) 469 #define SCTLR_WXN_BIT (ULL(1) << 19) 470 #define SCTLR_TSCXT_BIT (ULL(1) << 20) 471 #define SCTLR_IESB_BIT (ULL(1) << 21) 472 #define SCTLR_EIS_BIT (ULL(1) << 22) 473 #define SCTLR_SPAN_BIT (ULL(1) << 23) 474 #define SCTLR_E0E_BIT (ULL(1) << 24) 475 #define SCTLR_EE_BIT (ULL(1) << 25) 476 #define SCTLR_UCI_BIT (ULL(1) << 26) 477 #define SCTLR_EnDA_BIT (ULL(1) << 27) 478 #define SCTLR_nTLSMD_BIT (ULL(1) << 28) 479 #define SCTLR_LSMAOE_BIT (ULL(1) << 29) 480 #define SCTLR_EnIB_BIT (ULL(1) << 30) 481 #define SCTLR_EnIA_BIT (ULL(1) << 31) 482 #define SCTLR_BT0_BIT (ULL(1) << 35) 483 #define SCTLR_BT1_BIT (ULL(1) << 36) 484 #define SCTLR_BT_BIT (ULL(1) << 36) 485 #define SCTLR_ITFSB_BIT (ULL(1) << 37) 486 #define SCTLR_TCF0_SHIFT U(38) 487 #define SCTLR_TCF0_MASK ULL(3) 488 #define SCTLR_ENTP2_BIT (ULL(1) << 60) 489 490 /* Tag Check Faults in EL0 have no effect on the PE */ 491 #define SCTLR_TCF0_NO_EFFECT U(0) 492 /* Tag Check Faults in EL0 cause a synchronous exception */ 493 #define SCTLR_TCF0_SYNC U(1) 494 /* Tag Check Faults in EL0 are asynchronously accumulated */ 495 #define SCTLR_TCF0_ASYNC U(2) 496 /* 497 * Tag Check Faults in EL0 cause a synchronous exception on reads, 498 * and are asynchronously accumulated on writes 499 */ 500 #define SCTLR_TCF0_SYNCR_ASYNCW U(3) 501 502 #define SCTLR_TCF_SHIFT U(40) 503 #define SCTLR_TCF_MASK ULL(3) 504 505 /* Tag Check Faults in EL1 have no effect on the PE */ 506 #define SCTLR_TCF_NO_EFFECT U(0) 507 /* Tag Check Faults in EL1 cause a synchronous exception */ 508 #define SCTLR_TCF_SYNC U(1) 509 /* Tag Check Faults in EL1 are asynchronously accumulated */ 510 #define SCTLR_TCF_ASYNC U(2) 511 /* 512 * Tag Check Faults in EL1 cause a synchronous exception on reads, 513 * and are asynchronously accumulated on writes 514 */ 515 #define SCTLR_TCF_SYNCR_ASYNCW U(3) 516 517 #define SCTLR_ATA0_BIT (ULL(1) << 42) 518 #define SCTLR_ATA_BIT (ULL(1) << 43) 519 #define SCTLR_DSSBS_SHIFT U(44) 520 #define SCTLR_DSSBS_BIT (ULL(1) << SCTLR_DSSBS_SHIFT) 521 #define SCTLR_TWEDEn_BIT (ULL(1) << 45) 522 #define SCTLR_TWEDEL_SHIFT U(46) 523 #define SCTLR_TWEDEL_MASK ULL(0xf) 524 #define SCTLR_EnASR_BIT (ULL(1) << 54) 525 #define SCTLR_EnAS0_BIT (ULL(1) << 55) 526 #define SCTLR_EnALS_BIT (ULL(1) << 56) 527 #define SCTLR_EPAN_BIT (ULL(1) << 57) 528 #define SCTLR_RESET_VAL SCTLR_EL3_RES1 529 530 /* CPACR_EL1 definitions */ 531 #define CPACR_EL1_FPEN(x) ((x) << 20) 532 #define CPACR_EL1_FP_TRAP_EL0 UL(0x1) 533 #define CPACR_EL1_FP_TRAP_ALL UL(0x2) 534 #define CPACR_EL1_FP_TRAP_NONE UL(0x3) 535 #define CPACR_EL1_SMEN_SHIFT U(24) 536 #define CPACR_EL1_SMEN_MASK ULL(0x3) 537 538 /* SCR definitions */ 539 #define SCR_RES1_BITS ((U(1) << 4) | (U(1) << 5)) 540 #define SCR_NSE_SHIFT U(62) 541 #define SCR_NSE_BIT (ULL(1) << SCR_NSE_SHIFT) 542 #define SCR_GPF_BIT (UL(1) << 48) 543 #define SCR_TWEDEL_SHIFT U(30) 544 #define SCR_TWEDEL_MASK ULL(0xf) 545 #define SCR_PIEN_BIT (UL(1) << 45) 546 #define SCR_TCR2EN_BIT (UL(1) << 43) 547 #define SCR_TRNDR_BIT (UL(1) << 40) 548 #define SCR_GCSEn_BIT (UL(1) << 39) 549 #define SCR_HXEn_BIT (UL(1) << 38) 550 #define SCR_ENTP2_SHIFT U(41) 551 #define SCR_ENTP2_BIT (UL(1) << SCR_ENTP2_SHIFT) 552 #define SCR_AMVOFFEN_SHIFT U(35) 553 #define SCR_AMVOFFEN_BIT (UL(1) << SCR_AMVOFFEN_SHIFT) 554 #define SCR_TWEDEn_BIT (UL(1) << 29) 555 #define SCR_ECVEN_BIT (UL(1) << 28) 556 #define SCR_FGTEN_BIT (UL(1) << 27) 557 #define SCR_ATA_BIT (UL(1) << 26) 558 #define SCR_EnSCXT_BIT (UL(1) << 25) 559 #define SCR_FIEN_BIT (UL(1) << 21) 560 #define SCR_EEL2_BIT (UL(1) << 18) 561 #define SCR_API_BIT (UL(1) << 17) 562 #define SCR_APK_BIT (UL(1) << 16) 563 #define SCR_TERR_BIT (UL(1) << 15) 564 #define SCR_TWE_BIT (UL(1) << 13) 565 #define SCR_TWI_BIT (UL(1) << 12) 566 #define SCR_ST_BIT (UL(1) << 11) 567 #define SCR_RW_BIT (UL(1) << 10) 568 #define SCR_SIF_BIT (UL(1) << 9) 569 #define SCR_HCE_BIT (UL(1) << 8) 570 #define SCR_SMD_BIT (UL(1) << 7) 571 #define SCR_EA_BIT (UL(1) << 3) 572 #define SCR_FIQ_BIT (UL(1) << 2) 573 #define SCR_IRQ_BIT (UL(1) << 1) 574 #define SCR_NS_BIT (UL(1) << 0) 575 #define SCR_VALID_BIT_MASK U(0x24000002F8F) 576 #define SCR_RESET_VAL SCR_RES1_BITS 577 578 /* MDCR_EL3 definitions */ 579 #define MDCR_EnPMSN_BIT (ULL(1) << 36) 580 #define MDCR_MPMX_BIT (ULL(1) << 35) 581 #define MDCR_MCCD_BIT (ULL(1) << 34) 582 #define MDCR_SBRBE_SHIFT U(32) 583 #define MDCR_SBRBE_MASK ULL(0x3) 584 #define MDCR_NSTB(x) ((x) << 24) 585 #define MDCR_NSTB_EL1 ULL(0x3) 586 #define MDCR_NSTBE (ULL(1) << 26) 587 #define MDCR_MTPME_BIT (ULL(1) << 28) 588 #define MDCR_TDCC_BIT (ULL(1) << 27) 589 #define MDCR_SCCD_BIT (ULL(1) << 23) 590 #define MDCR_EPMAD_BIT (ULL(1) << 21) 591 #define MDCR_EDAD_BIT (ULL(1) << 20) 592 #define MDCR_TTRF_BIT (ULL(1) << 19) 593 #define MDCR_STE_BIT (ULL(1) << 18) 594 #define MDCR_SPME_BIT (ULL(1) << 17) 595 #define MDCR_SDD_BIT (ULL(1) << 16) 596 #define MDCR_SPD32(x) ((x) << 14) 597 #define MDCR_SPD32_LEGACY ULL(0x0) 598 #define MDCR_SPD32_DISABLE ULL(0x2) 599 #define MDCR_SPD32_ENABLE ULL(0x3) 600 #define MDCR_NSPB(x) ((x) << 12) 601 #define MDCR_NSPB_EL1 ULL(0x3) 602 #define MDCR_TDOSA_BIT (ULL(1) << 10) 603 #define MDCR_TDA_BIT (ULL(1) << 9) 604 #define MDCR_TPM_BIT (ULL(1) << 6) 605 #define MDCR_EL3_RESET_VAL MDCR_MTPME_BIT 606 607 /* MDCR_EL2 definitions */ 608 #define MDCR_EL2_MTPME (U(1) << 28) 609 #define MDCR_EL2_HLP_BIT (U(1) << 26) 610 #define MDCR_EL2_E2TB(x) ((x) << 24) 611 #define MDCR_EL2_E2TB_EL1 U(0x3) 612 #define MDCR_EL2_HCCD_BIT (U(1) << 23) 613 #define MDCR_EL2_TTRF (U(1) << 19) 614 #define MDCR_EL2_HPMD_BIT (U(1) << 17) 615 #define MDCR_EL2_TPMS (U(1) << 14) 616 #define MDCR_EL2_E2PB(x) ((x) << 12) 617 #define MDCR_EL2_E2PB_EL1 U(0x3) 618 #define MDCR_EL2_TDRA_BIT (U(1) << 11) 619 #define MDCR_EL2_TDOSA_BIT (U(1) << 10) 620 #define MDCR_EL2_TDA_BIT (U(1) << 9) 621 #define MDCR_EL2_TDE_BIT (U(1) << 8) 622 #define MDCR_EL2_HPME_BIT (U(1) << 7) 623 #define MDCR_EL2_TPM_BIT (U(1) << 6) 624 #define MDCR_EL2_TPMCR_BIT (U(1) << 5) 625 #define MDCR_EL2_HPMN_MASK U(0x1f) 626 #define MDCR_EL2_RESET_VAL U(0x0) 627 628 /* HSTR_EL2 definitions */ 629 #define HSTR_EL2_RESET_VAL U(0x0) 630 #define HSTR_EL2_T_MASK U(0xff) 631 632 /* CNTHP_CTL_EL2 definitions */ 633 #define CNTHP_CTL_ENABLE_BIT (U(1) << 0) 634 #define CNTHP_CTL_RESET_VAL U(0x0) 635 636 /* VTTBR_EL2 definitions */ 637 #define VTTBR_RESET_VAL ULL(0x0) 638 #define VTTBR_VMID_MASK ULL(0xff) 639 #define VTTBR_VMID_SHIFT U(48) 640 #define VTTBR_BADDR_MASK ULL(0xffffffffffff) 641 #define VTTBR_BADDR_SHIFT U(0) 642 643 /* HCR definitions */ 644 #define HCR_RESET_VAL ULL(0x0) 645 #define HCR_AMVOFFEN_SHIFT U(51) 646 #define HCR_AMVOFFEN_BIT (ULL(1) << HCR_AMVOFFEN_SHIFT) 647 #define HCR_TEA_BIT (ULL(1) << 47) 648 #define HCR_API_BIT (ULL(1) << 41) 649 #define HCR_APK_BIT (ULL(1) << 40) 650 #define HCR_E2H_BIT (ULL(1) << 34) 651 #define HCR_HCD_BIT (ULL(1) << 29) 652 #define HCR_TGE_BIT (ULL(1) << 27) 653 #define HCR_RW_SHIFT U(31) 654 #define HCR_RW_BIT (ULL(1) << HCR_RW_SHIFT) 655 #define HCR_TWE_BIT (ULL(1) << 14) 656 #define HCR_TWI_BIT (ULL(1) << 13) 657 #define HCR_AMO_BIT (ULL(1) << 5) 658 #define HCR_IMO_BIT (ULL(1) << 4) 659 #define HCR_FMO_BIT (ULL(1) << 3) 660 661 /* ISR definitions */ 662 #define ISR_A_SHIFT U(8) 663 #define ISR_I_SHIFT U(7) 664 #define ISR_F_SHIFT U(6) 665 666 /* CNTHCTL_EL2 definitions */ 667 #define CNTHCTL_RESET_VAL U(0x0) 668 #define EVNTEN_BIT (U(1) << 2) 669 #define EL1PCEN_BIT (U(1) << 1) 670 #define EL1PCTEN_BIT (U(1) << 0) 671 672 /* CNTKCTL_EL1 definitions */ 673 #define EL0PTEN_BIT (U(1) << 9) 674 #define EL0VTEN_BIT (U(1) << 8) 675 #define EL0PCTEN_BIT (U(1) << 0) 676 #define EL0VCTEN_BIT (U(1) << 1) 677 #define EVNTEN_BIT (U(1) << 2) 678 #define EVNTDIR_BIT (U(1) << 3) 679 #define EVNTI_SHIFT U(4) 680 #define EVNTI_MASK U(0xf) 681 682 /* CPTR_EL3 definitions */ 683 #define TCPAC_BIT (U(1) << 31) 684 #define TAM_SHIFT U(30) 685 #define TAM_BIT (U(1) << TAM_SHIFT) 686 #define TTA_BIT (U(1) << 20) 687 #define ESM_BIT (U(1) << 12) 688 #define TFP_BIT (U(1) << 10) 689 #define CPTR_EZ_BIT (U(1) << 8) 690 #define CPTR_EL3_RESET_VAL ((TCPAC_BIT | TAM_BIT | TTA_BIT | TFP_BIT) & \ 691 ~(CPTR_EZ_BIT | ESM_BIT)) 692 693 /* CPTR_EL2 definitions */ 694 #define CPTR_EL2_RES1 ((U(1) << 13) | (U(1) << 12) | (U(0x3ff))) 695 #define CPTR_EL2_TCPAC_BIT (U(1) << 31) 696 #define CPTR_EL2_TAM_SHIFT U(30) 697 #define CPTR_EL2_TAM_BIT (U(1) << CPTR_EL2_TAM_SHIFT) 698 #define CPTR_EL2_SMEN_MASK ULL(0x3) 699 #define CPTR_EL2_SMEN_SHIFT U(24) 700 #define CPTR_EL2_TTA_BIT (U(1) << 20) 701 #define CPTR_EL2_TSM_BIT (U(1) << 12) 702 #define CPTR_EL2_TFP_BIT (U(1) << 10) 703 #define CPTR_EL2_TZ_BIT (U(1) << 8) 704 #define CPTR_EL2_RESET_VAL CPTR_EL2_RES1 705 706 /* VTCR_EL2 definitions */ 707 #define VTCR_RESET_VAL U(0x0) 708 #define VTCR_EL2_MSA (U(1) << 31) 709 710 /* CPSR/SPSR definitions */ 711 #define DAIF_FIQ_BIT (U(1) << 0) 712 #define DAIF_IRQ_BIT (U(1) << 1) 713 #define DAIF_ABT_BIT (U(1) << 2) 714 #define DAIF_DBG_BIT (U(1) << 3) 715 #define SPSR_DAIF_SHIFT U(6) 716 #define SPSR_DAIF_MASK U(0xf) 717 718 #define SPSR_AIF_SHIFT U(6) 719 #define SPSR_AIF_MASK U(0x7) 720 721 #define SPSR_E_SHIFT U(9) 722 #define SPSR_E_MASK U(0x1) 723 #define SPSR_E_LITTLE U(0x0) 724 #define SPSR_E_BIG U(0x1) 725 726 #define SPSR_T_SHIFT U(5) 727 #define SPSR_T_MASK U(0x1) 728 #define SPSR_T_ARM U(0x0) 729 #define SPSR_T_THUMB U(0x1) 730 731 #define SPSR_M_SHIFT U(4) 732 #define SPSR_M_MASK U(0x1) 733 #define SPSR_M_AARCH64 U(0x0) 734 #define SPSR_M_AARCH32 U(0x1) 735 #define SPSR_M_EL2H U(0x9) 736 737 #define SPSR_EL_SHIFT U(2) 738 #define SPSR_EL_WIDTH U(2) 739 740 #define SPSR_SSBS_SHIFT_AARCH64 U(12) 741 #define SPSR_SSBS_BIT_AARCH64 (ULL(1) << SPSR_SSBS_SHIFT_AARCH64) 742 #define SPSR_SSBS_SHIFT_AARCH32 U(23) 743 #define SPSR_SSBS_BIT_AARCH32 (ULL(1) << SPSR_SSBS_SHIFT_AARCH32) 744 745 #define SPSR_PAN_BIT BIT_64(22) 746 747 #define SPSR_DIT_BIT BIT(24) 748 749 #define SPSR_TCO_BIT_AARCH64 BIT_64(25) 750 751 #define DISABLE_ALL_EXCEPTIONS \ 752 (DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT | DAIF_DBG_BIT) 753 754 #define DISABLE_INTERRUPTS (DAIF_FIQ_BIT | DAIF_IRQ_BIT) 755 756 /* 757 * RMR_EL3 definitions 758 */ 759 #define RMR_EL3_RR_BIT (U(1) << 1) 760 #define RMR_EL3_AA64_BIT (U(1) << 0) 761 762 /* 763 * HI-VECTOR address for AArch32 state 764 */ 765 #define HI_VECTOR_BASE U(0xFFFF0000) 766 767 /* 768 * TCR definitions 769 */ 770 #define TCR_EL3_RES1 ((ULL(1) << 31) | (ULL(1) << 23)) 771 #define TCR_EL2_RES1 ((ULL(1) << 31) | (ULL(1) << 23)) 772 #define TCR_EL1_IPS_SHIFT U(32) 773 #define TCR_EL2_PS_SHIFT U(16) 774 #define TCR_EL3_PS_SHIFT U(16) 775 776 #define TCR_TxSZ_MIN ULL(16) 777 #define TCR_TxSZ_MAX ULL(39) 778 #define TCR_TxSZ_MAX_TTST ULL(48) 779 780 #define TCR_T0SZ_SHIFT U(0) 781 #define TCR_T1SZ_SHIFT U(16) 782 783 /* (internal) physical address size bits in EL3/EL1 */ 784 #define TCR_PS_BITS_4GB ULL(0x0) 785 #define TCR_PS_BITS_64GB ULL(0x1) 786 #define TCR_PS_BITS_1TB ULL(0x2) 787 #define TCR_PS_BITS_4TB ULL(0x3) 788 #define TCR_PS_BITS_16TB ULL(0x4) 789 #define TCR_PS_BITS_256TB ULL(0x5) 790 791 #define ADDR_MASK_48_TO_63 ULL(0xFFFF000000000000) 792 #define ADDR_MASK_44_TO_47 ULL(0x0000F00000000000) 793 #define ADDR_MASK_42_TO_43 ULL(0x00000C0000000000) 794 #define ADDR_MASK_40_TO_41 ULL(0x0000030000000000) 795 #define ADDR_MASK_36_TO_39 ULL(0x000000F000000000) 796 #define ADDR_MASK_32_TO_35 ULL(0x0000000F00000000) 797 798 #define TCR_RGN_INNER_NC (ULL(0x0) << 8) 799 #define TCR_RGN_INNER_WBA (ULL(0x1) << 8) 800 #define TCR_RGN_INNER_WT (ULL(0x2) << 8) 801 #define TCR_RGN_INNER_WBNA (ULL(0x3) << 8) 802 803 #define TCR_RGN_OUTER_NC (ULL(0x0) << 10) 804 #define TCR_RGN_OUTER_WBA (ULL(0x1) << 10) 805 #define TCR_RGN_OUTER_WT (ULL(0x2) << 10) 806 #define TCR_RGN_OUTER_WBNA (ULL(0x3) << 10) 807 808 #define TCR_SH_NON_SHAREABLE (ULL(0x0) << 12) 809 #define TCR_SH_OUTER_SHAREABLE (ULL(0x2) << 12) 810 #define TCR_SH_INNER_SHAREABLE (ULL(0x3) << 12) 811 812 #define TCR_RGN1_INNER_NC (ULL(0x0) << 24) 813 #define TCR_RGN1_INNER_WBA (ULL(0x1) << 24) 814 #define TCR_RGN1_INNER_WT (ULL(0x2) << 24) 815 #define TCR_RGN1_INNER_WBNA (ULL(0x3) << 24) 816 817 #define TCR_RGN1_OUTER_NC (ULL(0x0) << 26) 818 #define TCR_RGN1_OUTER_WBA (ULL(0x1) << 26) 819 #define TCR_RGN1_OUTER_WT (ULL(0x2) << 26) 820 #define TCR_RGN1_OUTER_WBNA (ULL(0x3) << 26) 821 822 #define TCR_SH1_NON_SHAREABLE (ULL(0x0) << 28) 823 #define TCR_SH1_OUTER_SHAREABLE (ULL(0x2) << 28) 824 #define TCR_SH1_INNER_SHAREABLE (ULL(0x3) << 28) 825 826 #define TCR_TG0_SHIFT U(14) 827 #define TCR_TG0_MASK ULL(3) 828 #define TCR_TG0_4K (ULL(0) << TCR_TG0_SHIFT) 829 #define TCR_TG0_64K (ULL(1) << TCR_TG0_SHIFT) 830 #define TCR_TG0_16K (ULL(2) << TCR_TG0_SHIFT) 831 832 #define TCR_TG1_SHIFT U(30) 833 #define TCR_TG1_MASK ULL(3) 834 #define TCR_TG1_16K (ULL(1) << TCR_TG1_SHIFT) 835 #define TCR_TG1_4K (ULL(2) << TCR_TG1_SHIFT) 836 #define TCR_TG1_64K (ULL(3) << TCR_TG1_SHIFT) 837 838 #define TCR_EPD0_BIT (ULL(1) << 7) 839 #define TCR_EPD1_BIT (ULL(1) << 23) 840 841 #define MODE_SP_SHIFT U(0x0) 842 #define MODE_SP_MASK U(0x1) 843 #define MODE_SP_EL0 U(0x0) 844 #define MODE_SP_ELX U(0x1) 845 846 #define MODE_RW_SHIFT U(0x4) 847 #define MODE_RW_MASK U(0x1) 848 #define MODE_RW_64 U(0x0) 849 #define MODE_RW_32 U(0x1) 850 851 #define MODE_EL_SHIFT U(0x2) 852 #define MODE_EL_MASK U(0x3) 853 #define MODE_EL_WIDTH U(0x2) 854 #define MODE_EL3 U(0x3) 855 #define MODE_EL2 U(0x2) 856 #define MODE_EL1 U(0x1) 857 #define MODE_EL0 U(0x0) 858 859 #define MODE32_SHIFT U(0) 860 #define MODE32_MASK U(0xf) 861 #define MODE32_usr U(0x0) 862 #define MODE32_fiq U(0x1) 863 #define MODE32_irq U(0x2) 864 #define MODE32_svc U(0x3) 865 #define MODE32_mon U(0x6) 866 #define MODE32_abt U(0x7) 867 #define MODE32_hyp U(0xa) 868 #define MODE32_und U(0xb) 869 #define MODE32_sys U(0xf) 870 871 #define GET_RW(mode) (((mode) >> MODE_RW_SHIFT) & MODE_RW_MASK) 872 #define GET_EL(mode) (((mode) >> MODE_EL_SHIFT) & MODE_EL_MASK) 873 #define GET_SP(mode) (((mode) >> MODE_SP_SHIFT) & MODE_SP_MASK) 874 #define GET_M32(mode) (((mode) >> MODE32_SHIFT) & MODE32_MASK) 875 876 #define SPSR_64(el, sp, daif) \ 877 (((MODE_RW_64 << MODE_RW_SHIFT) | \ 878 (((el) & MODE_EL_MASK) << MODE_EL_SHIFT) | \ 879 (((sp) & MODE_SP_MASK) << MODE_SP_SHIFT) | \ 880 (((daif) & SPSR_DAIF_MASK) << SPSR_DAIF_SHIFT)) & \ 881 (~(SPSR_SSBS_BIT_AARCH64))) 882 883 #define SPSR_MODE32(mode, isa, endian, aif) \ 884 (((MODE_RW_32 << MODE_RW_SHIFT) | \ 885 (((mode) & MODE32_MASK) << MODE32_SHIFT) | \ 886 (((isa) & SPSR_T_MASK) << SPSR_T_SHIFT) | \ 887 (((endian) & SPSR_E_MASK) << SPSR_E_SHIFT) | \ 888 (((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT)) & \ 889 (~(SPSR_SSBS_BIT_AARCH32))) 890 891 /* 892 * TTBR Definitions 893 */ 894 #define TTBR_CNP_BIT ULL(0x1) 895 896 /* 897 * CTR_EL0 definitions 898 */ 899 #define CTR_CWG_SHIFT U(24) 900 #define CTR_CWG_MASK U(0xf) 901 #define CTR_ERG_SHIFT U(20) 902 #define CTR_ERG_MASK U(0xf) 903 #define CTR_DMINLINE_SHIFT U(16) 904 #define CTR_DMINLINE_MASK U(0xf) 905 #define CTR_L1IP_SHIFT U(14) 906 #define CTR_L1IP_MASK U(0x3) 907 #define CTR_IMINLINE_SHIFT U(0) 908 #define CTR_IMINLINE_MASK U(0xf) 909 910 #define MAX_CACHE_LINE_SIZE U(0x800) /* 2KB */ 911 912 /* Physical timer control register bit fields shifts and masks */ 913 #define CNTP_CTL_ENABLE_SHIFT U(0) 914 #define CNTP_CTL_IMASK_SHIFT U(1) 915 #define CNTP_CTL_ISTATUS_SHIFT U(2) 916 917 #define CNTP_CTL_ENABLE_MASK U(1) 918 #define CNTP_CTL_IMASK_MASK U(1) 919 #define CNTP_CTL_ISTATUS_MASK U(1) 920 921 /* Physical timer control macros */ 922 #define CNTP_CTL_ENABLE_BIT (U(1) << CNTP_CTL_ENABLE_SHIFT) 923 #define CNTP_CTL_IMASK_BIT (U(1) << CNTP_CTL_IMASK_SHIFT) 924 925 /* Exception Syndrome register bits and bobs */ 926 #define ESR_EC_SHIFT U(26) 927 #define ESR_EC_MASK U(0x3f) 928 #define ESR_EC_LENGTH U(6) 929 #define ESR_ISS_SHIFT U(0) 930 #define ESR_ISS_LENGTH U(25) 931 #define EC_UNKNOWN U(0x0) 932 #define EC_WFE_WFI U(0x1) 933 #define EC_AARCH32_CP15_MRC_MCR U(0x3) 934 #define EC_AARCH32_CP15_MRRC_MCRR U(0x4) 935 #define EC_AARCH32_CP14_MRC_MCR U(0x5) 936 #define EC_AARCH32_CP14_LDC_STC U(0x6) 937 #define EC_FP_SIMD U(0x7) 938 #define EC_AARCH32_CP10_MRC U(0x8) 939 #define EC_AARCH32_CP14_MRRC_MCRR U(0xc) 940 #define EC_ILLEGAL U(0xe) 941 #define EC_AARCH32_SVC U(0x11) 942 #define EC_AARCH32_HVC U(0x12) 943 #define EC_AARCH32_SMC U(0x13) 944 #define EC_AARCH64_SVC U(0x15) 945 #define EC_AARCH64_HVC U(0x16) 946 #define EC_AARCH64_SMC U(0x17) 947 #define EC_AARCH64_SYS U(0x18) 948 #define EC_IABORT_LOWER_EL U(0x20) 949 #define EC_IABORT_CUR_EL U(0x21) 950 #define EC_PC_ALIGN U(0x22) 951 #define EC_DABORT_LOWER_EL U(0x24) 952 #define EC_DABORT_CUR_EL U(0x25) 953 #define EC_SP_ALIGN U(0x26) 954 #define EC_AARCH32_FP U(0x28) 955 #define EC_AARCH64_FP U(0x2c) 956 #define EC_SERROR U(0x2f) 957 #define EC_BRK U(0x3c) 958 959 /* 960 * External Abort bit in Instruction and Data Aborts synchronous exception 961 * syndromes. 962 */ 963 #define ESR_ISS_EABORT_EA_BIT U(9) 964 965 #define EC_BITS(x) (((x) >> ESR_EC_SHIFT) & ESR_EC_MASK) 966 967 /* Reset bit inside the Reset management register for EL3 (RMR_EL3) */ 968 #define RMR_RESET_REQUEST_SHIFT U(0x1) 969 #define RMR_WARM_RESET_CPU (U(1) << RMR_RESET_REQUEST_SHIFT) 970 971 /******************************************************************************* 972 * Definitions of register offsets, fields and macros for CPU system 973 * instructions. 974 ******************************************************************************/ 975 976 #define TLBI_ADDR_SHIFT U(12) 977 #define TLBI_ADDR_MASK ULL(0x00000FFFFFFFFFFF) 978 #define TLBI_ADDR(x) (((x) >> TLBI_ADDR_SHIFT) & TLBI_ADDR_MASK) 979 980 /******************************************************************************* 981 * Definitions of register offsets and fields in the CNTCTLBase Frame of the 982 * system level implementation of the Generic Timer. 983 ******************************************************************************/ 984 #define CNTCTLBASE_CNTFRQ U(0x0) 985 #define CNTNSAR U(0x4) 986 #define CNTNSAR_NS_SHIFT(x) (x) 987 988 #define CNTACR_BASE(x) (U(0x40) + ((x) << 2)) 989 #define CNTACR_RPCT_SHIFT U(0x0) 990 #define CNTACR_RVCT_SHIFT U(0x1) 991 #define CNTACR_RFRQ_SHIFT U(0x2) 992 #define CNTACR_RVOFF_SHIFT U(0x3) 993 #define CNTACR_RWVT_SHIFT U(0x4) 994 #define CNTACR_RWPT_SHIFT U(0x5) 995 996 /******************************************************************************* 997 * Definitions of register offsets and fields in the CNTBaseN Frame of the 998 * system level implementation of the Generic Timer. 999 ******************************************************************************/ 1000 /* Physical Count register. */ 1001 #define CNTPCT_LO U(0x0) 1002 /* Counter Frequency register. */ 1003 #define CNTBASEN_CNTFRQ U(0x10) 1004 /* Physical Timer CompareValue register. */ 1005 #define CNTP_CVAL_LO U(0x20) 1006 /* Physical Timer Control register. */ 1007 #define CNTP_CTL U(0x2c) 1008 1009 /* PMCR_EL0 definitions */ 1010 #define PMCR_EL0_RESET_VAL U(0x0) 1011 #define PMCR_EL0_N_SHIFT U(11) 1012 #define PMCR_EL0_N_MASK U(0x1f) 1013 #define PMCR_EL0_N_BITS (PMCR_EL0_N_MASK << PMCR_EL0_N_SHIFT) 1014 #define PMCR_EL0_LP_BIT (U(1) << 7) 1015 #define PMCR_EL0_LC_BIT (U(1) << 6) 1016 #define PMCR_EL0_DP_BIT (U(1) << 5) 1017 #define PMCR_EL0_X_BIT (U(1) << 4) 1018 #define PMCR_EL0_D_BIT (U(1) << 3) 1019 #define PMCR_EL0_C_BIT (U(1) << 2) 1020 #define PMCR_EL0_P_BIT (U(1) << 1) 1021 #define PMCR_EL0_E_BIT (U(1) << 0) 1022 1023 /******************************************************************************* 1024 * Definitions for system register interface to SVE 1025 ******************************************************************************/ 1026 #define ZCR_EL3 S3_6_C1_C2_0 1027 #define ZCR_EL2 S3_4_C1_C2_0 1028 1029 /* ZCR_EL3 definitions */ 1030 #define ZCR_EL3_LEN_MASK U(0xf) 1031 1032 /* ZCR_EL2 definitions */ 1033 #define ZCR_EL2_LEN_MASK U(0xf) 1034 1035 /******************************************************************************* 1036 * Definitions for system register interface to SME as needed in EL3 1037 ******************************************************************************/ 1038 #define ID_AA64SMFR0_EL1 S3_0_C0_C4_5 1039 #define SMCR_EL3 S3_6_C1_C2_6 1040 1041 /* ID_AA64SMFR0_EL1 definitions */ 1042 #define ID_AA64SMFR0_EL1_SME_FA64_SHIFT U(63) 1043 #define ID_AA64SMFR0_EL1_SME_FA64_MASK U(0x1) 1044 #define ID_AA64SMFR0_EL1_SME_FA64_SUPPORTED U(0x1) 1045 #define ID_AA64SMFR0_EL1_SME_VER_SHIFT U(55) 1046 #define ID_AA64SMFR0_EL1_SME_VER_MASK ULL(0xf) 1047 #define ID_AA64SMFR0_EL1_SME_INST_SUPPORTED ULL(0x0) 1048 #define ID_AA64SMFR0_EL1_SME2_INST_SUPPORTED ULL(0x1) 1049 1050 /* SMCR_ELx definitions */ 1051 #define SMCR_ELX_LEN_SHIFT U(0) 1052 #define SMCR_ELX_LEN_MAX U(0x1ff) 1053 #define SMCR_ELX_FA64_BIT (U(1) << 31) 1054 #define SMCR_ELX_EZT0_BIT (U(1) << 30) 1055 1056 /******************************************************************************* 1057 * Definitions of MAIR encodings for device and normal memory 1058 ******************************************************************************/ 1059 /* 1060 * MAIR encodings for device memory attributes. 1061 */ 1062 #define MAIR_DEV_nGnRnE ULL(0x0) 1063 #define MAIR_DEV_nGnRE ULL(0x4) 1064 #define MAIR_DEV_nGRE ULL(0x8) 1065 #define MAIR_DEV_GRE ULL(0xc) 1066 1067 /* 1068 * MAIR encodings for normal memory attributes. 1069 * 1070 * Cache Policy 1071 * WT: Write Through 1072 * WB: Write Back 1073 * NC: Non-Cacheable 1074 * 1075 * Transient Hint 1076 * NTR: Non-Transient 1077 * TR: Transient 1078 * 1079 * Allocation Policy 1080 * RA: Read Allocate 1081 * WA: Write Allocate 1082 * RWA: Read and Write Allocate 1083 * NA: No Allocation 1084 */ 1085 #define MAIR_NORM_WT_TR_WA ULL(0x1) 1086 #define MAIR_NORM_WT_TR_RA ULL(0x2) 1087 #define MAIR_NORM_WT_TR_RWA ULL(0x3) 1088 #define MAIR_NORM_NC ULL(0x4) 1089 #define MAIR_NORM_WB_TR_WA ULL(0x5) 1090 #define MAIR_NORM_WB_TR_RA ULL(0x6) 1091 #define MAIR_NORM_WB_TR_RWA ULL(0x7) 1092 #define MAIR_NORM_WT_NTR_NA ULL(0x8) 1093 #define MAIR_NORM_WT_NTR_WA ULL(0x9) 1094 #define MAIR_NORM_WT_NTR_RA ULL(0xa) 1095 #define MAIR_NORM_WT_NTR_RWA ULL(0xb) 1096 #define MAIR_NORM_WB_NTR_NA ULL(0xc) 1097 #define MAIR_NORM_WB_NTR_WA ULL(0xd) 1098 #define MAIR_NORM_WB_NTR_RA ULL(0xe) 1099 #define MAIR_NORM_WB_NTR_RWA ULL(0xf) 1100 1101 #define MAIR_NORM_OUTER_SHIFT U(4) 1102 1103 #define MAKE_MAIR_NORMAL_MEMORY(inner, outer) \ 1104 ((inner) | ((outer) << MAIR_NORM_OUTER_SHIFT)) 1105 1106 /* PAR_EL1 fields */ 1107 #define PAR_F_SHIFT U(0) 1108 #define PAR_F_MASK ULL(0x1) 1109 #define PAR_ADDR_SHIFT U(12) 1110 #define PAR_ADDR_MASK (BIT(40) - ULL(1)) /* 40-bits-wide page address */ 1111 1112 /******************************************************************************* 1113 * Definitions for system register interface to SPE 1114 ******************************************************************************/ 1115 #define PMBLIMITR_EL1 S3_0_C9_C10_0 1116 1117 /******************************************************************************* 1118 * Definitions for system register interface, shifts and masks for MPAM 1119 ******************************************************************************/ 1120 #define MPAMIDR_EL1 S3_0_C10_C4_4 1121 #define MPAM2_EL2 S3_4_C10_C5_0 1122 #define MPAMHCR_EL2 S3_4_C10_C4_0 1123 #define MPAM3_EL3 S3_6_C10_C5_0 1124 1125 #define MPAMIDR_EL1_VPMR_MAX_SHIFT ULL(18) 1126 #define MPAMIDR_EL1_VPMR_MAX_MASK ULL(0x7) 1127 /******************************************************************************* 1128 * Definitions for system register interface to AMU for FEAT_AMUv1 1129 ******************************************************************************/ 1130 #define AMCR_EL0 S3_3_C13_C2_0 1131 #define AMCFGR_EL0 S3_3_C13_C2_1 1132 #define AMCGCR_EL0 S3_3_C13_C2_2 1133 #define AMUSERENR_EL0 S3_3_C13_C2_3 1134 #define AMCNTENCLR0_EL0 S3_3_C13_C2_4 1135 #define AMCNTENSET0_EL0 S3_3_C13_C2_5 1136 #define AMCNTENCLR1_EL0 S3_3_C13_C3_0 1137 #define AMCNTENSET1_EL0 S3_3_C13_C3_1 1138 1139 /* Activity Monitor Group 0 Event Counter Registers */ 1140 #define AMEVCNTR00_EL0 S3_3_C13_C4_0 1141 #define AMEVCNTR01_EL0 S3_3_C13_C4_1 1142 #define AMEVCNTR02_EL0 S3_3_C13_C4_2 1143 #define AMEVCNTR03_EL0 S3_3_C13_C4_3 1144 1145 /* Activity Monitor Group 0 Event Type Registers */ 1146 #define AMEVTYPER00_EL0 S3_3_C13_C6_0 1147 #define AMEVTYPER01_EL0 S3_3_C13_C6_1 1148 #define AMEVTYPER02_EL0 S3_3_C13_C6_2 1149 #define AMEVTYPER03_EL0 S3_3_C13_C6_3 1150 1151 /* Activity Monitor Group 1 Event Counter Registers */ 1152 #define AMEVCNTR10_EL0 S3_3_C13_C12_0 1153 #define AMEVCNTR11_EL0 S3_3_C13_C12_1 1154 #define AMEVCNTR12_EL0 S3_3_C13_C12_2 1155 #define AMEVCNTR13_EL0 S3_3_C13_C12_3 1156 #define AMEVCNTR14_EL0 S3_3_C13_C12_4 1157 #define AMEVCNTR15_EL0 S3_3_C13_C12_5 1158 #define AMEVCNTR16_EL0 S3_3_C13_C12_6 1159 #define AMEVCNTR17_EL0 S3_3_C13_C12_7 1160 #define AMEVCNTR18_EL0 S3_3_C13_C13_0 1161 #define AMEVCNTR19_EL0 S3_3_C13_C13_1 1162 #define AMEVCNTR1A_EL0 S3_3_C13_C13_2 1163 #define AMEVCNTR1B_EL0 S3_3_C13_C13_3 1164 #define AMEVCNTR1C_EL0 S3_3_C13_C13_4 1165 #define AMEVCNTR1D_EL0 S3_3_C13_C13_5 1166 #define AMEVCNTR1E_EL0 S3_3_C13_C13_6 1167 #define AMEVCNTR1F_EL0 S3_3_C13_C13_7 1168 1169 /* Activity Monitor Group 1 Event Type Registers */ 1170 #define AMEVTYPER10_EL0 S3_3_C13_C14_0 1171 #define AMEVTYPER11_EL0 S3_3_C13_C14_1 1172 #define AMEVTYPER12_EL0 S3_3_C13_C14_2 1173 #define AMEVTYPER13_EL0 S3_3_C13_C14_3 1174 #define AMEVTYPER14_EL0 S3_3_C13_C14_4 1175 #define AMEVTYPER15_EL0 S3_3_C13_C14_5 1176 #define AMEVTYPER16_EL0 S3_3_C13_C14_6 1177 #define AMEVTYPER17_EL0 S3_3_C13_C14_7 1178 #define AMEVTYPER18_EL0 S3_3_C13_C15_0 1179 #define AMEVTYPER19_EL0 S3_3_C13_C15_1 1180 #define AMEVTYPER1A_EL0 S3_3_C13_C15_2 1181 #define AMEVTYPER1B_EL0 S3_3_C13_C15_3 1182 #define AMEVTYPER1C_EL0 S3_3_C13_C15_4 1183 #define AMEVTYPER1D_EL0 S3_3_C13_C15_5 1184 #define AMEVTYPER1E_EL0 S3_3_C13_C15_6 1185 #define AMEVTYPER1F_EL0 S3_3_C13_C15_7 1186 1187 /* AMCNTENSET0_EL0 definitions */ 1188 #define AMCNTENSET0_EL0_Pn_SHIFT U(0) 1189 #define AMCNTENSET0_EL0_Pn_MASK ULL(0xffff) 1190 1191 /* AMCNTENSET1_EL0 definitions */ 1192 #define AMCNTENSET1_EL0_Pn_SHIFT U(0) 1193 #define AMCNTENSET1_EL0_Pn_MASK ULL(0xffff) 1194 1195 /* AMCNTENCLR0_EL0 definitions */ 1196 #define AMCNTENCLR0_EL0_Pn_SHIFT U(0) 1197 #define AMCNTENCLR0_EL0_Pn_MASK ULL(0xffff) 1198 1199 /* AMCNTENCLR1_EL0 definitions */ 1200 #define AMCNTENCLR1_EL0_Pn_SHIFT U(0) 1201 #define AMCNTENCLR1_EL0_Pn_MASK ULL(0xffff) 1202 1203 /* AMCFGR_EL0 definitions */ 1204 #define AMCFGR_EL0_NCG_SHIFT U(28) 1205 #define AMCFGR_EL0_NCG_MASK U(0xf) 1206 #define AMCFGR_EL0_N_SHIFT U(0) 1207 #define AMCFGR_EL0_N_MASK U(0xff) 1208 1209 /* AMCGCR_EL0 definitions */ 1210 #define AMCGCR_EL0_CG0NC_SHIFT U(0) 1211 #define AMCGCR_EL0_CG0NC_MASK U(0xff) 1212 #define AMCGCR_EL0_CG1NC_SHIFT U(8) 1213 #define AMCGCR_EL0_CG1NC_MASK U(0xff) 1214 1215 /* MPAM register definitions */ 1216 #define MPAM3_EL3_MPAMEN_BIT (ULL(1) << 63) 1217 #define MPAMHCR_EL2_TRAP_MPAMIDR_EL1 (ULL(1) << 31) 1218 1219 #define MPAM2_EL2_TRAPMPAM0EL1 (ULL(1) << 49) 1220 #define MPAM2_EL2_TRAPMPAM1EL1 (ULL(1) << 48) 1221 1222 #define MPAMIDR_HAS_HCR_BIT (ULL(1) << 17) 1223 1224 /******************************************************************************* 1225 * Definitions for system register interface to AMU for FEAT_AMUv1p1 1226 ******************************************************************************/ 1227 1228 /* Definition for register defining which virtual offsets are implemented. */ 1229 #define AMCG1IDR_EL0 S3_3_C13_C2_6 1230 #define AMCG1IDR_CTR_MASK ULL(0xffff) 1231 #define AMCG1IDR_CTR_SHIFT U(0) 1232 #define AMCG1IDR_VOFF_MASK ULL(0xffff) 1233 #define AMCG1IDR_VOFF_SHIFT U(16) 1234 1235 /* New bit added to AMCR_EL0 */ 1236 #define AMCR_CG1RZ_SHIFT U(17) 1237 #define AMCR_CG1RZ_BIT (ULL(0x1) << AMCR_CG1RZ_SHIFT) 1238 1239 /* 1240 * Definitions for virtual offset registers for architected activity monitor 1241 * event counters. 1242 * AMEVCNTVOFF01_EL2 intentionally left undefined, as it does not exist. 1243 */ 1244 #define AMEVCNTVOFF00_EL2 S3_4_C13_C8_0 1245 #define AMEVCNTVOFF02_EL2 S3_4_C13_C8_2 1246 #define AMEVCNTVOFF03_EL2 S3_4_C13_C8_3 1247 1248 /* 1249 * Definitions for virtual offset registers for auxiliary activity monitor event 1250 * counters. 1251 */ 1252 #define AMEVCNTVOFF10_EL2 S3_4_C13_C10_0 1253 #define AMEVCNTVOFF11_EL2 S3_4_C13_C10_1 1254 #define AMEVCNTVOFF12_EL2 S3_4_C13_C10_2 1255 #define AMEVCNTVOFF13_EL2 S3_4_C13_C10_3 1256 #define AMEVCNTVOFF14_EL2 S3_4_C13_C10_4 1257 #define AMEVCNTVOFF15_EL2 S3_4_C13_C10_5 1258 #define AMEVCNTVOFF16_EL2 S3_4_C13_C10_6 1259 #define AMEVCNTVOFF17_EL2 S3_4_C13_C10_7 1260 #define AMEVCNTVOFF18_EL2 S3_4_C13_C11_0 1261 #define AMEVCNTVOFF19_EL2 S3_4_C13_C11_1 1262 #define AMEVCNTVOFF1A_EL2 S3_4_C13_C11_2 1263 #define AMEVCNTVOFF1B_EL2 S3_4_C13_C11_3 1264 #define AMEVCNTVOFF1C_EL2 S3_4_C13_C11_4 1265 #define AMEVCNTVOFF1D_EL2 S3_4_C13_C11_5 1266 #define AMEVCNTVOFF1E_EL2 S3_4_C13_C11_6 1267 #define AMEVCNTVOFF1F_EL2 S3_4_C13_C11_7 1268 1269 /******************************************************************************* 1270 * Realm management extension register definitions 1271 ******************************************************************************/ 1272 #define GPCCR_EL3 S3_6_C2_C1_6 1273 #define GPTBR_EL3 S3_6_C2_C1_4 1274 1275 #define SCXTNUM_EL2 S3_4_C13_C0_7 1276 1277 /******************************************************************************* 1278 * RAS system registers 1279 ******************************************************************************/ 1280 #define DISR_EL1 S3_0_C12_C1_1 1281 #define DISR_A_BIT U(31) 1282 1283 #define ERRIDR_EL1 S3_0_C5_C3_0 1284 #define ERRIDR_MASK U(0xffff) 1285 1286 #define ERRSELR_EL1 S3_0_C5_C3_1 1287 1288 /* System register access to Standard Error Record registers */ 1289 #define ERXFR_EL1 S3_0_C5_C4_0 1290 #define ERXCTLR_EL1 S3_0_C5_C4_1 1291 #define ERXSTATUS_EL1 S3_0_C5_C4_2 1292 #define ERXADDR_EL1 S3_0_C5_C4_3 1293 #define ERXPFGF_EL1 S3_0_C5_C4_4 1294 #define ERXPFGCTL_EL1 S3_0_C5_C4_5 1295 #define ERXPFGCDN_EL1 S3_0_C5_C4_6 1296 #define ERXMISC0_EL1 S3_0_C5_C5_0 1297 #define ERXMISC1_EL1 S3_0_C5_C5_1 1298 1299 #define ERXCTLR_ED_SHIFT U(0) 1300 #define ERXCTLR_ED_BIT (U(1) << ERXCTLR_ED_SHIFT) 1301 #define ERXCTLR_UE_BIT (U(1) << 4) 1302 1303 #define ERXPFGCTL_UC_BIT (U(1) << 1) 1304 #define ERXPFGCTL_UEU_BIT (U(1) << 2) 1305 #define ERXPFGCTL_CDEN_BIT (U(1) << 31) 1306 1307 /******************************************************************************* 1308 * Armv8.3 Pointer Authentication Registers 1309 ******************************************************************************/ 1310 #define APIAKeyLo_EL1 S3_0_C2_C1_0 1311 #define APIAKeyHi_EL1 S3_0_C2_C1_1 1312 #define APIBKeyLo_EL1 S3_0_C2_C1_2 1313 #define APIBKeyHi_EL1 S3_0_C2_C1_3 1314 #define APDAKeyLo_EL1 S3_0_C2_C2_0 1315 #define APDAKeyHi_EL1 S3_0_C2_C2_1 1316 #define APDBKeyLo_EL1 S3_0_C2_C2_2 1317 #define APDBKeyHi_EL1 S3_0_C2_C2_3 1318 #define APGAKeyLo_EL1 S3_0_C2_C3_0 1319 #define APGAKeyHi_EL1 S3_0_C2_C3_1 1320 1321 /******************************************************************************* 1322 * Armv8.4 Data Independent Timing Registers 1323 ******************************************************************************/ 1324 #define DIT S3_3_C4_C2_5 1325 #define DIT_BIT BIT(24) 1326 1327 /******************************************************************************* 1328 * Armv8.5 - new MSR encoding to directly access PSTATE.SSBS field 1329 ******************************************************************************/ 1330 #define SSBS S3_3_C4_C2_6 1331 1332 /******************************************************************************* 1333 * Armv8.5 - Memory Tagging Extension Registers 1334 ******************************************************************************/ 1335 #define TFSRE0_EL1 S3_0_C5_C6_1 1336 #define TFSR_EL1 S3_0_C5_C6_0 1337 #define RGSR_EL1 S3_0_C1_C0_5 1338 #define GCR_EL1 S3_0_C1_C0_6 1339 1340 /******************************************************************************* 1341 * Armv8.5 - Random Number Generator Registers 1342 ******************************************************************************/ 1343 #define RNDR S3_3_C2_C4_0 1344 #define RNDRRS S3_3_C2_C4_1 1345 1346 /******************************************************************************* 1347 * FEAT_HCX - Extended Hypervisor Configuration Register 1348 ******************************************************************************/ 1349 #define HCRX_EL2 S3_4_C1_C2_2 1350 #define HCRX_EL2_MSCEn_BIT (UL(1) << 11) 1351 #define HCRX_EL2_MCE2_BIT (UL(1) << 10) 1352 #define HCRX_EL2_CMOW_BIT (UL(1) << 9) 1353 #define HCRX_EL2_VFNMI_BIT (UL(1) << 8) 1354 #define HCRX_EL2_VINMI_BIT (UL(1) << 7) 1355 #define HCRX_EL2_TALLINT_BIT (UL(1) << 6) 1356 #define HCRX_EL2_SMPME_BIT (UL(1) << 5) 1357 #define HCRX_EL2_FGTnXS_BIT (UL(1) << 4) 1358 #define HCRX_EL2_FnXS_BIT (UL(1) << 3) 1359 #define HCRX_EL2_EnASR_BIT (UL(1) << 2) 1360 #define HCRX_EL2_EnALS_BIT (UL(1) << 1) 1361 #define HCRX_EL2_EnAS0_BIT (UL(1) << 0) 1362 #define HCRX_EL2_INIT_VAL ULL(0x0) 1363 1364 /******************************************************************************* 1365 * FEAT_TCR2 - Extended Translation Control Register 1366 ******************************************************************************/ 1367 #define TCR2_EL2 S3_4_C2_C0_3 1368 1369 /******************************************************************************* 1370 * Permission indirection and overlay 1371 ******************************************************************************/ 1372 1373 #define PIRE0_EL2 S3_4_C10_C2_2 1374 #define PIR_EL2 S3_4_C10_C2_3 1375 #define POR_EL2 S3_4_C10_C2_4 1376 #define S2PIR_EL2 S3_4_C10_C2_5 1377 1378 /******************************************************************************* 1379 * FEAT_GCS - Guarded Control Stack Registers 1380 ******************************************************************************/ 1381 #define GCSCR_EL2 S3_4_C2_C5_0 1382 #define GCSPR_EL2 S3_4_C2_C5_1 1383 1384 /******************************************************************************* 1385 * Definitions for DynamicIQ Shared Unit registers 1386 ******************************************************************************/ 1387 #define CLUSTERPWRDN_EL1 S3_0_c15_c3_6 1388 1389 /* CLUSTERPWRDN_EL1 register definitions */ 1390 #define DSU_CLUSTER_PWR_OFF 0 1391 #define DSU_CLUSTER_PWR_ON 1 1392 #define DSU_CLUSTER_PWR_MASK U(1) 1393 1394 /******************************************************************************* 1395 * Definitions for CPU Power/Performance Management registers 1396 ******************************************************************************/ 1397 1398 #define CPUPPMCR_EL3 S3_6_C15_C2_0 1399 #define CPUPPMCR_EL3_MPMMPINCTL_SHIFT UINT64_C(0) 1400 #define CPUPPMCR_EL3_MPMMPINCTL_MASK UINT64_C(0x1) 1401 1402 #define CPUMPMMCR_EL3 S3_6_C15_C2_1 1403 #define CPUMPMMCR_EL3_MPMM_EN_SHIFT UINT64_C(0) 1404 #define CPUMPMMCR_EL3_MPMM_EN_MASK UINT64_C(0x1) 1405 1406 /* alternative system register encoding for the "sb" speculation barrier */ 1407 #define SYSREG_SB S0_3_C3_C0_7 1408 1409 #endif /* ARCH_H */ 1410