1 /* 2 * Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2020-2022, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef ARCH_H 9 #define ARCH_H 10 11 #include <lib/utils_def.h> 12 13 /******************************************************************************* 14 * MIDR bit definitions 15 ******************************************************************************/ 16 #define MIDR_IMPL_MASK U(0xff) 17 #define MIDR_IMPL_SHIFT U(0x18) 18 #define MIDR_VAR_SHIFT U(20) 19 #define MIDR_VAR_BITS U(4) 20 #define MIDR_VAR_MASK U(0xf) 21 #define MIDR_REV_SHIFT U(0) 22 #define MIDR_REV_BITS U(4) 23 #define MIDR_REV_MASK U(0xf) 24 #define MIDR_PN_MASK U(0xfff) 25 #define MIDR_PN_SHIFT U(0x4) 26 27 /******************************************************************************* 28 * MPIDR macros 29 ******************************************************************************/ 30 #define MPIDR_MT_MASK (ULL(1) << 24) 31 #define MPIDR_CPU_MASK MPIDR_AFFLVL_MASK 32 #define MPIDR_CLUSTER_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS) 33 #define MPIDR_AFFINITY_BITS U(8) 34 #define MPIDR_AFFLVL_MASK ULL(0xff) 35 #define MPIDR_AFF0_SHIFT U(0) 36 #define MPIDR_AFF1_SHIFT U(8) 37 #define MPIDR_AFF2_SHIFT U(16) 38 #define MPIDR_AFF3_SHIFT U(32) 39 #define MPIDR_AFF_SHIFT(_n) MPIDR_AFF##_n##_SHIFT 40 #define MPIDR_AFFINITY_MASK ULL(0xff00ffffff) 41 #define MPIDR_AFFLVL_SHIFT U(3) 42 #define MPIDR_AFFLVL0 ULL(0x0) 43 #define MPIDR_AFFLVL1 ULL(0x1) 44 #define MPIDR_AFFLVL2 ULL(0x2) 45 #define MPIDR_AFFLVL3 ULL(0x3) 46 #define MPIDR_AFFLVL(_n) MPIDR_AFFLVL##_n 47 #define MPIDR_AFFLVL0_VAL(mpidr) \ 48 (((mpidr) >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK) 49 #define MPIDR_AFFLVL1_VAL(mpidr) \ 50 (((mpidr) >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK) 51 #define MPIDR_AFFLVL2_VAL(mpidr) \ 52 (((mpidr) >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK) 53 #define MPIDR_AFFLVL3_VAL(mpidr) \ 54 (((mpidr) >> MPIDR_AFF3_SHIFT) & MPIDR_AFFLVL_MASK) 55 /* 56 * The MPIDR_MAX_AFFLVL count starts from 0. Take care to 57 * add one while using this macro to define array sizes. 58 * TODO: Support only the first 3 affinity levels for now. 59 */ 60 #define MPIDR_MAX_AFFLVL U(2) 61 62 #define MPID_MASK (MPIDR_MT_MASK | \ 63 (MPIDR_AFFLVL_MASK << MPIDR_AFF3_SHIFT) | \ 64 (MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT) | \ 65 (MPIDR_AFFLVL_MASK << MPIDR_AFF1_SHIFT) | \ 66 (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT)) 67 68 #define MPIDR_AFF_ID(mpid, n) \ 69 (((mpid) >> MPIDR_AFF_SHIFT(n)) & MPIDR_AFFLVL_MASK) 70 71 /* 72 * An invalid MPID. This value can be used by functions that return an MPID to 73 * indicate an error. 74 */ 75 #define INVALID_MPID U(0xFFFFFFFF) 76 77 /******************************************************************************* 78 * Definitions for Exception vector offsets 79 ******************************************************************************/ 80 #define CURRENT_EL_SP0 0x0 81 #define CURRENT_EL_SPX 0x200 82 #define LOWER_EL_AARCH64 0x400 83 #define LOWER_EL_AARCH32 0x600 84 85 #define SYNC_EXCEPTION 0x0 86 #define IRQ_EXCEPTION 0x80 87 #define FIQ_EXCEPTION 0x100 88 #define SERROR_EXCEPTION 0x180 89 90 /******************************************************************************* 91 * Definitions for CPU system register interface to GICv3 92 ******************************************************************************/ 93 #define ICC_IGRPEN1_EL1 S3_0_C12_C12_7 94 #define ICC_SGI1R S3_0_C12_C11_5 95 #define ICC_ASGI1R S3_0_C12_C11_6 96 #define ICC_SRE_EL1 S3_0_C12_C12_5 97 #define ICC_SRE_EL2 S3_4_C12_C9_5 98 #define ICC_SRE_EL3 S3_6_C12_C12_5 99 #define ICC_CTLR_EL1 S3_0_C12_C12_4 100 #define ICC_CTLR_EL3 S3_6_C12_C12_4 101 #define ICC_PMR_EL1 S3_0_C4_C6_0 102 #define ICC_RPR_EL1 S3_0_C12_C11_3 103 #define ICC_IGRPEN1_EL3 S3_6_c12_c12_7 104 #define ICC_IGRPEN0_EL1 S3_0_c12_c12_6 105 #define ICC_HPPIR0_EL1 S3_0_c12_c8_2 106 #define ICC_HPPIR1_EL1 S3_0_c12_c12_2 107 #define ICC_IAR0_EL1 S3_0_c12_c8_0 108 #define ICC_IAR1_EL1 S3_0_c12_c12_0 109 #define ICC_EOIR0_EL1 S3_0_c12_c8_1 110 #define ICC_EOIR1_EL1 S3_0_c12_c12_1 111 #define ICC_SGI0R_EL1 S3_0_c12_c11_7 112 113 /******************************************************************************* 114 * Definitions for EL2 system registers for save/restore routine 115 ******************************************************************************/ 116 #define CNTPOFF_EL2 S3_4_C14_C0_6 117 #define HDFGRTR2_EL2 S3_4_C3_C1_0 118 #define HDFGWTR2_EL2 S3_4_C3_C1_1 119 #define HFGRTR2_EL2 S3_4_C3_C1_2 120 #define HFGWTR2_EL2 S3_4_C3_C1_3 121 #define HDFGRTR_EL2 S3_4_C3_C1_4 122 #define HDFGWTR_EL2 S3_4_C3_C1_5 123 #define HAFGRTR_EL2 S3_4_C3_C1_6 124 #define HFGITR2_EL2 S3_4_C3_C1_7 125 #define HFGITR_EL2 S3_4_C1_C1_6 126 #define HFGRTR_EL2 S3_4_C1_C1_4 127 #define HFGWTR_EL2 S3_4_C1_C1_5 128 #define ICH_HCR_EL2 S3_4_C12_C11_0 129 #define ICH_VMCR_EL2 S3_4_C12_C11_7 130 #define MPAMVPM0_EL2 S3_4_C10_C6_0 131 #define MPAMVPM1_EL2 S3_4_C10_C6_1 132 #define MPAMVPM2_EL2 S3_4_C10_C6_2 133 #define MPAMVPM3_EL2 S3_4_C10_C6_3 134 #define MPAMVPM4_EL2 S3_4_C10_C6_4 135 #define MPAMVPM5_EL2 S3_4_C10_C6_5 136 #define MPAMVPM6_EL2 S3_4_C10_C6_6 137 #define MPAMVPM7_EL2 S3_4_C10_C6_7 138 #define MPAMVPMV_EL2 S3_4_C10_C4_1 139 #define VNCR_EL2 S3_4_C2_C2_0 140 #define PMSCR_EL2 S3_4_C9_C9_0 141 #define TFSR_EL2 S3_4_C5_C6_0 142 #define CONTEXTIDR_EL2 S3_4_C13_C0_1 143 #define TTBR1_EL2 S3_4_C2_C0_1 144 145 /******************************************************************************* 146 * Generic timer memory mapped registers & offsets 147 ******************************************************************************/ 148 #define CNTCR_OFF U(0x000) 149 #define CNTCV_OFF U(0x008) 150 #define CNTFID_OFF U(0x020) 151 152 #define CNTCR_EN (U(1) << 0) 153 #define CNTCR_HDBG (U(1) << 1) 154 #define CNTCR_FCREQ(x) ((x) << 8) 155 156 /******************************************************************************* 157 * System register bit definitions 158 ******************************************************************************/ 159 /* CLIDR definitions */ 160 #define LOUIS_SHIFT U(21) 161 #define LOC_SHIFT U(24) 162 #define CTYPE_SHIFT(n) U(3 * (n - 1)) 163 #define CLIDR_FIELD_WIDTH U(3) 164 165 /* CSSELR definitions */ 166 #define LEVEL_SHIFT U(1) 167 168 /* Data cache set/way op type defines */ 169 #define DCISW U(0x0) 170 #define DCCISW U(0x1) 171 #if ERRATA_A53_827319 172 #define DCCSW DCCISW 173 #else 174 #define DCCSW U(0x2) 175 #endif 176 177 #define ID_REG_FIELD_MASK ULL(0xf) 178 179 /* ID_AA64PFR0_EL1 definitions */ 180 #define ID_AA64PFR0_EL0_SHIFT U(0) 181 #define ID_AA64PFR0_EL1_SHIFT U(4) 182 #define ID_AA64PFR0_EL2_SHIFT U(8) 183 #define ID_AA64PFR0_EL3_SHIFT U(12) 184 185 #define ID_AA64PFR0_AMU_SHIFT U(44) 186 #define ID_AA64PFR0_AMU_MASK ULL(0xf) 187 #define ID_AA64PFR0_AMU_V1 ULL(0x1) 188 #define ID_AA64PFR0_AMU_V1P1 U(0x2) 189 190 #define ID_AA64PFR0_ELX_MASK ULL(0xf) 191 192 #define ID_AA64PFR0_GIC_SHIFT U(24) 193 #define ID_AA64PFR0_GIC_WIDTH U(4) 194 #define ID_AA64PFR0_GIC_MASK ULL(0xf) 195 196 #define ID_AA64PFR0_SVE_SHIFT U(32) 197 #define ID_AA64PFR0_SVE_MASK ULL(0xf) 198 #define ID_AA64PFR0_SVE_LENGTH U(4) 199 #define SVE_IMPLEMENTED ULL(0x1) 200 201 #define ID_AA64PFR0_SEL2_SHIFT U(36) 202 #define ID_AA64PFR0_SEL2_MASK ULL(0xf) 203 204 #define ID_AA64PFR0_MPAM_SHIFT U(40) 205 #define ID_AA64PFR0_MPAM_MASK ULL(0xf) 206 207 #define ID_AA64PFR0_DIT_SHIFT U(48) 208 #define ID_AA64PFR0_DIT_MASK ULL(0xf) 209 #define ID_AA64PFR0_DIT_LENGTH U(4) 210 #define DIT_IMPLEMENTED ULL(1) 211 212 #define ID_AA64PFR0_CSV2_SHIFT U(56) 213 #define ID_AA64PFR0_CSV2_MASK ULL(0xf) 214 #define ID_AA64PFR0_CSV2_LENGTH U(4) 215 #define CSV2_2_IMPLEMENTED ULL(0x2) 216 #define CSV2_3_IMPLEMENTED ULL(0x3) 217 218 #define ID_AA64PFR0_FEAT_RME_SHIFT U(52) 219 #define ID_AA64PFR0_FEAT_RME_MASK ULL(0xf) 220 #define ID_AA64PFR0_FEAT_RME_LENGTH U(4) 221 #define RME_NOT_IMPLEMENTED ULL(0) 222 223 #define ID_AA64PFR0_RAS_SHIFT U(28) 224 #define ID_AA64PFR0_RAS_MASK ULL(0xf) 225 #define ID_AA64PFR0_RAS_LENGTH U(4) 226 227 /* Exception level handling */ 228 #define EL_IMPL_NONE ULL(0) 229 #define EL_IMPL_A64ONLY ULL(1) 230 #define EL_IMPL_A64_A32 ULL(2) 231 232 /* ID_AA64DFR0_EL1.DebugVer definitions */ 233 #define ID_AA64DFR0_DEBUGVER_SHIFT U(0) 234 #define ID_AA64DFR0_DEBUGVER_MASK ULL(0xf) 235 #define DEBUGVER_V8P9_IMPLEMENTED ULL(0xb) 236 237 /* ID_AA64DFR0_EL1.TraceVer definitions */ 238 #define ID_AA64DFR0_TRACEVER_SHIFT U(4) 239 #define ID_AA64DFR0_TRACEVER_MASK ULL(0xf) 240 #define ID_AA64DFR0_TRACEVER_LENGTH U(4) 241 242 #define ID_AA64DFR0_TRACEFILT_SHIFT U(40) 243 #define ID_AA64DFR0_TRACEFILT_MASK U(0xf) 244 #define ID_AA64DFR0_TRACEFILT_LENGTH U(4) 245 #define TRACEFILT_IMPLEMENTED ULL(1) 246 247 #define ID_AA64DFR0_PMUVER_LENGTH U(4) 248 #define ID_AA64DFR0_PMUVER_SHIFT U(8) 249 #define ID_AA64DFR0_PMUVER_MASK U(0xf) 250 #define ID_AA64DFR0_PMUVER_PMUV3 U(1) 251 #define ID_AA64DFR0_PMUVER_PMUV3P8 U(8) 252 #define ID_AA64DFR0_PMUVER_IMP_DEF U(0xf) 253 254 /* ID_AA64DFR0_EL1.SEBEP definitions */ 255 #define ID_AA64DFR0_SEBEP_SHIFT U(24) 256 #define ID_AA64DFR0_SEBEP_MASK ULL(0xf) 257 #define SEBEP_IMPLEMENTED ULL(1) 258 259 /* ID_AA64DFR0_EL1.PMS definitions (for ARMv8.2+) */ 260 #define ID_AA64DFR0_PMS_SHIFT U(32) 261 #define ID_AA64DFR0_PMS_MASK ULL(0xf) 262 #define SPE_IMPLEMENTED ULL(0x1) 263 #define SPE_NOT_IMPLEMENTED ULL(0x0) 264 265 /* ID_AA64DFR0_EL1.TraceBuffer definitions */ 266 #define ID_AA64DFR0_TRACEBUFFER_SHIFT U(44) 267 #define ID_AA64DFR0_TRACEBUFFER_MASK ULL(0xf) 268 #define TRACEBUFFER_IMPLEMENTED ULL(1) 269 270 /* ID_AA64DFR0_EL1.MTPMU definitions (for ARMv8.6+) */ 271 #define ID_AA64DFR0_MTPMU_SHIFT U(48) 272 #define ID_AA64DFR0_MTPMU_MASK ULL(0xf) 273 #define MTPMU_IMPLEMENTED ULL(1) 274 #define MTPMU_NOT_IMPLEMENTED ULL(15) 275 276 /* ID_AA64DFR0_EL1.BRBE definitions */ 277 #define ID_AA64DFR0_BRBE_SHIFT U(52) 278 #define ID_AA64DFR0_BRBE_MASK ULL(0xf) 279 #define BRBE_IMPLEMENTED ULL(1) 280 281 /* ID_AA64DFR1_EL1 definitions */ 282 #define ID_AA64DFR1_EBEP_SHIFT U(48) 283 #define ID_AA64DFR1_EBEP_MASK ULL(0xf) 284 #define EBEP_IMPLEMENTED ULL(1) 285 286 /* ID_AA64ISAR0_EL1 definitions */ 287 #define ID_AA64ISAR0_RNDR_SHIFT U(60) 288 #define ID_AA64ISAR0_RNDR_MASK ULL(0xf) 289 290 /* ID_AA64ISAR1_EL1 definitions */ 291 #define ID_AA64ISAR1_EL1 S3_0_C0_C6_1 292 293 #define ID_AA64ISAR1_GPI_SHIFT U(28) 294 #define ID_AA64ISAR1_GPI_MASK ULL(0xf) 295 #define ID_AA64ISAR1_GPA_SHIFT U(24) 296 #define ID_AA64ISAR1_GPA_MASK ULL(0xf) 297 298 #define ID_AA64ISAR1_API_SHIFT U(8) 299 #define ID_AA64ISAR1_API_MASK ULL(0xf) 300 #define ID_AA64ISAR1_APA_SHIFT U(4) 301 #define ID_AA64ISAR1_APA_MASK ULL(0xf) 302 303 #define ID_AA64ISAR1_SB_SHIFT U(36) 304 #define ID_AA64ISAR1_SB_MASK ULL(0xf) 305 #define SB_IMPLEMENTED ULL(0x1) 306 #define SB_NOT_IMPLEMENTED ULL(0x0) 307 308 /* ID_AA64ISAR2_EL1 definitions */ 309 #define ID_AA64ISAR2_EL1 S3_0_C0_C6_2 310 311 /* ID_AA64PFR2_EL1 definitions */ 312 #define ID_AA64PFR2_EL1 S3_0_C0_C4_2 313 314 #define ID_AA64ISAR2_GPA3_SHIFT U(8) 315 #define ID_AA64ISAR2_GPA3_MASK ULL(0xf) 316 317 #define ID_AA64ISAR2_APA3_SHIFT U(12) 318 #define ID_AA64ISAR2_APA3_MASK ULL(0xf) 319 320 /* ID_AA64MMFR0_EL1 definitions */ 321 #define ID_AA64MMFR0_EL1_PARANGE_SHIFT U(0) 322 #define ID_AA64MMFR0_EL1_PARANGE_MASK ULL(0xf) 323 324 #define PARANGE_0000 U(32) 325 #define PARANGE_0001 U(36) 326 #define PARANGE_0010 U(40) 327 #define PARANGE_0011 U(42) 328 #define PARANGE_0100 U(44) 329 #define PARANGE_0101 U(48) 330 #define PARANGE_0110 U(52) 331 332 #define ID_AA64MMFR0_EL1_ECV_SHIFT U(60) 333 #define ID_AA64MMFR0_EL1_ECV_MASK ULL(0xf) 334 #define ID_AA64MMFR0_EL1_ECV_SELF_SYNCH ULL(0x2) 335 #define ECV_IMPLEMENTED ULL(0x1) 336 337 #define ID_AA64MMFR0_EL1_FGT_SHIFT U(56) 338 #define ID_AA64MMFR0_EL1_FGT_MASK ULL(0xf) 339 #define FGT2_IMPLEMENTED ULL(0x2) 340 #define FGT_IMPLEMENTED ULL(0x1) 341 #define FGT_NOT_IMPLEMENTED ULL(0x0) 342 343 #define ID_AA64MMFR0_EL1_TGRAN4_SHIFT U(28) 344 #define ID_AA64MMFR0_EL1_TGRAN4_MASK ULL(0xf) 345 346 #define ID_AA64MMFR0_EL1_TGRAN64_SHIFT U(24) 347 #define ID_AA64MMFR0_EL1_TGRAN64_MASK ULL(0xf) 348 349 #define ID_AA64MMFR0_EL1_TGRAN16_SHIFT U(20) 350 #define ID_AA64MMFR0_EL1_TGRAN16_MASK ULL(0xf) 351 #define TGRAN16_IMPLEMENTED ULL(0x1) 352 353 /* ID_AA64MMFR1_EL1 definitions */ 354 #define ID_AA64MMFR1_EL1_TWED_SHIFT U(32) 355 #define ID_AA64MMFR1_EL1_TWED_MASK ULL(0xf) 356 #define TWED_IMPLEMENTED ULL(0x1) 357 358 #define ID_AA64MMFR1_EL1_PAN_SHIFT U(20) 359 #define ID_AA64MMFR1_EL1_PAN_MASK ULL(0xf) 360 #define PAN_IMPLEMENTED ULL(0x1) 361 #define PAN2_IMPLEMENTED ULL(0x2) 362 #define PAN3_IMPLEMENTED ULL(0x3) 363 364 #define ID_AA64MMFR1_EL1_VHE_SHIFT U(8) 365 #define ID_AA64MMFR1_EL1_VHE_MASK ULL(0xf) 366 367 #define ID_AA64MMFR1_EL1_HCX_SHIFT U(40) 368 #define ID_AA64MMFR1_EL1_HCX_MASK ULL(0xf) 369 #define HCX_IMPLEMENTED ULL(0x1) 370 371 /* ID_AA64MMFR2_EL1 definitions */ 372 #define ID_AA64MMFR2_EL1 S3_0_C0_C7_2 373 374 #define ID_AA64MMFR2_EL1_ST_SHIFT U(28) 375 #define ID_AA64MMFR2_EL1_ST_MASK ULL(0xf) 376 377 #define ID_AA64MMFR2_EL1_CCIDX_SHIFT U(20) 378 #define ID_AA64MMFR2_EL1_CCIDX_MASK ULL(0xf) 379 #define ID_AA64MMFR2_EL1_CCIDX_LENGTH U(4) 380 381 #define ID_AA64MMFR2_EL1_UAO_SHIFT U(4) 382 #define ID_AA64MMFR2_EL1_UAO_MASK ULL(0xf) 383 384 #define ID_AA64MMFR2_EL1_CNP_SHIFT U(0) 385 #define ID_AA64MMFR2_EL1_CNP_MASK ULL(0xf) 386 387 #define ID_AA64MMFR2_EL1_NV_SHIFT U(24) 388 #define ID_AA64MMFR2_EL1_NV_MASK ULL(0xf) 389 #define NV2_IMPLEMENTED ULL(0x2) 390 391 /* ID_AA64MMFR3_EL1 definitions */ 392 #define ID_AA64MMFR3_EL1 S3_0_C0_C7_3 393 394 #define ID_AA64MMFR3_EL1_S2POE_SHIFT U(20) 395 #define ID_AA64MMFR3_EL1_S2POE_MASK ULL(0xf) 396 397 #define ID_AA64MMFR3_EL1_S1POE_SHIFT U(16) 398 #define ID_AA64MMFR3_EL1_S1POE_MASK ULL(0xf) 399 400 #define ID_AA64MMFR3_EL1_S2PIE_SHIFT U(12) 401 #define ID_AA64MMFR3_EL1_S2PIE_MASK ULL(0xf) 402 403 #define ID_AA64MMFR3_EL1_S1PIE_SHIFT U(8) 404 #define ID_AA64MMFR3_EL1_S1PIE_MASK ULL(0xf) 405 406 #define ID_AA64MMFR3_EL1_TCRX_SHIFT U(0) 407 #define ID_AA64MMFR3_EL1_TCRX_MASK ULL(0xf) 408 409 /* ID_AA64PFR1_EL1 definitions */ 410 411 #define ID_AA64PFR1_EL1_BT_SHIFT U(0) 412 #define ID_AA64PFR1_EL1_BT_MASK ULL(0xf) 413 #define BTI_IMPLEMENTED ULL(1) /* The BTI mechanism is implemented */ 414 415 #define ID_AA64PFR1_EL1_SSBS_SHIFT U(4) 416 #define ID_AA64PFR1_EL1_SSBS_MASK ULL(0xf) 417 #define SSBS_NOT_IMPLEMENTED ULL(0) /* No architectural SSBS support */ 418 419 #define ID_AA64PFR1_EL1_MTE_SHIFT U(8) 420 #define ID_AA64PFR1_EL1_MTE_MASK ULL(0xf) 421 422 #define ID_AA64PFR1_EL1_RNDR_TRAP_SHIFT U(28) 423 #define ID_AA64PFR1_EL1_RNDR_TRAP_MASK U(0xf) 424 425 #define ID_AA64PFR1_EL1_NMI_SHIFT U(36) 426 #define ID_AA64PFR1_EL1_NMI_MASK ULL(0xf) 427 #define NMI_IMPLEMENTED ULL(1) 428 429 #define ID_AA64PFR1_EL1_GCS_SHIFT U(44) 430 #define ID_AA64PFR1_EL1_GCS_MASK ULL(0xf) 431 #define GCS_IMPLEMENTED ULL(1) 432 433 #define RNG_TRAP_IMPLEMENTED ULL(0x1) 434 435 /* ID_AA64PFR2_EL1 definitions */ 436 #define ID_AA64PFR2_EL1_MTEPERM_SHIFT U(0) 437 #define ID_AA64PFR2_EL1_MTEPERM_MASK ULL(0xf) 438 439 #define ID_AA64PFR2_EL1_MTESTOREONLY_SHIFT U(4) 440 #define ID_AA64PFR2_EL1_MTESTOREONLY_MASK ULL(0xf) 441 442 #define ID_AA64PFR2_EL1_MTEFAR_SHIFT U(8) 443 #define ID_AA64PFR2_EL1_MTEFAR_MASK ULL(0xf) 444 445 #define VDISR_EL2 S3_4_C12_C1_1 446 #define VSESR_EL2 S3_4_C5_C2_3 447 448 /* Memory Tagging Extension is not implemented */ 449 #define MTE_UNIMPLEMENTED U(0) 450 /* FEAT_MTE: MTE instructions accessible at EL0 are implemented */ 451 #define MTE_IMPLEMENTED_EL0 U(1) 452 /* FEAT_MTE2: Full MTE is implemented */ 453 #define MTE_IMPLEMENTED_ELX U(2) 454 /* 455 * FEAT_MTE3: MTE is implemented with support for 456 * asymmetric Tag Check Fault handling 457 */ 458 #define MTE_IMPLEMENTED_ASY U(3) 459 460 #define ID_AA64PFR1_MPAM_FRAC_SHIFT ULL(16) 461 #define ID_AA64PFR1_MPAM_FRAC_MASK ULL(0xf) 462 463 #define ID_AA64PFR1_EL1_SME_SHIFT U(24) 464 #define ID_AA64PFR1_EL1_SME_MASK ULL(0xf) 465 #define ID_AA64PFR1_EL1_SME_WIDTH U(4) 466 #define SME_IMPLEMENTED ULL(0x1) 467 #define SME2_IMPLEMENTED ULL(0x2) 468 #define SME_NOT_IMPLEMENTED ULL(0x0) 469 470 /* ID_PFR1_EL1 definitions */ 471 #define ID_PFR1_VIRTEXT_SHIFT U(12) 472 #define ID_PFR1_VIRTEXT_MASK U(0xf) 473 #define GET_VIRT_EXT(id) (((id) >> ID_PFR1_VIRTEXT_SHIFT) \ 474 & ID_PFR1_VIRTEXT_MASK) 475 476 /* SCTLR definitions */ 477 #define SCTLR_EL2_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ 478 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \ 479 (U(1) << 11) | (U(1) << 5) | (U(1) << 4)) 480 481 #define SCTLR_EL1_RES1 ((UL(1) << 29) | (UL(1) << 28) | (UL(1) << 23) | \ 482 (UL(1) << 22) | (UL(1) << 20) | (UL(1) << 11)) 483 484 #define SCTLR_AARCH32_EL1_RES1 \ 485 ((U(1) << 23) | (U(1) << 22) | (U(1) << 11) | \ 486 (U(1) << 4) | (U(1) << 3)) 487 488 #define SCTLR_EL3_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ 489 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \ 490 (U(1) << 11) | (U(1) << 5) | (U(1) << 4)) 491 492 #define SCTLR_M_BIT (ULL(1) << 0) 493 #define SCTLR_A_BIT (ULL(1) << 1) 494 #define SCTLR_C_BIT (ULL(1) << 2) 495 #define SCTLR_SA_BIT (ULL(1) << 3) 496 #define SCTLR_SA0_BIT (ULL(1) << 4) 497 #define SCTLR_CP15BEN_BIT (ULL(1) << 5) 498 #define SCTLR_nAA_BIT (ULL(1) << 6) 499 #define SCTLR_ITD_BIT (ULL(1) << 7) 500 #define SCTLR_SED_BIT (ULL(1) << 8) 501 #define SCTLR_UMA_BIT (ULL(1) << 9) 502 #define SCTLR_EnRCTX_BIT (ULL(1) << 10) 503 #define SCTLR_EOS_BIT (ULL(1) << 11) 504 #define SCTLR_I_BIT (ULL(1) << 12) 505 #define SCTLR_EnDB_BIT (ULL(1) << 13) 506 #define SCTLR_DZE_BIT (ULL(1) << 14) 507 #define SCTLR_UCT_BIT (ULL(1) << 15) 508 #define SCTLR_NTWI_BIT (ULL(1) << 16) 509 #define SCTLR_NTWE_BIT (ULL(1) << 18) 510 #define SCTLR_WXN_BIT (ULL(1) << 19) 511 #define SCTLR_TSCXT_BIT (ULL(1) << 20) 512 #define SCTLR_IESB_BIT (ULL(1) << 21) 513 #define SCTLR_EIS_BIT (ULL(1) << 22) 514 #define SCTLR_SPAN_BIT (ULL(1) << 23) 515 #define SCTLR_E0E_BIT (ULL(1) << 24) 516 #define SCTLR_EE_BIT (ULL(1) << 25) 517 #define SCTLR_UCI_BIT (ULL(1) << 26) 518 #define SCTLR_EnDA_BIT (ULL(1) << 27) 519 #define SCTLR_nTLSMD_BIT (ULL(1) << 28) 520 #define SCTLR_LSMAOE_BIT (ULL(1) << 29) 521 #define SCTLR_EnIB_BIT (ULL(1) << 30) 522 #define SCTLR_EnIA_BIT (ULL(1) << 31) 523 #define SCTLR_BT0_BIT (ULL(1) << 35) 524 #define SCTLR_BT1_BIT (ULL(1) << 36) 525 #define SCTLR_BT_BIT (ULL(1) << 36) 526 #define SCTLR_ITFSB_BIT (ULL(1) << 37) 527 #define SCTLR_TCF0_SHIFT U(38) 528 #define SCTLR_TCF0_MASK ULL(3) 529 #define SCTLR_ENTP2_BIT (ULL(1) << 60) 530 #define SCTLR_SPINTMASK_BIT (ULL(1) << 62) 531 532 /* Tag Check Faults in EL0 have no effect on the PE */ 533 #define SCTLR_TCF0_NO_EFFECT U(0) 534 /* Tag Check Faults in EL0 cause a synchronous exception */ 535 #define SCTLR_TCF0_SYNC U(1) 536 /* Tag Check Faults in EL0 are asynchronously accumulated */ 537 #define SCTLR_TCF0_ASYNC U(2) 538 /* 539 * Tag Check Faults in EL0 cause a synchronous exception on reads, 540 * and are asynchronously accumulated on writes 541 */ 542 #define SCTLR_TCF0_SYNCR_ASYNCW U(3) 543 544 #define SCTLR_TCF_SHIFT U(40) 545 #define SCTLR_TCF_MASK ULL(3) 546 547 /* Tag Check Faults in EL1 have no effect on the PE */ 548 #define SCTLR_TCF_NO_EFFECT U(0) 549 /* Tag Check Faults in EL1 cause a synchronous exception */ 550 #define SCTLR_TCF_SYNC U(1) 551 /* Tag Check Faults in EL1 are asynchronously accumulated */ 552 #define SCTLR_TCF_ASYNC U(2) 553 /* 554 * Tag Check Faults in EL1 cause a synchronous exception on reads, 555 * and are asynchronously accumulated on writes 556 */ 557 #define SCTLR_TCF_SYNCR_ASYNCW U(3) 558 559 #define SCTLR_ATA0_BIT (ULL(1) << 42) 560 #define SCTLR_ATA_BIT (ULL(1) << 43) 561 #define SCTLR_DSSBS_SHIFT U(44) 562 #define SCTLR_DSSBS_BIT (ULL(1) << SCTLR_DSSBS_SHIFT) 563 #define SCTLR_TWEDEn_BIT (ULL(1) << 45) 564 #define SCTLR_TWEDEL_SHIFT U(46) 565 #define SCTLR_TWEDEL_MASK ULL(0xf) 566 #define SCTLR_EnASR_BIT (ULL(1) << 54) 567 #define SCTLR_EnAS0_BIT (ULL(1) << 55) 568 #define SCTLR_EnALS_BIT (ULL(1) << 56) 569 #define SCTLR_EPAN_BIT (ULL(1) << 57) 570 #define SCTLR_RESET_VAL SCTLR_EL3_RES1 571 572 /* CPACR_EL1 definitions */ 573 #define CPACR_EL1_FPEN(x) ((x) << 20) 574 #define CPACR_EL1_FP_TRAP_EL0 UL(0x1) 575 #define CPACR_EL1_FP_TRAP_ALL UL(0x2) 576 #define CPACR_EL1_FP_TRAP_NONE UL(0x3) 577 #define CPACR_EL1_SMEN_SHIFT U(24) 578 #define CPACR_EL1_SMEN_MASK ULL(0x3) 579 580 /* SCR definitions */ 581 #define SCR_RES1_BITS ((U(1) << 4) | (U(1) << 5)) 582 #define SCR_NSE_SHIFT U(62) 583 #define SCR_FGTEN2_BIT (UL(1) << 59) 584 #define SCR_NSE_BIT (ULL(1) << SCR_NSE_SHIFT) 585 #define SCR_GPF_BIT (UL(1) << 48) 586 #define SCR_TWEDEL_SHIFT U(30) 587 #define SCR_TWEDEL_MASK ULL(0xf) 588 #define SCR_PIEN_BIT (UL(1) << 45) 589 #define SCR_TCR2EN_BIT (UL(1) << 43) 590 #define SCR_TRNDR_BIT (UL(1) << 40) 591 #define SCR_GCSEn_BIT (UL(1) << 39) 592 #define SCR_HXEn_BIT (UL(1) << 38) 593 #define SCR_ENTP2_SHIFT U(41) 594 #define SCR_ENTP2_BIT (UL(1) << SCR_ENTP2_SHIFT) 595 #define SCR_AMVOFFEN_SHIFT U(35) 596 #define SCR_AMVOFFEN_BIT (UL(1) << SCR_AMVOFFEN_SHIFT) 597 #define SCR_TWEDEn_BIT (UL(1) << 29) 598 #define SCR_ECVEN_BIT (UL(1) << 28) 599 #define SCR_FGTEN_BIT (UL(1) << 27) 600 #define SCR_ATA_BIT (UL(1) << 26) 601 #define SCR_EnSCXT_BIT (UL(1) << 25) 602 #define SCR_FIEN_BIT (UL(1) << 21) 603 #define SCR_EEL2_BIT (UL(1) << 18) 604 #define SCR_API_BIT (UL(1) << 17) 605 #define SCR_APK_BIT (UL(1) << 16) 606 #define SCR_TERR_BIT (UL(1) << 15) 607 #define SCR_TWE_BIT (UL(1) << 13) 608 #define SCR_TWI_BIT (UL(1) << 12) 609 #define SCR_ST_BIT (UL(1) << 11) 610 #define SCR_RW_BIT (UL(1) << 10) 611 #define SCR_SIF_BIT (UL(1) << 9) 612 #define SCR_HCE_BIT (UL(1) << 8) 613 #define SCR_SMD_BIT (UL(1) << 7) 614 #define SCR_EA_BIT (UL(1) << 3) 615 #define SCR_FIQ_BIT (UL(1) << 2) 616 #define SCR_IRQ_BIT (UL(1) << 1) 617 #define SCR_NS_BIT (UL(1) << 0) 618 #define SCR_VALID_BIT_MASK U(0x24000002F8F) 619 #define SCR_RESET_VAL SCR_RES1_BITS 620 621 /* MDCR_EL3 definitions */ 622 #define MDCR_EBWE_BIT (ULL(1) << 43) 623 #define MDCR_EnPMSN_BIT (ULL(1) << 36) 624 #define MDCR_MPMX_BIT (ULL(1) << 35) 625 #define MDCR_MCCD_BIT (ULL(1) << 34) 626 #define MDCR_SBRBE_SHIFT U(32) 627 #define MDCR_SBRBE_MASK ULL(0x3) 628 #define MDCR_NSTB(x) ((x) << 24) 629 #define MDCR_NSTB_EL1 ULL(0x3) 630 #define MDCR_NSTBE_BIT (ULL(1) << 26) 631 #define MDCR_MTPME_BIT (ULL(1) << 28) 632 #define MDCR_TDCC_BIT (ULL(1) << 27) 633 #define MDCR_SCCD_BIT (ULL(1) << 23) 634 #define MDCR_EPMAD_BIT (ULL(1) << 21) 635 #define MDCR_EDAD_BIT (ULL(1) << 20) 636 #define MDCR_TTRF_BIT (ULL(1) << 19) 637 #define MDCR_STE_BIT (ULL(1) << 18) 638 #define MDCR_SPME_BIT (ULL(1) << 17) 639 #define MDCR_SDD_BIT (ULL(1) << 16) 640 #define MDCR_SPD32(x) ((x) << 14) 641 #define MDCR_SPD32_LEGACY ULL(0x0) 642 #define MDCR_SPD32_DISABLE ULL(0x2) 643 #define MDCR_SPD32_ENABLE ULL(0x3) 644 #define MDCR_NSPB(x) ((x) << 12) 645 #define MDCR_NSPB_EL1 ULL(0x3) 646 #define MDCR_NSPBE_BIT (ULL(1) << 11) 647 #define MDCR_TDOSA_BIT (ULL(1) << 10) 648 #define MDCR_TDA_BIT (ULL(1) << 9) 649 #define MDCR_TPM_BIT (ULL(1) << 6) 650 #define MDCR_EL3_RESET_VAL MDCR_MTPME_BIT 651 652 /* MDCR_EL2 definitions */ 653 #define MDCR_EL2_MTPME (U(1) << 28) 654 #define MDCR_EL2_HLP_BIT (U(1) << 26) 655 #define MDCR_EL2_E2TB(x) ((x) << 24) 656 #define MDCR_EL2_E2TB_EL1 U(0x3) 657 #define MDCR_EL2_HCCD_BIT (U(1) << 23) 658 #define MDCR_EL2_TTRF (U(1) << 19) 659 #define MDCR_EL2_HPMD_BIT (U(1) << 17) 660 #define MDCR_EL2_TPMS (U(1) << 14) 661 #define MDCR_EL2_E2PB(x) ((x) << 12) 662 #define MDCR_EL2_E2PB_EL1 U(0x3) 663 #define MDCR_EL2_TDRA_BIT (U(1) << 11) 664 #define MDCR_EL2_TDOSA_BIT (U(1) << 10) 665 #define MDCR_EL2_TDA_BIT (U(1) << 9) 666 #define MDCR_EL2_TDE_BIT (U(1) << 8) 667 #define MDCR_EL2_HPME_BIT (U(1) << 7) 668 #define MDCR_EL2_TPM_BIT (U(1) << 6) 669 #define MDCR_EL2_TPMCR_BIT (U(1) << 5) 670 #define MDCR_EL2_HPMN_MASK U(0x1f) 671 #define MDCR_EL2_RESET_VAL U(0x0) 672 673 /* HSTR_EL2 definitions */ 674 #define HSTR_EL2_RESET_VAL U(0x0) 675 #define HSTR_EL2_T_MASK U(0xff) 676 677 /* CNTHP_CTL_EL2 definitions */ 678 #define CNTHP_CTL_ENABLE_BIT (U(1) << 0) 679 #define CNTHP_CTL_RESET_VAL U(0x0) 680 681 /* VTTBR_EL2 definitions */ 682 #define VTTBR_RESET_VAL ULL(0x0) 683 #define VTTBR_VMID_MASK ULL(0xff) 684 #define VTTBR_VMID_SHIFT U(48) 685 #define VTTBR_BADDR_MASK ULL(0xffffffffffff) 686 #define VTTBR_BADDR_SHIFT U(0) 687 688 /* HCR definitions */ 689 #define HCR_RESET_VAL ULL(0x0) 690 #define HCR_AMVOFFEN_SHIFT U(51) 691 #define HCR_AMVOFFEN_BIT (ULL(1) << HCR_AMVOFFEN_SHIFT) 692 #define HCR_TEA_BIT (ULL(1) << 47) 693 #define HCR_API_BIT (ULL(1) << 41) 694 #define HCR_APK_BIT (ULL(1) << 40) 695 #define HCR_E2H_BIT (ULL(1) << 34) 696 #define HCR_HCD_BIT (ULL(1) << 29) 697 #define HCR_TGE_BIT (ULL(1) << 27) 698 #define HCR_RW_SHIFT U(31) 699 #define HCR_RW_BIT (ULL(1) << HCR_RW_SHIFT) 700 #define HCR_TWE_BIT (ULL(1) << 14) 701 #define HCR_TWI_BIT (ULL(1) << 13) 702 #define HCR_AMO_BIT (ULL(1) << 5) 703 #define HCR_IMO_BIT (ULL(1) << 4) 704 #define HCR_FMO_BIT (ULL(1) << 3) 705 706 /* ISR definitions */ 707 #define ISR_A_SHIFT U(8) 708 #define ISR_I_SHIFT U(7) 709 #define ISR_F_SHIFT U(6) 710 711 /* CNTHCTL_EL2 definitions */ 712 #define CNTHCTL_RESET_VAL U(0x0) 713 #define EVNTEN_BIT (U(1) << 2) 714 #define EL1PCEN_BIT (U(1) << 1) 715 #define EL1PCTEN_BIT (U(1) << 0) 716 717 /* CNTKCTL_EL1 definitions */ 718 #define EL0PTEN_BIT (U(1) << 9) 719 #define EL0VTEN_BIT (U(1) << 8) 720 #define EL0PCTEN_BIT (U(1) << 0) 721 #define EL0VCTEN_BIT (U(1) << 1) 722 #define EVNTEN_BIT (U(1) << 2) 723 #define EVNTDIR_BIT (U(1) << 3) 724 #define EVNTI_SHIFT U(4) 725 #define EVNTI_MASK U(0xf) 726 727 /* CPTR_EL3 definitions */ 728 #define TCPAC_BIT (U(1) << 31) 729 #define TAM_SHIFT U(30) 730 #define TAM_BIT (U(1) << TAM_SHIFT) 731 #define TTA_BIT (U(1) << 20) 732 #define ESM_BIT (U(1) << 12) 733 #define TFP_BIT (U(1) << 10) 734 #define CPTR_EZ_BIT (U(1) << 8) 735 #define CPTR_EL3_RESET_VAL ((TCPAC_BIT | TAM_BIT | TTA_BIT | TFP_BIT) & \ 736 ~(CPTR_EZ_BIT | ESM_BIT)) 737 738 /* CPTR_EL2 definitions */ 739 #define CPTR_EL2_RES1 ((U(1) << 13) | (U(1) << 12) | (U(0x3ff))) 740 #define CPTR_EL2_TCPAC_BIT (U(1) << 31) 741 #define CPTR_EL2_TAM_SHIFT U(30) 742 #define CPTR_EL2_TAM_BIT (U(1) << CPTR_EL2_TAM_SHIFT) 743 #define CPTR_EL2_SMEN_MASK ULL(0x3) 744 #define CPTR_EL2_SMEN_SHIFT U(24) 745 #define CPTR_EL2_TTA_BIT (U(1) << 20) 746 #define CPTR_EL2_TSM_BIT (U(1) << 12) 747 #define CPTR_EL2_TFP_BIT (U(1) << 10) 748 #define CPTR_EL2_TZ_BIT (U(1) << 8) 749 #define CPTR_EL2_RESET_VAL CPTR_EL2_RES1 750 751 /* VTCR_EL2 definitions */ 752 #define VTCR_RESET_VAL U(0x0) 753 #define VTCR_EL2_MSA (U(1) << 31) 754 755 /* CPSR/SPSR definitions */ 756 #define DAIF_FIQ_BIT (U(1) << 0) 757 #define DAIF_IRQ_BIT (U(1) << 1) 758 #define DAIF_ABT_BIT (U(1) << 2) 759 #define DAIF_DBG_BIT (U(1) << 3) 760 #define SPSR_V_BIT (U(1) << 28) 761 #define SPSR_C_BIT (U(1) << 29) 762 #define SPSR_Z_BIT (U(1) << 30) 763 #define SPSR_N_BIT (U(1) << 31) 764 #define SPSR_DAIF_SHIFT U(6) 765 #define SPSR_DAIF_MASK U(0xf) 766 767 #define SPSR_AIF_SHIFT U(6) 768 #define SPSR_AIF_MASK U(0x7) 769 770 #define SPSR_E_SHIFT U(9) 771 #define SPSR_E_MASK U(0x1) 772 #define SPSR_E_LITTLE U(0x0) 773 #define SPSR_E_BIG U(0x1) 774 775 #define SPSR_T_SHIFT U(5) 776 #define SPSR_T_MASK U(0x1) 777 #define SPSR_T_ARM U(0x0) 778 #define SPSR_T_THUMB U(0x1) 779 780 #define SPSR_M_SHIFT U(4) 781 #define SPSR_M_MASK U(0x1) 782 #define SPSR_M_AARCH64 U(0x0) 783 #define SPSR_M_AARCH32 U(0x1) 784 #define SPSR_M_EL1H U(0x5) 785 #define SPSR_M_EL2H U(0x9) 786 787 #define SPSR_EL_SHIFT U(2) 788 #define SPSR_EL_WIDTH U(2) 789 790 #define SPSR_BTYPE_SHIFT_AARCH64 U(10) 791 #define SPSR_BTYPE_MASK_AARCH64 U(0x3) 792 #define SPSR_SSBS_SHIFT_AARCH64 U(12) 793 #define SPSR_SSBS_BIT_AARCH64 (ULL(1) << SPSR_SSBS_SHIFT_AARCH64) 794 #define SPSR_SSBS_SHIFT_AARCH32 U(23) 795 #define SPSR_SSBS_BIT_AARCH32 (ULL(1) << SPSR_SSBS_SHIFT_AARCH32) 796 #define SPSR_ALLINT_BIT_AARCH64 BIT_64(13) 797 #define SPSR_IL_BIT BIT_64(20) 798 #define SPSR_SS_BIT BIT_64(21) 799 #define SPSR_PAN_BIT BIT_64(22) 800 #define SPSR_UAO_BIT_AARCH64 BIT_64(23) 801 #define SPSR_DIT_BIT BIT(24) 802 #define SPSR_TCO_BIT_AARCH64 BIT_64(25) 803 #define SPSR_PM_BIT_AARCH64 BIT_64(32) 804 #define SPSR_PPEND_BIT BIT(33) 805 #define SPSR_EXLOCK_BIT_AARCH64 BIT_64(34) 806 #define SPSR_NZCV (SPSR_V_BIT | SPSR_C_BIT | SPSR_Z_BIT | SPSR_N_BIT) 807 808 #define DISABLE_ALL_EXCEPTIONS \ 809 (DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT | DAIF_DBG_BIT) 810 #define DISABLE_INTERRUPTS (DAIF_FIQ_BIT | DAIF_IRQ_BIT) 811 812 /* 813 * RMR_EL3 definitions 814 */ 815 #define RMR_EL3_RR_BIT (U(1) << 1) 816 #define RMR_EL3_AA64_BIT (U(1) << 0) 817 818 /* 819 * HI-VECTOR address for AArch32 state 820 */ 821 #define HI_VECTOR_BASE U(0xFFFF0000) 822 823 /* 824 * TCR definitions 825 */ 826 #define TCR_EL3_RES1 ((ULL(1) << 31) | (ULL(1) << 23)) 827 #define TCR_EL2_RES1 ((ULL(1) << 31) | (ULL(1) << 23)) 828 #define TCR_EL1_IPS_SHIFT U(32) 829 #define TCR_EL2_PS_SHIFT U(16) 830 #define TCR_EL3_PS_SHIFT U(16) 831 832 #define TCR_TxSZ_MIN ULL(16) 833 #define TCR_TxSZ_MAX ULL(39) 834 #define TCR_TxSZ_MAX_TTST ULL(48) 835 836 #define TCR_T0SZ_SHIFT U(0) 837 #define TCR_T1SZ_SHIFT U(16) 838 839 /* (internal) physical address size bits in EL3/EL1 */ 840 #define TCR_PS_BITS_4GB ULL(0x0) 841 #define TCR_PS_BITS_64GB ULL(0x1) 842 #define TCR_PS_BITS_1TB ULL(0x2) 843 #define TCR_PS_BITS_4TB ULL(0x3) 844 #define TCR_PS_BITS_16TB ULL(0x4) 845 #define TCR_PS_BITS_256TB ULL(0x5) 846 847 #define ADDR_MASK_48_TO_63 ULL(0xFFFF000000000000) 848 #define ADDR_MASK_44_TO_47 ULL(0x0000F00000000000) 849 #define ADDR_MASK_42_TO_43 ULL(0x00000C0000000000) 850 #define ADDR_MASK_40_TO_41 ULL(0x0000030000000000) 851 #define ADDR_MASK_36_TO_39 ULL(0x000000F000000000) 852 #define ADDR_MASK_32_TO_35 ULL(0x0000000F00000000) 853 854 #define TCR_RGN_INNER_NC (ULL(0x0) << 8) 855 #define TCR_RGN_INNER_WBA (ULL(0x1) << 8) 856 #define TCR_RGN_INNER_WT (ULL(0x2) << 8) 857 #define TCR_RGN_INNER_WBNA (ULL(0x3) << 8) 858 859 #define TCR_RGN_OUTER_NC (ULL(0x0) << 10) 860 #define TCR_RGN_OUTER_WBA (ULL(0x1) << 10) 861 #define TCR_RGN_OUTER_WT (ULL(0x2) << 10) 862 #define TCR_RGN_OUTER_WBNA (ULL(0x3) << 10) 863 864 #define TCR_SH_NON_SHAREABLE (ULL(0x0) << 12) 865 #define TCR_SH_OUTER_SHAREABLE (ULL(0x2) << 12) 866 #define TCR_SH_INNER_SHAREABLE (ULL(0x3) << 12) 867 868 #define TCR_RGN1_INNER_NC (ULL(0x0) << 24) 869 #define TCR_RGN1_INNER_WBA (ULL(0x1) << 24) 870 #define TCR_RGN1_INNER_WT (ULL(0x2) << 24) 871 #define TCR_RGN1_INNER_WBNA (ULL(0x3) << 24) 872 873 #define TCR_RGN1_OUTER_NC (ULL(0x0) << 26) 874 #define TCR_RGN1_OUTER_WBA (ULL(0x1) << 26) 875 #define TCR_RGN1_OUTER_WT (ULL(0x2) << 26) 876 #define TCR_RGN1_OUTER_WBNA (ULL(0x3) << 26) 877 878 #define TCR_SH1_NON_SHAREABLE (ULL(0x0) << 28) 879 #define TCR_SH1_OUTER_SHAREABLE (ULL(0x2) << 28) 880 #define TCR_SH1_INNER_SHAREABLE (ULL(0x3) << 28) 881 882 #define TCR_TG0_SHIFT U(14) 883 #define TCR_TG0_MASK ULL(3) 884 #define TCR_TG0_4K (ULL(0) << TCR_TG0_SHIFT) 885 #define TCR_TG0_64K (ULL(1) << TCR_TG0_SHIFT) 886 #define TCR_TG0_16K (ULL(2) << TCR_TG0_SHIFT) 887 888 #define TCR_TG1_SHIFT U(30) 889 #define TCR_TG1_MASK ULL(3) 890 #define TCR_TG1_16K (ULL(1) << TCR_TG1_SHIFT) 891 #define TCR_TG1_4K (ULL(2) << TCR_TG1_SHIFT) 892 #define TCR_TG1_64K (ULL(3) << TCR_TG1_SHIFT) 893 894 #define TCR_EPD0_BIT (ULL(1) << 7) 895 #define TCR_EPD1_BIT (ULL(1) << 23) 896 897 #define MODE_SP_SHIFT U(0x0) 898 #define MODE_SP_MASK U(0x1) 899 #define MODE_SP_EL0 U(0x0) 900 #define MODE_SP_ELX U(0x1) 901 902 #define MODE_RW_SHIFT U(0x4) 903 #define MODE_RW_MASK U(0x1) 904 #define MODE_RW_64 U(0x0) 905 #define MODE_RW_32 U(0x1) 906 907 #define MODE_EL_SHIFT U(0x2) 908 #define MODE_EL_MASK U(0x3) 909 #define MODE_EL_WIDTH U(0x2) 910 #define MODE_EL3 U(0x3) 911 #define MODE_EL2 U(0x2) 912 #define MODE_EL1 U(0x1) 913 #define MODE_EL0 U(0x0) 914 915 #define MODE32_SHIFT U(0) 916 #define MODE32_MASK U(0xf) 917 #define MODE32_usr U(0x0) 918 #define MODE32_fiq U(0x1) 919 #define MODE32_irq U(0x2) 920 #define MODE32_svc U(0x3) 921 #define MODE32_mon U(0x6) 922 #define MODE32_abt U(0x7) 923 #define MODE32_hyp U(0xa) 924 #define MODE32_und U(0xb) 925 #define MODE32_sys U(0xf) 926 927 #define GET_RW(mode) (((mode) >> MODE_RW_SHIFT) & MODE_RW_MASK) 928 #define GET_EL(mode) (((mode) >> MODE_EL_SHIFT) & MODE_EL_MASK) 929 #define GET_SP(mode) (((mode) >> MODE_SP_SHIFT) & MODE_SP_MASK) 930 #define GET_M32(mode) (((mode) >> MODE32_SHIFT) & MODE32_MASK) 931 932 #define SPSR_64(el, sp, daif) \ 933 (((MODE_RW_64 << MODE_RW_SHIFT) | \ 934 (((el) & MODE_EL_MASK) << MODE_EL_SHIFT) | \ 935 (((sp) & MODE_SP_MASK) << MODE_SP_SHIFT) | \ 936 (((daif) & SPSR_DAIF_MASK) << SPSR_DAIF_SHIFT)) & \ 937 (~(SPSR_SSBS_BIT_AARCH64))) 938 939 #define SPSR_MODE32(mode, isa, endian, aif) \ 940 (((MODE_RW_32 << MODE_RW_SHIFT) | \ 941 (((mode) & MODE32_MASK) << MODE32_SHIFT) | \ 942 (((isa) & SPSR_T_MASK) << SPSR_T_SHIFT) | \ 943 (((endian) & SPSR_E_MASK) << SPSR_E_SHIFT) | \ 944 (((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT)) & \ 945 (~(SPSR_SSBS_BIT_AARCH32))) 946 947 /* 948 * TTBR Definitions 949 */ 950 #define TTBR_CNP_BIT ULL(0x1) 951 952 /* 953 * CTR_EL0 definitions 954 */ 955 #define CTR_CWG_SHIFT U(24) 956 #define CTR_CWG_MASK U(0xf) 957 #define CTR_ERG_SHIFT U(20) 958 #define CTR_ERG_MASK U(0xf) 959 #define CTR_DMINLINE_SHIFT U(16) 960 #define CTR_DMINLINE_MASK U(0xf) 961 #define CTR_L1IP_SHIFT U(14) 962 #define CTR_L1IP_MASK U(0x3) 963 #define CTR_IMINLINE_SHIFT U(0) 964 #define CTR_IMINLINE_MASK U(0xf) 965 966 #define MAX_CACHE_LINE_SIZE U(0x800) /* 2KB */ 967 968 /* Physical timer control register bit fields shifts and masks */ 969 #define CNTP_CTL_ENABLE_SHIFT U(0) 970 #define CNTP_CTL_IMASK_SHIFT U(1) 971 #define CNTP_CTL_ISTATUS_SHIFT U(2) 972 973 #define CNTP_CTL_ENABLE_MASK U(1) 974 #define CNTP_CTL_IMASK_MASK U(1) 975 #define CNTP_CTL_ISTATUS_MASK U(1) 976 977 /* Physical timer control macros */ 978 #define CNTP_CTL_ENABLE_BIT (U(1) << CNTP_CTL_ENABLE_SHIFT) 979 #define CNTP_CTL_IMASK_BIT (U(1) << CNTP_CTL_IMASK_SHIFT) 980 981 /* Exception Syndrome register bits and bobs */ 982 #define ESR_EC_SHIFT U(26) 983 #define ESR_EC_MASK U(0x3f) 984 #define ESR_EC_LENGTH U(6) 985 #define ESR_ISS_SHIFT U(0) 986 #define ESR_ISS_LENGTH U(25) 987 #define ESR_IL_BIT (U(1) << 25) 988 #define EC_UNKNOWN U(0x0) 989 #define EC_WFE_WFI U(0x1) 990 #define EC_AARCH32_CP15_MRC_MCR U(0x3) 991 #define EC_AARCH32_CP15_MRRC_MCRR U(0x4) 992 #define EC_AARCH32_CP14_MRC_MCR U(0x5) 993 #define EC_AARCH32_CP14_LDC_STC U(0x6) 994 #define EC_FP_SIMD U(0x7) 995 #define EC_AARCH32_CP10_MRC U(0x8) 996 #define EC_AARCH32_CP14_MRRC_MCRR U(0xc) 997 #define EC_ILLEGAL U(0xe) 998 #define EC_AARCH32_SVC U(0x11) 999 #define EC_AARCH32_HVC U(0x12) 1000 #define EC_AARCH32_SMC U(0x13) 1001 #define EC_AARCH64_SVC U(0x15) 1002 #define EC_AARCH64_HVC U(0x16) 1003 #define EC_AARCH64_SMC U(0x17) 1004 #define EC_AARCH64_SYS U(0x18) 1005 #define EC_IMP_DEF_EL3 U(0x1f) 1006 #define EC_IABORT_LOWER_EL U(0x20) 1007 #define EC_IABORT_CUR_EL U(0x21) 1008 #define EC_PC_ALIGN U(0x22) 1009 #define EC_DABORT_LOWER_EL U(0x24) 1010 #define EC_DABORT_CUR_EL U(0x25) 1011 #define EC_SP_ALIGN U(0x26) 1012 #define EC_AARCH32_FP U(0x28) 1013 #define EC_AARCH64_FP U(0x2c) 1014 #define EC_SERROR U(0x2f) 1015 #define EC_BRK U(0x3c) 1016 1017 /* 1018 * External Abort bit in Instruction and Data Aborts synchronous exception 1019 * syndromes. 1020 */ 1021 #define ESR_ISS_EABORT_EA_BIT U(9) 1022 1023 #define EC_BITS(x) (((x) >> ESR_EC_SHIFT) & ESR_EC_MASK) 1024 1025 /* Reset bit inside the Reset management register for EL3 (RMR_EL3) */ 1026 #define RMR_RESET_REQUEST_SHIFT U(0x1) 1027 #define RMR_WARM_RESET_CPU (U(1) << RMR_RESET_REQUEST_SHIFT) 1028 1029 /******************************************************************************* 1030 * Definitions of register offsets, fields and macros for CPU system 1031 * instructions. 1032 ******************************************************************************/ 1033 1034 #define TLBI_ADDR_SHIFT U(12) 1035 #define TLBI_ADDR_MASK ULL(0x00000FFFFFFFFFFF) 1036 #define TLBI_ADDR(x) (((x) >> TLBI_ADDR_SHIFT) & TLBI_ADDR_MASK) 1037 1038 /******************************************************************************* 1039 * Definitions of register offsets and fields in the CNTCTLBase Frame of the 1040 * system level implementation of the Generic Timer. 1041 ******************************************************************************/ 1042 #define CNTCTLBASE_CNTFRQ U(0x0) 1043 #define CNTNSAR U(0x4) 1044 #define CNTNSAR_NS_SHIFT(x) (x) 1045 1046 #define CNTACR_BASE(x) (U(0x40) + ((x) << 2)) 1047 #define CNTACR_RPCT_SHIFT U(0x0) 1048 #define CNTACR_RVCT_SHIFT U(0x1) 1049 #define CNTACR_RFRQ_SHIFT U(0x2) 1050 #define CNTACR_RVOFF_SHIFT U(0x3) 1051 #define CNTACR_RWVT_SHIFT U(0x4) 1052 #define CNTACR_RWPT_SHIFT U(0x5) 1053 1054 /******************************************************************************* 1055 * Definitions of register offsets and fields in the CNTBaseN Frame of the 1056 * system level implementation of the Generic Timer. 1057 ******************************************************************************/ 1058 /* Physical Count register. */ 1059 #define CNTPCT_LO U(0x0) 1060 /* Counter Frequency register. */ 1061 #define CNTBASEN_CNTFRQ U(0x10) 1062 /* Physical Timer CompareValue register. */ 1063 #define CNTP_CVAL_LO U(0x20) 1064 /* Physical Timer Control register. */ 1065 #define CNTP_CTL U(0x2c) 1066 1067 /* PMCR_EL0 definitions */ 1068 #define PMCR_EL0_RESET_VAL U(0x0) 1069 #define PMCR_EL0_N_SHIFT U(11) 1070 #define PMCR_EL0_N_MASK U(0x1f) 1071 #define PMCR_EL0_N_BITS (PMCR_EL0_N_MASK << PMCR_EL0_N_SHIFT) 1072 #define PMCR_EL0_LP_BIT (U(1) << 7) 1073 #define PMCR_EL0_LC_BIT (U(1) << 6) 1074 #define PMCR_EL0_DP_BIT (U(1) << 5) 1075 #define PMCR_EL0_X_BIT (U(1) << 4) 1076 #define PMCR_EL0_D_BIT (U(1) << 3) 1077 #define PMCR_EL0_C_BIT (U(1) << 2) 1078 #define PMCR_EL0_P_BIT (U(1) << 1) 1079 #define PMCR_EL0_E_BIT (U(1) << 0) 1080 1081 /******************************************************************************* 1082 * Definitions for system register interface to SVE 1083 ******************************************************************************/ 1084 #define ZCR_EL3 S3_6_C1_C2_0 1085 #define ZCR_EL2 S3_4_C1_C2_0 1086 1087 /* ZCR_EL3 definitions */ 1088 #define ZCR_EL3_LEN_MASK U(0xf) 1089 1090 /* ZCR_EL2 definitions */ 1091 #define ZCR_EL2_LEN_MASK U(0xf) 1092 1093 /******************************************************************************* 1094 * Definitions for system register interface to SME as needed in EL3 1095 ******************************************************************************/ 1096 #define ID_AA64SMFR0_EL1 S3_0_C0_C4_5 1097 #define SMCR_EL3 S3_6_C1_C2_6 1098 1099 /* ID_AA64SMFR0_EL1 definitions */ 1100 #define ID_AA64SMFR0_EL1_SME_FA64_SHIFT U(63) 1101 #define ID_AA64SMFR0_EL1_SME_FA64_MASK U(0x1) 1102 #define SME_FA64_IMPLEMENTED U(0x1) 1103 #define ID_AA64SMFR0_EL1_SME_VER_SHIFT U(55) 1104 #define ID_AA64SMFR0_EL1_SME_VER_MASK ULL(0xf) 1105 #define SME_INST_IMPLEMENTED ULL(0x0) 1106 #define SME2_INST_IMPLEMENTED ULL(0x1) 1107 1108 /* SMCR_ELx definitions */ 1109 #define SMCR_ELX_LEN_SHIFT U(0) 1110 #define SMCR_ELX_LEN_MAX U(0x1ff) 1111 #define SMCR_ELX_FA64_BIT (U(1) << 31) 1112 #define SMCR_ELX_EZT0_BIT (U(1) << 30) 1113 1114 /******************************************************************************* 1115 * Definitions of MAIR encodings for device and normal memory 1116 ******************************************************************************/ 1117 /* 1118 * MAIR encodings for device memory attributes. 1119 */ 1120 #define MAIR_DEV_nGnRnE ULL(0x0) 1121 #define MAIR_DEV_nGnRE ULL(0x4) 1122 #define MAIR_DEV_nGRE ULL(0x8) 1123 #define MAIR_DEV_GRE ULL(0xc) 1124 1125 /* 1126 * MAIR encodings for normal memory attributes. 1127 * 1128 * Cache Policy 1129 * WT: Write Through 1130 * WB: Write Back 1131 * NC: Non-Cacheable 1132 * 1133 * Transient Hint 1134 * NTR: Non-Transient 1135 * TR: Transient 1136 * 1137 * Allocation Policy 1138 * RA: Read Allocate 1139 * WA: Write Allocate 1140 * RWA: Read and Write Allocate 1141 * NA: No Allocation 1142 */ 1143 #define MAIR_NORM_WT_TR_WA ULL(0x1) 1144 #define MAIR_NORM_WT_TR_RA ULL(0x2) 1145 #define MAIR_NORM_WT_TR_RWA ULL(0x3) 1146 #define MAIR_NORM_NC ULL(0x4) 1147 #define MAIR_NORM_WB_TR_WA ULL(0x5) 1148 #define MAIR_NORM_WB_TR_RA ULL(0x6) 1149 #define MAIR_NORM_WB_TR_RWA ULL(0x7) 1150 #define MAIR_NORM_WT_NTR_NA ULL(0x8) 1151 #define MAIR_NORM_WT_NTR_WA ULL(0x9) 1152 #define MAIR_NORM_WT_NTR_RA ULL(0xa) 1153 #define MAIR_NORM_WT_NTR_RWA ULL(0xb) 1154 #define MAIR_NORM_WB_NTR_NA ULL(0xc) 1155 #define MAIR_NORM_WB_NTR_WA ULL(0xd) 1156 #define MAIR_NORM_WB_NTR_RA ULL(0xe) 1157 #define MAIR_NORM_WB_NTR_RWA ULL(0xf) 1158 1159 #define MAIR_NORM_OUTER_SHIFT U(4) 1160 1161 #define MAKE_MAIR_NORMAL_MEMORY(inner, outer) \ 1162 ((inner) | ((outer) << MAIR_NORM_OUTER_SHIFT)) 1163 1164 /* PAR_EL1 fields */ 1165 #define PAR_F_SHIFT U(0) 1166 #define PAR_F_MASK ULL(0x1) 1167 #define PAR_ADDR_SHIFT U(12) 1168 #define PAR_ADDR_MASK (BIT(40) - ULL(1)) /* 40-bits-wide page address */ 1169 1170 /******************************************************************************* 1171 * Definitions for system register interface to SPE 1172 ******************************************************************************/ 1173 #define PMBLIMITR_EL1 S3_0_C9_C10_0 1174 1175 /******************************************************************************* 1176 * Definitions for system register interface, shifts and masks for MPAM 1177 ******************************************************************************/ 1178 #define MPAMIDR_EL1 S3_0_C10_C4_4 1179 #define MPAM2_EL2 S3_4_C10_C5_0 1180 #define MPAMHCR_EL2 S3_4_C10_C4_0 1181 #define MPAM3_EL3 S3_6_C10_C5_0 1182 1183 #define MPAMIDR_EL1_VPMR_MAX_SHIFT ULL(18) 1184 #define MPAMIDR_EL1_VPMR_MAX_MASK ULL(0x7) 1185 /******************************************************************************* 1186 * Definitions for system register interface to AMU for FEAT_AMUv1 1187 ******************************************************************************/ 1188 #define AMCR_EL0 S3_3_C13_C2_0 1189 #define AMCFGR_EL0 S3_3_C13_C2_1 1190 #define AMCGCR_EL0 S3_3_C13_C2_2 1191 #define AMUSERENR_EL0 S3_3_C13_C2_3 1192 #define AMCNTENCLR0_EL0 S3_3_C13_C2_4 1193 #define AMCNTENSET0_EL0 S3_3_C13_C2_5 1194 #define AMCNTENCLR1_EL0 S3_3_C13_C3_0 1195 #define AMCNTENSET1_EL0 S3_3_C13_C3_1 1196 1197 /* Activity Monitor Group 0 Event Counter Registers */ 1198 #define AMEVCNTR00_EL0 S3_3_C13_C4_0 1199 #define AMEVCNTR01_EL0 S3_3_C13_C4_1 1200 #define AMEVCNTR02_EL0 S3_3_C13_C4_2 1201 #define AMEVCNTR03_EL0 S3_3_C13_C4_3 1202 1203 /* Activity Monitor Group 0 Event Type Registers */ 1204 #define AMEVTYPER00_EL0 S3_3_C13_C6_0 1205 #define AMEVTYPER01_EL0 S3_3_C13_C6_1 1206 #define AMEVTYPER02_EL0 S3_3_C13_C6_2 1207 #define AMEVTYPER03_EL0 S3_3_C13_C6_3 1208 1209 /* Activity Monitor Group 1 Event Counter Registers */ 1210 #define AMEVCNTR10_EL0 S3_3_C13_C12_0 1211 #define AMEVCNTR11_EL0 S3_3_C13_C12_1 1212 #define AMEVCNTR12_EL0 S3_3_C13_C12_2 1213 #define AMEVCNTR13_EL0 S3_3_C13_C12_3 1214 #define AMEVCNTR14_EL0 S3_3_C13_C12_4 1215 #define AMEVCNTR15_EL0 S3_3_C13_C12_5 1216 #define AMEVCNTR16_EL0 S3_3_C13_C12_6 1217 #define AMEVCNTR17_EL0 S3_3_C13_C12_7 1218 #define AMEVCNTR18_EL0 S3_3_C13_C13_0 1219 #define AMEVCNTR19_EL0 S3_3_C13_C13_1 1220 #define AMEVCNTR1A_EL0 S3_3_C13_C13_2 1221 #define AMEVCNTR1B_EL0 S3_3_C13_C13_3 1222 #define AMEVCNTR1C_EL0 S3_3_C13_C13_4 1223 #define AMEVCNTR1D_EL0 S3_3_C13_C13_5 1224 #define AMEVCNTR1E_EL0 S3_3_C13_C13_6 1225 #define AMEVCNTR1F_EL0 S3_3_C13_C13_7 1226 1227 /* Activity Monitor Group 1 Event Type Registers */ 1228 #define AMEVTYPER10_EL0 S3_3_C13_C14_0 1229 #define AMEVTYPER11_EL0 S3_3_C13_C14_1 1230 #define AMEVTYPER12_EL0 S3_3_C13_C14_2 1231 #define AMEVTYPER13_EL0 S3_3_C13_C14_3 1232 #define AMEVTYPER14_EL0 S3_3_C13_C14_4 1233 #define AMEVTYPER15_EL0 S3_3_C13_C14_5 1234 #define AMEVTYPER16_EL0 S3_3_C13_C14_6 1235 #define AMEVTYPER17_EL0 S3_3_C13_C14_7 1236 #define AMEVTYPER18_EL0 S3_3_C13_C15_0 1237 #define AMEVTYPER19_EL0 S3_3_C13_C15_1 1238 #define AMEVTYPER1A_EL0 S3_3_C13_C15_2 1239 #define AMEVTYPER1B_EL0 S3_3_C13_C15_3 1240 #define AMEVTYPER1C_EL0 S3_3_C13_C15_4 1241 #define AMEVTYPER1D_EL0 S3_3_C13_C15_5 1242 #define AMEVTYPER1E_EL0 S3_3_C13_C15_6 1243 #define AMEVTYPER1F_EL0 S3_3_C13_C15_7 1244 1245 /* AMCNTENSET0_EL0 definitions */ 1246 #define AMCNTENSET0_EL0_Pn_SHIFT U(0) 1247 #define AMCNTENSET0_EL0_Pn_MASK ULL(0xffff) 1248 1249 /* AMCNTENSET1_EL0 definitions */ 1250 #define AMCNTENSET1_EL0_Pn_SHIFT U(0) 1251 #define AMCNTENSET1_EL0_Pn_MASK ULL(0xffff) 1252 1253 /* AMCNTENCLR0_EL0 definitions */ 1254 #define AMCNTENCLR0_EL0_Pn_SHIFT U(0) 1255 #define AMCNTENCLR0_EL0_Pn_MASK ULL(0xffff) 1256 1257 /* AMCNTENCLR1_EL0 definitions */ 1258 #define AMCNTENCLR1_EL0_Pn_SHIFT U(0) 1259 #define AMCNTENCLR1_EL0_Pn_MASK ULL(0xffff) 1260 1261 /* AMCFGR_EL0 definitions */ 1262 #define AMCFGR_EL0_NCG_SHIFT U(28) 1263 #define AMCFGR_EL0_NCG_MASK U(0xf) 1264 #define AMCFGR_EL0_N_SHIFT U(0) 1265 #define AMCFGR_EL0_N_MASK U(0xff) 1266 1267 /* AMCGCR_EL0 definitions */ 1268 #define AMCGCR_EL0_CG0NC_SHIFT U(0) 1269 #define AMCGCR_EL0_CG0NC_MASK U(0xff) 1270 #define AMCGCR_EL0_CG1NC_SHIFT U(8) 1271 #define AMCGCR_EL0_CG1NC_MASK U(0xff) 1272 1273 /* MPAM register definitions */ 1274 #define MPAM3_EL3_MPAMEN_BIT (ULL(1) << 63) 1275 #define MPAM3_EL3_TRAPLOWER_BIT (ULL(1) << 62) 1276 #define MPAMHCR_EL2_TRAP_MPAMIDR_EL1 (ULL(1) << 31) 1277 #define MPAM3_EL3_RESET_VAL MPAM3_EL3_TRAPLOWER_BIT 1278 1279 #define MPAM2_EL2_TRAPMPAM0EL1 (ULL(1) << 49) 1280 #define MPAM2_EL2_TRAPMPAM1EL1 (ULL(1) << 48) 1281 1282 #define MPAMIDR_HAS_HCR_BIT (ULL(1) << 17) 1283 1284 /******************************************************************************* 1285 * Definitions for system register interface to AMU for FEAT_AMUv1p1 1286 ******************************************************************************/ 1287 1288 /* Definition for register defining which virtual offsets are implemented. */ 1289 #define AMCG1IDR_EL0 S3_3_C13_C2_6 1290 #define AMCG1IDR_CTR_MASK ULL(0xffff) 1291 #define AMCG1IDR_CTR_SHIFT U(0) 1292 #define AMCG1IDR_VOFF_MASK ULL(0xffff) 1293 #define AMCG1IDR_VOFF_SHIFT U(16) 1294 1295 /* New bit added to AMCR_EL0 */ 1296 #define AMCR_CG1RZ_SHIFT U(17) 1297 #define AMCR_CG1RZ_BIT (ULL(0x1) << AMCR_CG1RZ_SHIFT) 1298 1299 /* 1300 * Definitions for virtual offset registers for architected activity monitor 1301 * event counters. 1302 * AMEVCNTVOFF01_EL2 intentionally left undefined, as it does not exist. 1303 */ 1304 #define AMEVCNTVOFF00_EL2 S3_4_C13_C8_0 1305 #define AMEVCNTVOFF02_EL2 S3_4_C13_C8_2 1306 #define AMEVCNTVOFF03_EL2 S3_4_C13_C8_3 1307 1308 /* 1309 * Definitions for virtual offset registers for auxiliary activity monitor event 1310 * counters. 1311 */ 1312 #define AMEVCNTVOFF10_EL2 S3_4_C13_C10_0 1313 #define AMEVCNTVOFF11_EL2 S3_4_C13_C10_1 1314 #define AMEVCNTVOFF12_EL2 S3_4_C13_C10_2 1315 #define AMEVCNTVOFF13_EL2 S3_4_C13_C10_3 1316 #define AMEVCNTVOFF14_EL2 S3_4_C13_C10_4 1317 #define AMEVCNTVOFF15_EL2 S3_4_C13_C10_5 1318 #define AMEVCNTVOFF16_EL2 S3_4_C13_C10_6 1319 #define AMEVCNTVOFF17_EL2 S3_4_C13_C10_7 1320 #define AMEVCNTVOFF18_EL2 S3_4_C13_C11_0 1321 #define AMEVCNTVOFF19_EL2 S3_4_C13_C11_1 1322 #define AMEVCNTVOFF1A_EL2 S3_4_C13_C11_2 1323 #define AMEVCNTVOFF1B_EL2 S3_4_C13_C11_3 1324 #define AMEVCNTVOFF1C_EL2 S3_4_C13_C11_4 1325 #define AMEVCNTVOFF1D_EL2 S3_4_C13_C11_5 1326 #define AMEVCNTVOFF1E_EL2 S3_4_C13_C11_6 1327 #define AMEVCNTVOFF1F_EL2 S3_4_C13_C11_7 1328 1329 /******************************************************************************* 1330 * Realm management extension register definitions 1331 ******************************************************************************/ 1332 #define GPCCR_EL3 S3_6_C2_C1_6 1333 #define GPTBR_EL3 S3_6_C2_C1_4 1334 1335 #define SCXTNUM_EL2 S3_4_C13_C0_7 1336 #define SCXTNUM_EL1 S3_0_C13_C0_7 1337 #define SCXTNUM_EL0 S3_3_C13_C0_7 1338 1339 /******************************************************************************* 1340 * RAS system registers 1341 ******************************************************************************/ 1342 #define DISR_EL1 S3_0_C12_C1_1 1343 #define DISR_A_BIT U(31) 1344 1345 #define ERRIDR_EL1 S3_0_C5_C3_0 1346 #define ERRIDR_MASK U(0xffff) 1347 1348 #define ERRSELR_EL1 S3_0_C5_C3_1 1349 1350 /* System register access to Standard Error Record registers */ 1351 #define ERXFR_EL1 S3_0_C5_C4_0 1352 #define ERXCTLR_EL1 S3_0_C5_C4_1 1353 #define ERXSTATUS_EL1 S3_0_C5_C4_2 1354 #define ERXADDR_EL1 S3_0_C5_C4_3 1355 #define ERXPFGF_EL1 S3_0_C5_C4_4 1356 #define ERXPFGCTL_EL1 S3_0_C5_C4_5 1357 #define ERXPFGCDN_EL1 S3_0_C5_C4_6 1358 #define ERXMISC0_EL1 S3_0_C5_C5_0 1359 #define ERXMISC1_EL1 S3_0_C5_C5_1 1360 1361 #define ERXCTLR_ED_SHIFT U(0) 1362 #define ERXCTLR_ED_BIT (U(1) << ERXCTLR_ED_SHIFT) 1363 #define ERXCTLR_UE_BIT (U(1) << 4) 1364 1365 #define ERXPFGCTL_UC_BIT (U(1) << 1) 1366 #define ERXPFGCTL_UEU_BIT (U(1) << 2) 1367 #define ERXPFGCTL_CDEN_BIT (U(1) << 31) 1368 1369 /******************************************************************************* 1370 * Armv8.3 Pointer Authentication Registers 1371 ******************************************************************************/ 1372 #define APIAKeyLo_EL1 S3_0_C2_C1_0 1373 #define APIAKeyHi_EL1 S3_0_C2_C1_1 1374 #define APIBKeyLo_EL1 S3_0_C2_C1_2 1375 #define APIBKeyHi_EL1 S3_0_C2_C1_3 1376 #define APDAKeyLo_EL1 S3_0_C2_C2_0 1377 #define APDAKeyHi_EL1 S3_0_C2_C2_1 1378 #define APDBKeyLo_EL1 S3_0_C2_C2_2 1379 #define APDBKeyHi_EL1 S3_0_C2_C2_3 1380 #define APGAKeyLo_EL1 S3_0_C2_C3_0 1381 #define APGAKeyHi_EL1 S3_0_C2_C3_1 1382 1383 /******************************************************************************* 1384 * Armv8.4 Data Independent Timing Registers 1385 ******************************************************************************/ 1386 #define DIT S3_3_C4_C2_5 1387 #define DIT_BIT BIT(24) 1388 1389 /******************************************************************************* 1390 * Armv8.5 - new MSR encoding to directly access PSTATE.SSBS field 1391 ******************************************************************************/ 1392 #define SSBS S3_3_C4_C2_6 1393 1394 /******************************************************************************* 1395 * Armv8.5 - Memory Tagging Extension Registers 1396 ******************************************************************************/ 1397 #define TFSRE0_EL1 S3_0_C5_C6_1 1398 #define TFSR_EL1 S3_0_C5_C6_0 1399 #define RGSR_EL1 S3_0_C1_C0_5 1400 #define GCR_EL1 S3_0_C1_C0_6 1401 1402 #define GCR_EL1_RRND_BIT (UL(1) << 16) 1403 1404 /******************************************************************************* 1405 * Armv8.5 - Random Number Generator Registers 1406 ******************************************************************************/ 1407 #define RNDR S3_3_C2_C4_0 1408 #define RNDRRS S3_3_C2_C4_1 1409 1410 /******************************************************************************* 1411 * FEAT_HCX - Extended Hypervisor Configuration Register 1412 ******************************************************************************/ 1413 #define HCRX_EL2 S3_4_C1_C2_2 1414 #define HCRX_EL2_MSCEn_BIT (UL(1) << 11) 1415 #define HCRX_EL2_MCE2_BIT (UL(1) << 10) 1416 #define HCRX_EL2_CMOW_BIT (UL(1) << 9) 1417 #define HCRX_EL2_VFNMI_BIT (UL(1) << 8) 1418 #define HCRX_EL2_VINMI_BIT (UL(1) << 7) 1419 #define HCRX_EL2_TALLINT_BIT (UL(1) << 6) 1420 #define HCRX_EL2_SMPME_BIT (UL(1) << 5) 1421 #define HCRX_EL2_FGTnXS_BIT (UL(1) << 4) 1422 #define HCRX_EL2_FnXS_BIT (UL(1) << 3) 1423 #define HCRX_EL2_EnASR_BIT (UL(1) << 2) 1424 #define HCRX_EL2_EnALS_BIT (UL(1) << 1) 1425 #define HCRX_EL2_EnAS0_BIT (UL(1) << 0) 1426 #define HCRX_EL2_INIT_VAL ULL(0x0) 1427 1428 /******************************************************************************* 1429 * FEAT_FGT - Definitions for Fine-Grained Trap registers 1430 ******************************************************************************/ 1431 #define HFGITR_EL2_INIT_VAL ULL(0x180000000000000) 1432 #define HFGRTR_EL2_INIT_VAL ULL(0xC4000000000000) 1433 #define HFGWTR_EL2_INIT_VAL ULL(0xC4000000000000) 1434 1435 /******************************************************************************* 1436 * FEAT_TCR2 - Extended Translation Control Registers 1437 ******************************************************************************/ 1438 #define TCR2_EL1 S3_0_C2_C0_3 1439 #define TCR2_EL2 S3_4_C2_C0_3 1440 1441 /******************************************************************************* 1442 * Permission indirection and overlay Registers 1443 ******************************************************************************/ 1444 1445 #define PIRE0_EL1 S3_0_C10_C2_2 1446 #define PIRE0_EL2 S3_4_C10_C2_2 1447 #define PIR_EL1 S3_0_C10_C2_3 1448 #define PIR_EL2 S3_4_C10_C2_3 1449 #define POR_EL1 S3_0_C10_C2_4 1450 #define POR_EL2 S3_4_C10_C2_4 1451 #define S2PIR_EL2 S3_4_C10_C2_5 1452 #define S2POR_EL1 S3_0_C10_C2_5 1453 1454 /******************************************************************************* 1455 * FEAT_GCS - Guarded Control Stack Registers 1456 ******************************************************************************/ 1457 #define GCSCR_EL2 S3_4_C2_C5_0 1458 #define GCSPR_EL2 S3_4_C2_C5_1 1459 #define GCSCR_EL1 S3_0_C2_C5_0 1460 #define GCSCRE0_EL1 S3_0_C2_C5_2 1461 #define GCSPR_EL1 S3_0_C2_C5_1 1462 #define GCSPR_EL0 S3_3_C2_C5_1 1463 1464 #define GCSCR_EXLOCK_EN_BIT (UL(1) << 6) 1465 1466 /******************************************************************************* 1467 * FEAT_TRF - Trace Filter Control Registers 1468 ******************************************************************************/ 1469 #define TRFCR_EL2 S3_4_C1_C2_1 1470 #define TRFCR_EL1 S3_0_C1_C2_1 1471 1472 /******************************************************************************* 1473 * Definitions for DynamicIQ Shared Unit registers 1474 ******************************************************************************/ 1475 #define CLUSTERPWRDN_EL1 S3_0_c15_c3_6 1476 1477 /* CLUSTERPWRDN_EL1 register definitions */ 1478 #define DSU_CLUSTER_PWR_OFF 0 1479 #define DSU_CLUSTER_PWR_ON 1 1480 #define DSU_CLUSTER_PWR_MASK U(1) 1481 #define DSU_CLUSTER_MEM_RET BIT(1) 1482 1483 /******************************************************************************* 1484 * Definitions for CPU Power/Performance Management registers 1485 ******************************************************************************/ 1486 1487 #define CPUPPMCR_EL3 S3_6_C15_C2_0 1488 #define CPUPPMCR_EL3_MPMMPINCTL_SHIFT UINT64_C(0) 1489 #define CPUPPMCR_EL3_MPMMPINCTL_MASK UINT64_C(0x1) 1490 1491 #define CPUMPMMCR_EL3 S3_6_C15_C2_1 1492 #define CPUMPMMCR_EL3_MPMM_EN_SHIFT UINT64_C(0) 1493 #define CPUMPMMCR_EL3_MPMM_EN_MASK UINT64_C(0x1) 1494 1495 /* alternative system register encoding for the "sb" speculation barrier */ 1496 #define SYSREG_SB S0_3_C3_C0_7 1497 1498 #define CLUSTERPMCR_EL1 S3_0_C15_C5_0 1499 #define CLUSTERPMCNTENSET_EL1 S3_0_C15_C5_1 1500 #define CLUSTERPMCCNTR_EL1 S3_0_C15_C6_0 1501 #define CLUSTERPMOVSSET_EL1 S3_0_C15_C5_3 1502 #define CLUSTERPMOVSCLR_EL1 S3_0_C15_C5_4 1503 #define CLUSTERPMSELR_EL1 S3_0_C15_C5_5 1504 #define CLUSTERPMXEVTYPER_EL1 S3_0_C15_C6_1 1505 #define CLUSTERPMXEVCNTR_EL1 S3_0_C15_C6_2 1506 1507 #define CLUSTERPMCR_E_BIT BIT(0) 1508 #define CLUSTERPMCR_N_SHIFT U(11) 1509 #define CLUSTERPMCR_N_MASK U(0x1f) 1510 1511 #endif /* ARCH_H */ 1512