1 /* 2 * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef ARCH_H 9 #define ARCH_H 10 11 #include <lib/utils_def.h> 12 13 /******************************************************************************* 14 * MIDR bit definitions 15 ******************************************************************************/ 16 #define MIDR_IMPL_MASK U(0xff) 17 #define MIDR_IMPL_SHIFT U(0x18) 18 #define MIDR_VAR_SHIFT U(20) 19 #define MIDR_VAR_BITS U(4) 20 #define MIDR_VAR_MASK U(0xf) 21 #define MIDR_REV_SHIFT U(0) 22 #define MIDR_REV_BITS U(4) 23 #define MIDR_REV_MASK U(0xf) 24 #define MIDR_PN_MASK U(0xfff) 25 #define MIDR_PN_SHIFT U(0x4) 26 27 /******************************************************************************* 28 * MPIDR macros 29 ******************************************************************************/ 30 #define MPIDR_MT_MASK (ULL(1) << 24) 31 #define MPIDR_CPU_MASK MPIDR_AFFLVL_MASK 32 #define MPIDR_CLUSTER_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS) 33 #define MPIDR_AFFINITY_BITS U(8) 34 #define MPIDR_AFFLVL_MASK ULL(0xff) 35 #define MPIDR_AFF0_SHIFT U(0) 36 #define MPIDR_AFF1_SHIFT U(8) 37 #define MPIDR_AFF2_SHIFT U(16) 38 #define MPIDR_AFF3_SHIFT U(32) 39 #define MPIDR_AFF_SHIFT(_n) MPIDR_AFF##_n##_SHIFT 40 #define MPIDR_AFFINITY_MASK ULL(0xff00ffffff) 41 #define MPIDR_AFFLVL_SHIFT U(3) 42 #define MPIDR_AFFLVL0 ULL(0x0) 43 #define MPIDR_AFFLVL1 ULL(0x1) 44 #define MPIDR_AFFLVL2 ULL(0x2) 45 #define MPIDR_AFFLVL3 ULL(0x3) 46 #define MPIDR_AFFLVL(_n) MPIDR_AFFLVL##_n 47 #define MPIDR_AFFLVL0_VAL(mpidr) \ 48 (((mpidr) >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK) 49 #define MPIDR_AFFLVL1_VAL(mpidr) \ 50 (((mpidr) >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK) 51 #define MPIDR_AFFLVL2_VAL(mpidr) \ 52 (((mpidr) >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK) 53 #define MPIDR_AFFLVL3_VAL(mpidr) \ 54 (((mpidr) >> MPIDR_AFF3_SHIFT) & MPIDR_AFFLVL_MASK) 55 /* 56 * The MPIDR_MAX_AFFLVL count starts from 0. Take care to 57 * add one while using this macro to define array sizes. 58 * TODO: Support only the first 3 affinity levels for now. 59 */ 60 #define MPIDR_MAX_AFFLVL U(2) 61 62 #define MPID_MASK (MPIDR_MT_MASK | \ 63 (MPIDR_AFFLVL_MASK << MPIDR_AFF3_SHIFT) | \ 64 (MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT) | \ 65 (MPIDR_AFFLVL_MASK << MPIDR_AFF1_SHIFT) | \ 66 (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT)) 67 68 #define MPIDR_AFF_ID(mpid, n) \ 69 (((mpid) >> MPIDR_AFF_SHIFT(n)) & MPIDR_AFFLVL_MASK) 70 71 /* 72 * An invalid MPID. This value can be used by functions that return an MPID to 73 * indicate an error. 74 */ 75 #define INVALID_MPID U(0xFFFFFFFF) 76 77 /******************************************************************************* 78 * Definitions for CPU system register interface to GICv3 79 ******************************************************************************/ 80 #define ICC_IGRPEN1_EL1 S3_0_C12_C12_7 81 #define ICC_SGI1R S3_0_C12_C11_5 82 #define ICC_SRE_EL1 S3_0_C12_C12_5 83 #define ICC_SRE_EL2 S3_4_C12_C9_5 84 #define ICC_SRE_EL3 S3_6_C12_C12_5 85 #define ICC_CTLR_EL1 S3_0_C12_C12_4 86 #define ICC_CTLR_EL3 S3_6_C12_C12_4 87 #define ICC_PMR_EL1 S3_0_C4_C6_0 88 #define ICC_RPR_EL1 S3_0_C12_C11_3 89 #define ICC_IGRPEN1_EL3 S3_6_c12_c12_7 90 #define ICC_IGRPEN0_EL1 S3_0_c12_c12_6 91 #define ICC_HPPIR0_EL1 S3_0_c12_c8_2 92 #define ICC_HPPIR1_EL1 S3_0_c12_c12_2 93 #define ICC_IAR0_EL1 S3_0_c12_c8_0 94 #define ICC_IAR1_EL1 S3_0_c12_c12_0 95 #define ICC_EOIR0_EL1 S3_0_c12_c8_1 96 #define ICC_EOIR1_EL1 S3_0_c12_c12_1 97 #define ICC_SGI0R_EL1 S3_0_c12_c11_7 98 99 /******************************************************************************* 100 * Definitions for EL2 system registers for save/restore routine 101 ******************************************************************************/ 102 103 #define CNTPOFF_EL2 S3_4_C14_C0_6 104 #define HAFGRTR_EL2 S3_4_C3_C1_6 105 #define HDFGRTR_EL2 S3_4_C3_C1_4 106 #define HDFGWTR_EL2 S3_4_C3_C1_5 107 #define HFGITR_EL2 S3_4_C1_C1_6 108 #define HFGRTR_EL2 S3_4_C1_C1_4 109 #define HFGWTR_EL2 S3_4_C1_C1_5 110 #define ICH_HCR_EL2 S3_4_C12_C11_0 111 #define ICH_VMCR_EL2 S3_4_C12_C11_7 112 #define MPAMVPM0_EL2 S3_4_C10_C5_0 113 #define MPAMVPM1_EL2 S3_4_C10_C5_1 114 #define MPAMVPM2_EL2 S3_4_C10_C5_2 115 #define MPAMVPM3_EL2 S3_4_C10_C5_3 116 #define MPAMVPM4_EL2 S3_4_C10_C5_4 117 #define MPAMVPM5_EL2 S3_4_C10_C5_5 118 #define MPAMVPM6_EL2 S3_4_C10_C5_6 119 #define MPAMVPM7_EL2 S3_4_C10_C5_7 120 #define MPAMVPMV_EL2 S3_4_C10_C4_1 121 #define TRFCR_EL2 S3_4_C1_C2_1 122 #define PMSCR_EL2 S3_4_C9_C9_0 123 #define TFSR_EL2 S3_4_C5_C6_0 124 125 /******************************************************************************* 126 * Generic timer memory mapped registers & offsets 127 ******************************************************************************/ 128 #define CNTCR_OFF U(0x000) 129 #define CNTCV_OFF U(0x008) 130 #define CNTFID_OFF U(0x020) 131 132 #define CNTCR_EN (U(1) << 0) 133 #define CNTCR_HDBG (U(1) << 1) 134 #define CNTCR_FCREQ(x) ((x) << 8) 135 136 /******************************************************************************* 137 * System register bit definitions 138 ******************************************************************************/ 139 /* CLIDR definitions */ 140 #define LOUIS_SHIFT U(21) 141 #define LOC_SHIFT U(24) 142 #define CTYPE_SHIFT(n) U(3 * (n - 1)) 143 #define CLIDR_FIELD_WIDTH U(3) 144 145 /* CSSELR definitions */ 146 #define LEVEL_SHIFT U(1) 147 148 /* Data cache set/way op type defines */ 149 #define DCISW U(0x0) 150 #define DCCISW U(0x1) 151 #if ERRATA_A53_827319 152 #define DCCSW DCCISW 153 #else 154 #define DCCSW U(0x2) 155 #endif 156 157 /* ID_AA64PFR0_EL1 definitions */ 158 #define ID_AA64PFR0_EL0_SHIFT U(0) 159 #define ID_AA64PFR0_EL1_SHIFT U(4) 160 #define ID_AA64PFR0_EL2_SHIFT U(8) 161 #define ID_AA64PFR0_EL3_SHIFT U(12) 162 #define ID_AA64PFR0_AMU_SHIFT U(44) 163 #define ID_AA64PFR0_AMU_MASK ULL(0xf) 164 #define ID_AA64PFR0_ELX_MASK ULL(0xf) 165 #define ID_AA64PFR0_GIC_SHIFT U(24) 166 #define ID_AA64PFR0_GIC_WIDTH U(4) 167 #define ID_AA64PFR0_GIC_MASK ULL(0xf) 168 #define ID_AA64PFR0_SVE_SHIFT U(32) 169 #define ID_AA64PFR0_SVE_MASK ULL(0xf) 170 #define ID_AA64PFR0_SEL2_SHIFT U(36) 171 #define ID_AA64PFR0_SEL2_MASK ULL(0xf) 172 #define ID_AA64PFR0_MPAM_SHIFT U(40) 173 #define ID_AA64PFR0_MPAM_MASK ULL(0xf) 174 #define ID_AA64PFR0_DIT_SHIFT U(48) 175 #define ID_AA64PFR0_DIT_MASK ULL(0xf) 176 #define ID_AA64PFR0_DIT_LENGTH U(4) 177 #define ID_AA64PFR0_DIT_SUPPORTED U(1) 178 #define ID_AA64PFR0_CSV2_SHIFT U(56) 179 #define ID_AA64PFR0_CSV2_MASK ULL(0xf) 180 #define ID_AA64PFR0_CSV2_LENGTH U(4) 181 182 /* Exception level handling */ 183 #define EL_IMPL_NONE ULL(0) 184 #define EL_IMPL_A64ONLY ULL(1) 185 #define EL_IMPL_A64_A32 ULL(2) 186 187 /* ID_AA64DFR0_EL1.PMS definitions (for ARMv8.2+) */ 188 #define ID_AA64DFR0_PMS_SHIFT U(32) 189 #define ID_AA64DFR0_PMS_MASK ULL(0xf) 190 191 /* ID_AA64ISAR1_EL1 definitions */ 192 #define ID_AA64ISAR1_EL1 S3_0_C0_C6_1 193 #define ID_AA64ISAR1_GPI_SHIFT U(28) 194 #define ID_AA64ISAR1_GPI_MASK ULL(0xf) 195 #define ID_AA64ISAR1_GPA_SHIFT U(24) 196 #define ID_AA64ISAR1_GPA_MASK ULL(0xf) 197 #define ID_AA64ISAR1_API_SHIFT U(8) 198 #define ID_AA64ISAR1_API_MASK ULL(0xf) 199 #define ID_AA64ISAR1_APA_SHIFT U(4) 200 #define ID_AA64ISAR1_APA_MASK ULL(0xf) 201 202 /* ID_AA64MMFR0_EL1 definitions */ 203 #define ID_AA64MMFR0_EL1_PARANGE_SHIFT U(0) 204 #define ID_AA64MMFR0_EL1_PARANGE_MASK ULL(0xf) 205 206 #define PARANGE_0000 U(32) 207 #define PARANGE_0001 U(36) 208 #define PARANGE_0010 U(40) 209 #define PARANGE_0011 U(42) 210 #define PARANGE_0100 U(44) 211 #define PARANGE_0101 U(48) 212 #define PARANGE_0110 U(52) 213 214 #define ID_AA64MMFR0_EL1_ECV_SHIFT U(60) 215 #define ID_AA64MMFR0_EL1_ECV_MASK ULL(0xf) 216 #define ID_AA64MMFR0_EL1_ECV_NOT_SUPPORTED ULL(0x0) 217 #define ID_AA64MMFR0_EL1_ECV_SUPPORTED ULL(0x1) 218 #define ID_AA64MMFR0_EL1_ECV_SELF_SYNCH ULL(0x2) 219 220 #define ID_AA64MMFR0_EL1_FGT_SHIFT U(56) 221 #define ID_AA64MMFR0_EL1_FGT_MASK ULL(0xf) 222 #define ID_AA64MMFR0_EL1_FGT_SUPPORTED ULL(0x1) 223 #define ID_AA64MMFR0_EL1_FGT_NOT_SUPPORTED ULL(0x0) 224 225 #define ID_AA64MMFR0_EL1_TGRAN4_SHIFT U(28) 226 #define ID_AA64MMFR0_EL1_TGRAN4_MASK ULL(0xf) 227 #define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED ULL(0x0) 228 #define ID_AA64MMFR0_EL1_TGRAN4_NOT_SUPPORTED ULL(0xf) 229 230 #define ID_AA64MMFR0_EL1_TGRAN64_SHIFT U(24) 231 #define ID_AA64MMFR0_EL1_TGRAN64_MASK ULL(0xf) 232 #define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED ULL(0x0) 233 #define ID_AA64MMFR0_EL1_TGRAN64_NOT_SUPPORTED ULL(0xf) 234 235 #define ID_AA64MMFR0_EL1_TGRAN16_SHIFT U(20) 236 #define ID_AA64MMFR0_EL1_TGRAN16_MASK ULL(0xf) 237 #define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED ULL(0x1) 238 #define ID_AA64MMFR0_EL1_TGRAN16_NOT_SUPPORTED ULL(0x0) 239 240 /* ID_AA64MMFR1_EL1 definitions */ 241 #define ID_AA64MMFR1_EL1_TWED_SHIFT U(32) 242 #define ID_AA64MMFR1_EL1_TWED_MASK ULL(0xf) 243 #define ID_AA64MMFR1_EL1_TWED_SUPPORTED ULL(0x1) 244 #define ID_AA64MMFR1_EL1_TWED_NOT_SUPPORTED ULL(0x0) 245 246 /* ID_AA64MMFR2_EL1 definitions */ 247 #define ID_AA64MMFR2_EL1 S3_0_C0_C7_2 248 249 #define ID_AA64MMFR2_EL1_ST_SHIFT U(28) 250 #define ID_AA64MMFR2_EL1_ST_MASK ULL(0xf) 251 252 #define ID_AA64MMFR2_EL1_CNP_SHIFT U(0) 253 #define ID_AA64MMFR2_EL1_CNP_MASK ULL(0xf) 254 255 /* ID_AA64PFR1_EL1 definitions */ 256 #define ID_AA64PFR1_EL1_SSBS_SHIFT U(4) 257 #define ID_AA64PFR1_EL1_SSBS_MASK ULL(0xf) 258 259 #define SSBS_UNAVAILABLE ULL(0) /* No architectural SSBS support */ 260 261 #define ID_AA64PFR1_EL1_BT_SHIFT U(0) 262 #define ID_AA64PFR1_EL1_BT_MASK ULL(0xf) 263 264 #define BTI_IMPLEMENTED ULL(1) /* The BTI mechanism is implemented */ 265 266 #define ID_AA64PFR1_EL1_MTE_SHIFT U(8) 267 #define ID_AA64PFR1_EL1_MTE_MASK ULL(0xf) 268 269 #define MTE_UNIMPLEMENTED ULL(0) 270 #define MTE_IMPLEMENTED_EL0 ULL(1) /* MTE is only implemented at EL0 */ 271 #define MTE_IMPLEMENTED_ELX ULL(2) /* MTE is implemented at all ELs */ 272 273 #define ID_AA64PFR1_MPAM_FRAC_SHIFT ULL(16) 274 #define ID_AA64PFR1_MPAM_FRAC_MASK ULL(0xf) 275 276 /* ID_PFR1_EL1 definitions */ 277 #define ID_PFR1_VIRTEXT_SHIFT U(12) 278 #define ID_PFR1_VIRTEXT_MASK U(0xf) 279 #define GET_VIRT_EXT(id) (((id) >> ID_PFR1_VIRTEXT_SHIFT) \ 280 & ID_PFR1_VIRTEXT_MASK) 281 282 /* SCTLR definitions */ 283 #define SCTLR_EL2_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ 284 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \ 285 (U(1) << 11) | (U(1) << 5) | (U(1) << 4)) 286 287 #define SCTLR_EL1_RES1 ((UL(1) << 29) | (UL(1) << 28) | (UL(1) << 23) | \ 288 (UL(1) << 22) | (UL(1) << 20) | (UL(1) << 11)) 289 #define SCTLR_AARCH32_EL1_RES1 \ 290 ((U(1) << 23) | (U(1) << 22) | (U(1) << 11) | \ 291 (U(1) << 4) | (U(1) << 3)) 292 293 #define SCTLR_EL3_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ 294 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \ 295 (U(1) << 11) | (U(1) << 5) | (U(1) << 4)) 296 297 #define SCTLR_M_BIT (ULL(1) << 0) 298 #define SCTLR_A_BIT (ULL(1) << 1) 299 #define SCTLR_C_BIT (ULL(1) << 2) 300 #define SCTLR_SA_BIT (ULL(1) << 3) 301 #define SCTLR_SA0_BIT (ULL(1) << 4) 302 #define SCTLR_CP15BEN_BIT (ULL(1) << 5) 303 #define SCTLR_ITD_BIT (ULL(1) << 7) 304 #define SCTLR_SED_BIT (ULL(1) << 8) 305 #define SCTLR_UMA_BIT (ULL(1) << 9) 306 #define SCTLR_I_BIT (ULL(1) << 12) 307 #define SCTLR_EnDB_BIT (ULL(1) << 13) 308 #define SCTLR_DZE_BIT (ULL(1) << 14) 309 #define SCTLR_UCT_BIT (ULL(1) << 15) 310 #define SCTLR_NTWI_BIT (ULL(1) << 16) 311 #define SCTLR_NTWE_BIT (ULL(1) << 18) 312 #define SCTLR_WXN_BIT (ULL(1) << 19) 313 #define SCTLR_UWXN_BIT (ULL(1) << 20) 314 #define SCTLR_IESB_BIT (ULL(1) << 21) 315 #define SCTLR_E0E_BIT (ULL(1) << 24) 316 #define SCTLR_EE_BIT (ULL(1) << 25) 317 #define SCTLR_UCI_BIT (ULL(1) << 26) 318 #define SCTLR_EnDA_BIT (ULL(1) << 27) 319 #define SCTLR_EnIB_BIT (ULL(1) << 30) 320 #define SCTLR_EnIA_BIT (ULL(1) << 31) 321 #define SCTLR_BT0_BIT (ULL(1) << 35) 322 #define SCTLR_BT1_BIT (ULL(1) << 36) 323 #define SCTLR_BT_BIT (ULL(1) << 36) 324 #define SCTLR_DSSBS_BIT (ULL(1) << 44) 325 #define SCTLR_RESET_VAL SCTLR_EL3_RES1 326 327 /* CPACR_El1 definitions */ 328 #define CPACR_EL1_FPEN(x) ((x) << 20) 329 #define CPACR_EL1_FP_TRAP_EL0 U(0x1) 330 #define CPACR_EL1_FP_TRAP_ALL U(0x2) 331 #define CPACR_EL1_FP_TRAP_NONE U(0x3) 332 333 /* SCR definitions */ 334 #define SCR_RES1_BITS ((U(1) << 4) | (U(1) << 5)) 335 #define SCR_TWEDEL_SHIFT U(30) 336 #define SCR_TWEDEL_MASK ULL(0xf) 337 #define SCR_TWEDEn_BIT (UL(1) << 29) 338 #define SCR_ECVEN_BIT (U(1) << 28) 339 #define SCR_FGTEN_BIT (U(1) << 27) 340 #define SCR_ATA_BIT (U(1) << 26) 341 #define SCR_FIEN_BIT (U(1) << 21) 342 #define SCR_EEL2_BIT (U(1) << 18) 343 #define SCR_API_BIT (U(1) << 17) 344 #define SCR_APK_BIT (U(1) << 16) 345 #define SCR_TERR_BIT (U(1) << 15) 346 #define SCR_TWE_BIT (U(1) << 13) 347 #define SCR_TWI_BIT (U(1) << 12) 348 #define SCR_ST_BIT (U(1) << 11) 349 #define SCR_RW_BIT (U(1) << 10) 350 #define SCR_SIF_BIT (U(1) << 9) 351 #define SCR_HCE_BIT (U(1) << 8) 352 #define SCR_SMD_BIT (U(1) << 7) 353 #define SCR_EA_BIT (U(1) << 3) 354 #define SCR_FIQ_BIT (U(1) << 2) 355 #define SCR_IRQ_BIT (U(1) << 1) 356 #define SCR_NS_BIT (U(1) << 0) 357 #define SCR_VALID_BIT_MASK U(0x2f8f) 358 #define SCR_RESET_VAL SCR_RES1_BITS 359 360 /* MDCR_EL3 definitions */ 361 #define MDCR_SCCD_BIT (ULL(1) << 23) 362 #define MDCR_SPME_BIT (ULL(1) << 17) 363 #define MDCR_SDD_BIT (ULL(1) << 16) 364 #define MDCR_SPD32(x) ((x) << 14) 365 #define MDCR_SPD32_LEGACY ULL(0x0) 366 #define MDCR_SPD32_DISABLE ULL(0x2) 367 #define MDCR_SPD32_ENABLE ULL(0x3) 368 #define MDCR_NSPB(x) ((x) << 12) 369 #define MDCR_NSPB_EL1 ULL(0x3) 370 #define MDCR_TDOSA_BIT (ULL(1) << 10) 371 #define MDCR_TDA_BIT (ULL(1) << 9) 372 #define MDCR_TPM_BIT (ULL(1) << 6) 373 #define MDCR_EL3_RESET_VAL ULL(0x0) 374 375 /* MDCR_EL2 definitions */ 376 #define MDCR_EL2_HLP (U(1) << 26) 377 #define MDCR_EL2_HCCD (U(1) << 23) 378 #define MDCR_EL2_TTRF (U(1) << 19) 379 #define MDCR_EL2_HPMD (U(1) << 17) 380 #define MDCR_EL2_TPMS (U(1) << 14) 381 #define MDCR_EL2_E2PB(x) ((x) << 12) 382 #define MDCR_EL2_E2PB_EL1 U(0x3) 383 #define MDCR_EL2_TDRA_BIT (U(1) << 11) 384 #define MDCR_EL2_TDOSA_BIT (U(1) << 10) 385 #define MDCR_EL2_TDA_BIT (U(1) << 9) 386 #define MDCR_EL2_TDE_BIT (U(1) << 8) 387 #define MDCR_EL2_HPME_BIT (U(1) << 7) 388 #define MDCR_EL2_TPM_BIT (U(1) << 6) 389 #define MDCR_EL2_TPMCR_BIT (U(1) << 5) 390 #define MDCR_EL2_RESET_VAL U(0x0) 391 392 /* HSTR_EL2 definitions */ 393 #define HSTR_EL2_RESET_VAL U(0x0) 394 #define HSTR_EL2_T_MASK U(0xff) 395 396 /* CNTHP_CTL_EL2 definitions */ 397 #define CNTHP_CTL_ENABLE_BIT (U(1) << 0) 398 #define CNTHP_CTL_RESET_VAL U(0x0) 399 400 /* VTTBR_EL2 definitions */ 401 #define VTTBR_RESET_VAL ULL(0x0) 402 #define VTTBR_VMID_MASK ULL(0xff) 403 #define VTTBR_VMID_SHIFT U(48) 404 #define VTTBR_BADDR_MASK ULL(0xffffffffffff) 405 #define VTTBR_BADDR_SHIFT U(0) 406 407 /* HCR definitions */ 408 #define HCR_API_BIT (ULL(1) << 41) 409 #define HCR_APK_BIT (ULL(1) << 40) 410 #define HCR_E2H_BIT (ULL(1) << 34) 411 #define HCR_TGE_BIT (ULL(1) << 27) 412 #define HCR_RW_SHIFT U(31) 413 #define HCR_RW_BIT (ULL(1) << HCR_RW_SHIFT) 414 #define HCR_AMO_BIT (ULL(1) << 5) 415 #define HCR_IMO_BIT (ULL(1) << 4) 416 #define HCR_FMO_BIT (ULL(1) << 3) 417 418 /* ISR definitions */ 419 #define ISR_A_SHIFT U(8) 420 #define ISR_I_SHIFT U(7) 421 #define ISR_F_SHIFT U(6) 422 423 /* CNTHCTL_EL2 definitions */ 424 #define CNTHCTL_RESET_VAL U(0x0) 425 #define EVNTEN_BIT (U(1) << 2) 426 #define EL1PCEN_BIT (U(1) << 1) 427 #define EL1PCTEN_BIT (U(1) << 0) 428 429 /* CNTKCTL_EL1 definitions */ 430 #define EL0PTEN_BIT (U(1) << 9) 431 #define EL0VTEN_BIT (U(1) << 8) 432 #define EL0PCTEN_BIT (U(1) << 0) 433 #define EL0VCTEN_BIT (U(1) << 1) 434 #define EVNTEN_BIT (U(1) << 2) 435 #define EVNTDIR_BIT (U(1) << 3) 436 #define EVNTI_SHIFT U(4) 437 #define EVNTI_MASK U(0xf) 438 439 /* CPTR_EL3 definitions */ 440 #define TCPAC_BIT (U(1) << 31) 441 #define TAM_BIT (U(1) << 30) 442 #define TTA_BIT (U(1) << 20) 443 #define TFP_BIT (U(1) << 10) 444 #define CPTR_EZ_BIT (U(1) << 8) 445 #define CPTR_EL3_RESET_VAL U(0x0) 446 447 /* CPTR_EL2 definitions */ 448 #define CPTR_EL2_RES1 ((U(1) << 13) | (U(1) << 12) | (U(0x3ff))) 449 #define CPTR_EL2_TCPAC_BIT (U(1) << 31) 450 #define CPTR_EL2_TAM_BIT (U(1) << 30) 451 #define CPTR_EL2_TTA_BIT (U(1) << 20) 452 #define CPTR_EL2_TFP_BIT (U(1) << 10) 453 #define CPTR_EL2_TZ_BIT (U(1) << 8) 454 #define CPTR_EL2_RESET_VAL CPTR_EL2_RES1 455 456 /* CPSR/SPSR definitions */ 457 #define DAIF_FIQ_BIT (U(1) << 0) 458 #define DAIF_IRQ_BIT (U(1) << 1) 459 #define DAIF_ABT_BIT (U(1) << 2) 460 #define DAIF_DBG_BIT (U(1) << 3) 461 #define SPSR_DAIF_SHIFT U(6) 462 #define SPSR_DAIF_MASK U(0xf) 463 464 #define SPSR_AIF_SHIFT U(6) 465 #define SPSR_AIF_MASK U(0x7) 466 467 #define SPSR_E_SHIFT U(9) 468 #define SPSR_E_MASK U(0x1) 469 #define SPSR_E_LITTLE U(0x0) 470 #define SPSR_E_BIG U(0x1) 471 472 #define SPSR_T_SHIFT U(5) 473 #define SPSR_T_MASK U(0x1) 474 #define SPSR_T_ARM U(0x0) 475 #define SPSR_T_THUMB U(0x1) 476 477 #define SPSR_M_SHIFT U(4) 478 #define SPSR_M_MASK U(0x1) 479 #define SPSR_M_AARCH64 U(0x0) 480 #define SPSR_M_AARCH32 U(0x1) 481 482 #define SPSR_EL_SHIFT U(2) 483 #define SPSR_EL_WIDTH U(2) 484 485 #define SPSR_SSBS_BIT_AARCH64 BIT_64(12) 486 #define SPSR_SSBS_BIT_AARCH32 BIT_64(23) 487 488 #define DISABLE_ALL_EXCEPTIONS \ 489 (DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT | DAIF_DBG_BIT) 490 491 #define DISABLE_INTERRUPTS (DAIF_FIQ_BIT | DAIF_IRQ_BIT) 492 493 /* 494 * RMR_EL3 definitions 495 */ 496 #define RMR_EL3_RR_BIT (U(1) << 1) 497 #define RMR_EL3_AA64_BIT (U(1) << 0) 498 499 /* 500 * HI-VECTOR address for AArch32 state 501 */ 502 #define HI_VECTOR_BASE U(0xFFFF0000) 503 504 /* 505 * TCR defintions 506 */ 507 #define TCR_EL3_RES1 ((ULL(1) << 31) | (ULL(1) << 23)) 508 #define TCR_EL2_RES1 ((ULL(1) << 31) | (ULL(1) << 23)) 509 #define TCR_EL1_IPS_SHIFT U(32) 510 #define TCR_EL2_PS_SHIFT U(16) 511 #define TCR_EL3_PS_SHIFT U(16) 512 513 #define TCR_TxSZ_MIN ULL(16) 514 #define TCR_TxSZ_MAX ULL(39) 515 #define TCR_TxSZ_MAX_TTST ULL(48) 516 517 #define TCR_T0SZ_SHIFT U(0) 518 #define TCR_T1SZ_SHIFT U(16) 519 520 /* (internal) physical address size bits in EL3/EL1 */ 521 #define TCR_PS_BITS_4GB ULL(0x0) 522 #define TCR_PS_BITS_64GB ULL(0x1) 523 #define TCR_PS_BITS_1TB ULL(0x2) 524 #define TCR_PS_BITS_4TB ULL(0x3) 525 #define TCR_PS_BITS_16TB ULL(0x4) 526 #define TCR_PS_BITS_256TB ULL(0x5) 527 528 #define ADDR_MASK_48_TO_63 ULL(0xFFFF000000000000) 529 #define ADDR_MASK_44_TO_47 ULL(0x0000F00000000000) 530 #define ADDR_MASK_42_TO_43 ULL(0x00000C0000000000) 531 #define ADDR_MASK_40_TO_41 ULL(0x0000030000000000) 532 #define ADDR_MASK_36_TO_39 ULL(0x000000F000000000) 533 #define ADDR_MASK_32_TO_35 ULL(0x0000000F00000000) 534 535 #define TCR_RGN_INNER_NC (ULL(0x0) << 8) 536 #define TCR_RGN_INNER_WBA (ULL(0x1) << 8) 537 #define TCR_RGN_INNER_WT (ULL(0x2) << 8) 538 #define TCR_RGN_INNER_WBNA (ULL(0x3) << 8) 539 540 #define TCR_RGN_OUTER_NC (ULL(0x0) << 10) 541 #define TCR_RGN_OUTER_WBA (ULL(0x1) << 10) 542 #define TCR_RGN_OUTER_WT (ULL(0x2) << 10) 543 #define TCR_RGN_OUTER_WBNA (ULL(0x3) << 10) 544 545 #define TCR_SH_NON_SHAREABLE (ULL(0x0) << 12) 546 #define TCR_SH_OUTER_SHAREABLE (ULL(0x2) << 12) 547 #define TCR_SH_INNER_SHAREABLE (ULL(0x3) << 12) 548 549 #define TCR_RGN1_INNER_NC (ULL(0x0) << 24) 550 #define TCR_RGN1_INNER_WBA (ULL(0x1) << 24) 551 #define TCR_RGN1_INNER_WT (ULL(0x2) << 24) 552 #define TCR_RGN1_INNER_WBNA (ULL(0x3) << 24) 553 554 #define TCR_RGN1_OUTER_NC (ULL(0x0) << 26) 555 #define TCR_RGN1_OUTER_WBA (ULL(0x1) << 26) 556 #define TCR_RGN1_OUTER_WT (ULL(0x2) << 26) 557 #define TCR_RGN1_OUTER_WBNA (ULL(0x3) << 26) 558 559 #define TCR_SH1_NON_SHAREABLE (ULL(0x0) << 28) 560 #define TCR_SH1_OUTER_SHAREABLE (ULL(0x2) << 28) 561 #define TCR_SH1_INNER_SHAREABLE (ULL(0x3) << 28) 562 563 #define TCR_TG0_SHIFT U(14) 564 #define TCR_TG0_MASK ULL(3) 565 #define TCR_TG0_4K (ULL(0) << TCR_TG0_SHIFT) 566 #define TCR_TG0_64K (ULL(1) << TCR_TG0_SHIFT) 567 #define TCR_TG0_16K (ULL(2) << TCR_TG0_SHIFT) 568 569 #define TCR_TG1_SHIFT U(30) 570 #define TCR_TG1_MASK ULL(3) 571 #define TCR_TG1_16K (ULL(1) << TCR_TG1_SHIFT) 572 #define TCR_TG1_4K (ULL(2) << TCR_TG1_SHIFT) 573 #define TCR_TG1_64K (ULL(3) << TCR_TG1_SHIFT) 574 575 #define TCR_EPD0_BIT (ULL(1) << 7) 576 #define TCR_EPD1_BIT (ULL(1) << 23) 577 578 #define MODE_SP_SHIFT U(0x0) 579 #define MODE_SP_MASK U(0x1) 580 #define MODE_SP_EL0 U(0x0) 581 #define MODE_SP_ELX U(0x1) 582 583 #define MODE_RW_SHIFT U(0x4) 584 #define MODE_RW_MASK U(0x1) 585 #define MODE_RW_64 U(0x0) 586 #define MODE_RW_32 U(0x1) 587 588 #define MODE_EL_SHIFT U(0x2) 589 #define MODE_EL_MASK U(0x3) 590 #define MODE_EL_WIDTH U(0x2) 591 #define MODE_EL3 U(0x3) 592 #define MODE_EL2 U(0x2) 593 #define MODE_EL1 U(0x1) 594 #define MODE_EL0 U(0x0) 595 596 #define MODE32_SHIFT U(0) 597 #define MODE32_MASK U(0xf) 598 #define MODE32_usr U(0x0) 599 #define MODE32_fiq U(0x1) 600 #define MODE32_irq U(0x2) 601 #define MODE32_svc U(0x3) 602 #define MODE32_mon U(0x6) 603 #define MODE32_abt U(0x7) 604 #define MODE32_hyp U(0xa) 605 #define MODE32_und U(0xb) 606 #define MODE32_sys U(0xf) 607 608 #define GET_RW(mode) (((mode) >> MODE_RW_SHIFT) & MODE_RW_MASK) 609 #define GET_EL(mode) (((mode) >> MODE_EL_SHIFT) & MODE_EL_MASK) 610 #define GET_SP(mode) (((mode) >> MODE_SP_SHIFT) & MODE_SP_MASK) 611 #define GET_M32(mode) (((mode) >> MODE32_SHIFT) & MODE32_MASK) 612 613 #define SPSR_64(el, sp, daif) \ 614 (((MODE_RW_64 << MODE_RW_SHIFT) | \ 615 (((el) & MODE_EL_MASK) << MODE_EL_SHIFT) | \ 616 (((sp) & MODE_SP_MASK) << MODE_SP_SHIFT) | \ 617 (((daif) & SPSR_DAIF_MASK) << SPSR_DAIF_SHIFT)) & \ 618 (~(SPSR_SSBS_BIT_AARCH64))) 619 620 #define SPSR_MODE32(mode, isa, endian, aif) \ 621 (((MODE_RW_32 << MODE_RW_SHIFT) | \ 622 (((mode) & MODE32_MASK) << MODE32_SHIFT) | \ 623 (((isa) & SPSR_T_MASK) << SPSR_T_SHIFT) | \ 624 (((endian) & SPSR_E_MASK) << SPSR_E_SHIFT) | \ 625 (((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT)) & \ 626 (~(SPSR_SSBS_BIT_AARCH32))) 627 628 /* 629 * TTBR Definitions 630 */ 631 #define TTBR_CNP_BIT ULL(0x1) 632 633 /* 634 * CTR_EL0 definitions 635 */ 636 #define CTR_CWG_SHIFT U(24) 637 #define CTR_CWG_MASK U(0xf) 638 #define CTR_ERG_SHIFT U(20) 639 #define CTR_ERG_MASK U(0xf) 640 #define CTR_DMINLINE_SHIFT U(16) 641 #define CTR_DMINLINE_MASK U(0xf) 642 #define CTR_L1IP_SHIFT U(14) 643 #define CTR_L1IP_MASK U(0x3) 644 #define CTR_IMINLINE_SHIFT U(0) 645 #define CTR_IMINLINE_MASK U(0xf) 646 647 #define MAX_CACHE_LINE_SIZE U(0x800) /* 2KB */ 648 649 /* Physical timer control register bit fields shifts and masks */ 650 #define CNTP_CTL_ENABLE_SHIFT U(0) 651 #define CNTP_CTL_IMASK_SHIFT U(1) 652 #define CNTP_CTL_ISTATUS_SHIFT U(2) 653 654 #define CNTP_CTL_ENABLE_MASK U(1) 655 #define CNTP_CTL_IMASK_MASK U(1) 656 #define CNTP_CTL_ISTATUS_MASK U(1) 657 658 /* Physical timer control macros */ 659 #define CNTP_CTL_ENABLE_BIT (U(1) << CNTP_CTL_ENABLE_SHIFT) 660 #define CNTP_CTL_IMASK_BIT (U(1) << CNTP_CTL_IMASK_SHIFT) 661 662 /* Exception Syndrome register bits and bobs */ 663 #define ESR_EC_SHIFT U(26) 664 #define ESR_EC_MASK U(0x3f) 665 #define ESR_EC_LENGTH U(6) 666 #define ESR_ISS_SHIFT U(0) 667 #define ESR_ISS_LENGTH U(25) 668 #define EC_UNKNOWN U(0x0) 669 #define EC_WFE_WFI U(0x1) 670 #define EC_AARCH32_CP15_MRC_MCR U(0x3) 671 #define EC_AARCH32_CP15_MRRC_MCRR U(0x4) 672 #define EC_AARCH32_CP14_MRC_MCR U(0x5) 673 #define EC_AARCH32_CP14_LDC_STC U(0x6) 674 #define EC_FP_SIMD U(0x7) 675 #define EC_AARCH32_CP10_MRC U(0x8) 676 #define EC_AARCH32_CP14_MRRC_MCRR U(0xc) 677 #define EC_ILLEGAL U(0xe) 678 #define EC_AARCH32_SVC U(0x11) 679 #define EC_AARCH32_HVC U(0x12) 680 #define EC_AARCH32_SMC U(0x13) 681 #define EC_AARCH64_SVC U(0x15) 682 #define EC_AARCH64_HVC U(0x16) 683 #define EC_AARCH64_SMC U(0x17) 684 #define EC_AARCH64_SYS U(0x18) 685 #define EC_IABORT_LOWER_EL U(0x20) 686 #define EC_IABORT_CUR_EL U(0x21) 687 #define EC_PC_ALIGN U(0x22) 688 #define EC_DABORT_LOWER_EL U(0x24) 689 #define EC_DABORT_CUR_EL U(0x25) 690 #define EC_SP_ALIGN U(0x26) 691 #define EC_AARCH32_FP U(0x28) 692 #define EC_AARCH64_FP U(0x2c) 693 #define EC_SERROR U(0x2f) 694 #define EC_BRK U(0x3c) 695 696 /* 697 * External Abort bit in Instruction and Data Aborts synchronous exception 698 * syndromes. 699 */ 700 #define ESR_ISS_EABORT_EA_BIT U(9) 701 702 #define EC_BITS(x) (((x) >> ESR_EC_SHIFT) & ESR_EC_MASK) 703 704 /* Reset bit inside the Reset management register for EL3 (RMR_EL3) */ 705 #define RMR_RESET_REQUEST_SHIFT U(0x1) 706 #define RMR_WARM_RESET_CPU (U(1) << RMR_RESET_REQUEST_SHIFT) 707 708 /******************************************************************************* 709 * Definitions of register offsets, fields and macros for CPU system 710 * instructions. 711 ******************************************************************************/ 712 713 #define TLBI_ADDR_SHIFT U(12) 714 #define TLBI_ADDR_MASK ULL(0x00000FFFFFFFFFFF) 715 #define TLBI_ADDR(x) (((x) >> TLBI_ADDR_SHIFT) & TLBI_ADDR_MASK) 716 717 /******************************************************************************* 718 * Definitions of register offsets and fields in the CNTCTLBase Frame of the 719 * system level implementation of the Generic Timer. 720 ******************************************************************************/ 721 #define CNTCTLBASE_CNTFRQ U(0x0) 722 #define CNTNSAR U(0x4) 723 #define CNTNSAR_NS_SHIFT(x) (x) 724 725 #define CNTACR_BASE(x) (U(0x40) + ((x) << 2)) 726 #define CNTACR_RPCT_SHIFT U(0x0) 727 #define CNTACR_RVCT_SHIFT U(0x1) 728 #define CNTACR_RFRQ_SHIFT U(0x2) 729 #define CNTACR_RVOFF_SHIFT U(0x3) 730 #define CNTACR_RWVT_SHIFT U(0x4) 731 #define CNTACR_RWPT_SHIFT U(0x5) 732 733 /******************************************************************************* 734 * Definitions of register offsets and fields in the CNTBaseN Frame of the 735 * system level implementation of the Generic Timer. 736 ******************************************************************************/ 737 /* Physical Count register. */ 738 #define CNTPCT_LO U(0x0) 739 /* Counter Frequency register. */ 740 #define CNTBASEN_CNTFRQ U(0x10) 741 /* Physical Timer CompareValue register. */ 742 #define CNTP_CVAL_LO U(0x20) 743 /* Physical Timer Control register. */ 744 #define CNTP_CTL U(0x2c) 745 746 /* PMCR_EL0 definitions */ 747 #define PMCR_EL0_RESET_VAL U(0x0) 748 #define PMCR_EL0_N_SHIFT U(11) 749 #define PMCR_EL0_N_MASK U(0x1f) 750 #define PMCR_EL0_N_BITS (PMCR_EL0_N_MASK << PMCR_EL0_N_SHIFT) 751 #define PMCR_EL0_LP_BIT (U(1) << 7) 752 #define PMCR_EL0_LC_BIT (U(1) << 6) 753 #define PMCR_EL0_DP_BIT (U(1) << 5) 754 #define PMCR_EL0_X_BIT (U(1) << 4) 755 #define PMCR_EL0_D_BIT (U(1) << 3) 756 #define PMCR_EL0_C_BIT (U(1) << 2) 757 #define PMCR_EL0_P_BIT (U(1) << 1) 758 #define PMCR_EL0_E_BIT (U(1) << 0) 759 760 /******************************************************************************* 761 * Definitions for system register interface to SVE 762 ******************************************************************************/ 763 #define ZCR_EL3 S3_6_C1_C2_0 764 #define ZCR_EL2 S3_4_C1_C2_0 765 766 /* ZCR_EL3 definitions */ 767 #define ZCR_EL3_LEN_MASK U(0xf) 768 769 /* ZCR_EL2 definitions */ 770 #define ZCR_EL2_LEN_MASK U(0xf) 771 772 /******************************************************************************* 773 * Definitions of MAIR encodings for device and normal memory 774 ******************************************************************************/ 775 /* 776 * MAIR encodings for device memory attributes. 777 */ 778 #define MAIR_DEV_nGnRnE ULL(0x0) 779 #define MAIR_DEV_nGnRE ULL(0x4) 780 #define MAIR_DEV_nGRE ULL(0x8) 781 #define MAIR_DEV_GRE ULL(0xc) 782 783 /* 784 * MAIR encodings for normal memory attributes. 785 * 786 * Cache Policy 787 * WT: Write Through 788 * WB: Write Back 789 * NC: Non-Cacheable 790 * 791 * Transient Hint 792 * NTR: Non-Transient 793 * TR: Transient 794 * 795 * Allocation Policy 796 * RA: Read Allocate 797 * WA: Write Allocate 798 * RWA: Read and Write Allocate 799 * NA: No Allocation 800 */ 801 #define MAIR_NORM_WT_TR_WA ULL(0x1) 802 #define MAIR_NORM_WT_TR_RA ULL(0x2) 803 #define MAIR_NORM_WT_TR_RWA ULL(0x3) 804 #define MAIR_NORM_NC ULL(0x4) 805 #define MAIR_NORM_WB_TR_WA ULL(0x5) 806 #define MAIR_NORM_WB_TR_RA ULL(0x6) 807 #define MAIR_NORM_WB_TR_RWA ULL(0x7) 808 #define MAIR_NORM_WT_NTR_NA ULL(0x8) 809 #define MAIR_NORM_WT_NTR_WA ULL(0x9) 810 #define MAIR_NORM_WT_NTR_RA ULL(0xa) 811 #define MAIR_NORM_WT_NTR_RWA ULL(0xb) 812 #define MAIR_NORM_WB_NTR_NA ULL(0xc) 813 #define MAIR_NORM_WB_NTR_WA ULL(0xd) 814 #define MAIR_NORM_WB_NTR_RA ULL(0xe) 815 #define MAIR_NORM_WB_NTR_RWA ULL(0xf) 816 817 #define MAIR_NORM_OUTER_SHIFT U(4) 818 819 #define MAKE_MAIR_NORMAL_MEMORY(inner, outer) \ 820 ((inner) | ((outer) << MAIR_NORM_OUTER_SHIFT)) 821 822 /* PAR_EL1 fields */ 823 #define PAR_F_SHIFT U(0) 824 #define PAR_F_MASK ULL(0x1) 825 #define PAR_ADDR_SHIFT U(12) 826 #define PAR_ADDR_MASK (BIT(40) - ULL(1)) /* 40-bits-wide page address */ 827 828 /******************************************************************************* 829 * Definitions for system register interface to SPE 830 ******************************************************************************/ 831 #define PMBLIMITR_EL1 S3_0_C9_C10_0 832 833 /******************************************************************************* 834 * Definitions for system register interface to MPAM 835 ******************************************************************************/ 836 #define MPAMIDR_EL1 S3_0_C10_C4_4 837 #define MPAM2_EL2 S3_4_C10_C5_0 838 #define MPAMHCR_EL2 S3_4_C10_C4_0 839 #define MPAM3_EL3 S3_6_C10_C5_0 840 841 /******************************************************************************* 842 * Definitions for system register interface to AMU for ARMv8.4 onwards 843 ******************************************************************************/ 844 #define AMCR_EL0 S3_3_C13_C2_0 845 #define AMCFGR_EL0 S3_3_C13_C2_1 846 #define AMCGCR_EL0 S3_3_C13_C2_2 847 #define AMUSERENR_EL0 S3_3_C13_C2_3 848 #define AMCNTENCLR0_EL0 S3_3_C13_C2_4 849 #define AMCNTENSET0_EL0 S3_3_C13_C2_5 850 #define AMCNTENCLR1_EL0 S3_3_C13_C3_0 851 #define AMCNTENSET1_EL0 S3_3_C13_C3_1 852 853 /* Activity Monitor Group 0 Event Counter Registers */ 854 #define AMEVCNTR00_EL0 S3_3_C13_C4_0 855 #define AMEVCNTR01_EL0 S3_3_C13_C4_1 856 #define AMEVCNTR02_EL0 S3_3_C13_C4_2 857 #define AMEVCNTR03_EL0 S3_3_C13_C4_3 858 859 /* Activity Monitor Group 0 Event Type Registers */ 860 #define AMEVTYPER00_EL0 S3_3_C13_C6_0 861 #define AMEVTYPER01_EL0 S3_3_C13_C6_1 862 #define AMEVTYPER02_EL0 S3_3_C13_C6_2 863 #define AMEVTYPER03_EL0 S3_3_C13_C6_3 864 865 /* Activity Monitor Group 1 Event Counter Registers */ 866 #define AMEVCNTR10_EL0 S3_3_C13_C12_0 867 #define AMEVCNTR11_EL0 S3_3_C13_C12_1 868 #define AMEVCNTR12_EL0 S3_3_C13_C12_2 869 #define AMEVCNTR13_EL0 S3_3_C13_C12_3 870 #define AMEVCNTR14_EL0 S3_3_C13_C12_4 871 #define AMEVCNTR15_EL0 S3_3_C13_C12_5 872 #define AMEVCNTR16_EL0 S3_3_C13_C12_6 873 #define AMEVCNTR17_EL0 S3_3_C13_C12_7 874 #define AMEVCNTR18_EL0 S3_3_C13_C13_0 875 #define AMEVCNTR19_EL0 S3_3_C13_C13_1 876 #define AMEVCNTR1A_EL0 S3_3_C13_C13_2 877 #define AMEVCNTR1B_EL0 S3_3_C13_C13_3 878 #define AMEVCNTR1C_EL0 S3_3_C13_C13_4 879 #define AMEVCNTR1D_EL0 S3_3_C13_C13_5 880 #define AMEVCNTR1E_EL0 S3_3_C13_C13_6 881 #define AMEVCNTR1F_EL0 S3_3_C13_C13_7 882 883 /* Activity Monitor Group 1 Event Type Registers */ 884 #define AMEVTYPER10_EL0 S3_3_C13_C14_0 885 #define AMEVTYPER11_EL0 S3_3_C13_C14_1 886 #define AMEVTYPER12_EL0 S3_3_C13_C14_2 887 #define AMEVTYPER13_EL0 S3_3_C13_C14_3 888 #define AMEVTYPER14_EL0 S3_3_C13_C14_4 889 #define AMEVTYPER15_EL0 S3_3_C13_C14_5 890 #define AMEVTYPER16_EL0 S3_3_C13_C14_6 891 #define AMEVTYPER17_EL0 S3_3_C13_C14_7 892 #define AMEVTYPER18_EL0 S3_3_C13_C15_0 893 #define AMEVTYPER19_EL0 S3_3_C13_C15_1 894 #define AMEVTYPER1A_EL0 S3_3_C13_C15_2 895 #define AMEVTYPER1B_EL0 S3_3_C13_C15_3 896 #define AMEVTYPER1C_EL0 S3_3_C13_C15_4 897 #define AMEVTYPER1D_EL0 S3_3_C13_C15_5 898 #define AMEVTYPER1E_EL0 S3_3_C13_C15_6 899 #define AMEVTYPER1F_EL0 S3_3_C13_C15_7 900 901 /* AMCGCR_EL0 definitions */ 902 #define AMCGCR_EL0_CG1NC_SHIFT U(8) 903 #define AMCGCR_EL0_CG1NC_LENGTH U(8) 904 #define AMCGCR_EL0_CG1NC_MASK U(0xff) 905 906 /* MPAM register definitions */ 907 #define MPAM3_EL3_MPAMEN_BIT (ULL(1) << 63) 908 #define MPAMHCR_EL2_TRAP_MPAMIDR_EL1 (ULL(1) << 31) 909 910 #define MPAM2_EL2_TRAPMPAM0EL1 (ULL(1) << 49) 911 #define MPAM2_EL2_TRAPMPAM1EL1 (ULL(1) << 48) 912 913 #define MPAMIDR_HAS_HCR_BIT (ULL(1) << 17) 914 915 /******************************************************************************* 916 * RAS system registers 917 ******************************************************************************/ 918 #define DISR_EL1 S3_0_C12_C1_1 919 #define DISR_A_BIT U(31) 920 921 #define ERRIDR_EL1 S3_0_C5_C3_0 922 #define ERRIDR_MASK U(0xffff) 923 924 #define ERRSELR_EL1 S3_0_C5_C3_1 925 926 /* System register access to Standard Error Record registers */ 927 #define ERXFR_EL1 S3_0_C5_C4_0 928 #define ERXCTLR_EL1 S3_0_C5_C4_1 929 #define ERXSTATUS_EL1 S3_0_C5_C4_2 930 #define ERXADDR_EL1 S3_0_C5_C4_3 931 #define ERXPFGF_EL1 S3_0_C5_C4_4 932 #define ERXPFGCTL_EL1 S3_0_C5_C4_5 933 #define ERXPFGCDN_EL1 S3_0_C5_C4_6 934 #define ERXMISC0_EL1 S3_0_C5_C5_0 935 #define ERXMISC1_EL1 S3_0_C5_C5_1 936 937 #define ERXCTLR_ED_BIT (U(1) << 0) 938 #define ERXCTLR_UE_BIT (U(1) << 4) 939 940 #define ERXPFGCTL_UC_BIT (U(1) << 1) 941 #define ERXPFGCTL_UEU_BIT (U(1) << 2) 942 #define ERXPFGCTL_CDEN_BIT (U(1) << 31) 943 944 /******************************************************************************* 945 * Armv8.3 Pointer Authentication Registers 946 ******************************************************************************/ 947 #define APIAKeyLo_EL1 S3_0_C2_C1_0 948 #define APIAKeyHi_EL1 S3_0_C2_C1_1 949 #define APIBKeyLo_EL1 S3_0_C2_C1_2 950 #define APIBKeyHi_EL1 S3_0_C2_C1_3 951 #define APDAKeyLo_EL1 S3_0_C2_C2_0 952 #define APDAKeyHi_EL1 S3_0_C2_C2_1 953 #define APDBKeyLo_EL1 S3_0_C2_C2_2 954 #define APDBKeyHi_EL1 S3_0_C2_C2_3 955 #define APGAKeyLo_EL1 S3_0_C2_C3_0 956 #define APGAKeyHi_EL1 S3_0_C2_C3_1 957 958 /******************************************************************************* 959 * Armv8.4 Data Independent Timing Registers 960 ******************************************************************************/ 961 #define DIT S3_3_C4_C2_5 962 #define DIT_BIT BIT(24) 963 964 /******************************************************************************* 965 * Armv8.5 - new MSR encoding to directly access PSTATE.SSBS field 966 ******************************************************************************/ 967 #define SSBS S3_3_C4_C2_6 968 969 /******************************************************************************* 970 * Armv8.5 - Memory Tagging Extension Registers 971 ******************************************************************************/ 972 #define TFSRE0_EL1 S3_0_C5_C6_1 973 #define TFSR_EL1 S3_0_C5_C6_0 974 #define RGSR_EL1 S3_0_C1_C0_5 975 #define GCR_EL1 S3_0_C1_C0_6 976 977 /******************************************************************************* 978 * Definitions for DynamicIQ Shared Unit registers 979 ******************************************************************************/ 980 #define CLUSTERPWRDN_EL1 S3_0_c15_c3_6 981 982 /* CLUSTERPWRDN_EL1 register definitions */ 983 #define DSU_CLUSTER_PWR_OFF 0 984 #define DSU_CLUSTER_PWR_ON 1 985 #define DSU_CLUSTER_PWR_MASK U(1) 986 987 #endif /* ARCH_H */ 988