1/* 2 * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#ifndef EL3_COMMON_MACROS_S 8#define EL3_COMMON_MACROS_S 9 10#include <arch.h> 11#include <asm_macros.S> 12#include <assert_macros.S> 13 14 /* 15 * Helper macro to initialise EL3 registers we care about. 16 */ 17 .macro el3_arch_init_common 18 /* --------------------------------------------------------------------- 19 * SCTLR has already been initialised - read current value before 20 * modifying. 21 * 22 * SCTLR.I: Enable the instruction cache. 23 * 24 * SCTLR.A: Enable Alignment fault checking. All instructions that load 25 * or store one or more registers have an alignment check that the 26 * address being accessed is aligned to the size of the data element(s) 27 * being accessed. 28 * --------------------------------------------------------------------- 29 */ 30 ldr r1, =(SCTLR_I_BIT | SCTLR_A_BIT) 31 ldcopr r0, SCTLR 32 orr r0, r0, r1 33 stcopr r0, SCTLR 34 isb 35 36 /* --------------------------------------------------------------------- 37 * Initialise SCR, setting all fields rather than relying on the hw. 38 * 39 * SCR.SIF: Enabled so that Secure state instruction fetches from 40 * Non-secure memory are not permitted. 41 * --------------------------------------------------------------------- 42 */ 43 ldr r0, =(SCR_RESET_VAL | SCR_SIF_BIT) 44 stcopr r0, SCR 45 46 /* ----------------------------------------------------- 47 * Enable the Asynchronous data abort now that the 48 * exception vectors have been setup. 49 * ----------------------------------------------------- 50 */ 51 cpsie a 52 isb 53 54 /* --------------------------------------------------------------------- 55 * Initialise NSACR, setting all the fields, except for the 56 * IMPLEMENTATION DEFINED field, rather than relying on the hw. Some 57 * fields are architecturally UNKNOWN on reset. 58 * 59 * NSACR_ENABLE_FP_ACCESS: Represents NSACR.cp11 and NSACR.cp10. The 60 * cp11 field is ignored, but is set to same value as cp10. The cp10 61 * field is set to allow access to Advanced SIMD and floating point 62 * features from both Security states. 63 * --------------------------------------------------------------------- 64 */ 65 ldcopr r0, NSACR 66 and r0, r0, #NSACR_IMP_DEF_MASK 67 orr r0, r0, #(NSACR_RESET_VAL | NSACR_ENABLE_FP_ACCESS) 68 stcopr r0, NSACR 69 isb 70 71 /* --------------------------------------------------------------------- 72 * Initialise CPACR, setting all fields rather than relying on hw. Some 73 * fields are architecturally UNKNOWN on reset. 74 * 75 * CPACR.TRCDIS: Trap control for PL0 and PL1 System register accesses 76 * to trace registers. Set to zero to allow access. 77 * 78 * CPACR_ENABLE_FP_ACCESS: Represents CPACR.cp11 and CPACR.cp10. The 79 * cp11 field is ignored, but is set to same value as cp10. The cp10 80 * field is set to allow full access from PL0 and PL1 to floating-point 81 * and Advanced SIMD features. 82 * --------------------------------------------------------------------- 83 */ 84 ldr r0, =((CPACR_RESET_VAL | CPACR_ENABLE_FP_ACCESS) & ~(TRCDIS_BIT)) 85 stcopr r0, CPACR 86 isb 87 88 /* --------------------------------------------------------------------- 89 * Initialise FPEXC, setting all fields rather than relying on hw. Some 90 * fields are architecturally UNKNOWN on reset and are set to zero 91 * except for field(s) listed below. 92 * 93 * FPEXC.EN: Enable access to Advanced SIMD and floating point features 94 * from all exception levels. 95 * 96 * __SOFTFP__: Predefined macro exposed by soft-float toolchain. 97 * ARMv7 and Cortex-A32(ARMv8/aarch32) has both soft-float and 98 * hard-float variants of toolchain, avoid compiling below code with 99 * soft-float toolchain as "vmsr" instruction will not be recognized. 100 * --------------------------------------------------------------------- 101 */ 102#if ((ARM_ARCH_MAJOR > 7) || defined(ARMV7_SUPPORTS_VFP)) && !(__SOFTFP__) 103 ldr r0, =(FPEXC_RESET_VAL | FPEXC_EN_BIT) 104 vmsr FPEXC, r0 105 isb 106#endif 107 108#if (ARM_ARCH_MAJOR > 7) 109 /* --------------------------------------------------------------------- 110 * Initialise SDCR, setting all the fields rather than relying on hw. 111 * 112 * SDCR.SPD: Disable AArch32 privileged debug. Debug exceptions from 113 * Secure EL1 are disabled. 114 * 115 * SDCR: Set to one so that cycle counting by PMCCNTR is prohibited in 116 * Secure state. This bit is RES0 in versions of the architecture 117 * earlier than ARMv8.5, setting it to 1 doesn't have any effect on 118 * them. 119 * --------------------------------------------------------------------- 120 */ 121 ldr r0, =(SDCR_RESET_VAL | SDCR_SPD(SDCR_SPD_DISABLE) | SDCR_SCCD_BIT) 122 stcopr r0, SDCR 123#endif 124 125 /* 126 * If Data Independent Timing (DIT) functionality is implemented, 127 * always enable DIT in EL3 128 */ 129 ldcopr r0, ID_PFR0 130 and r0, r0, #(ID_PFR0_DIT_MASK << ID_PFR0_DIT_SHIFT) 131 cmp r0, #ID_PFR0_DIT_SUPPORTED 132 bne 1f 133 mrs r0, cpsr 134 orr r0, r0, #CPSR_DIT_BIT 135 msr cpsr_cxsf, r0 1361: 137 .endm 138 139/* ----------------------------------------------------------------------------- 140 * This is the super set of actions that need to be performed during a cold boot 141 * or a warm boot in EL3. This code is shared by BL1 and BL32 (SP_MIN). 142 * 143 * This macro will always perform reset handling, architectural initialisations 144 * and stack setup. The rest of the actions are optional because they might not 145 * be needed, depending on the context in which this macro is called. This is 146 * why this macro is parameterised ; each parameter allows to enable/disable 147 * some actions. 148 * 149 * _init_sctlr: 150 * Whether the macro needs to initialise the SCTLR register including 151 * configuring the endianness of data accesses. 152 * 153 * _warm_boot_mailbox: 154 * Whether the macro needs to detect the type of boot (cold/warm). The 155 * detection is based on the platform entrypoint address : if it is zero 156 * then it is a cold boot, otherwise it is a warm boot. In the latter case, 157 * this macro jumps on the platform entrypoint address. 158 * 159 * _secondary_cold_boot: 160 * Whether the macro needs to identify the CPU that is calling it: primary 161 * CPU or secondary CPU. The primary CPU will be allowed to carry on with 162 * the platform initialisations, while the secondaries will be put in a 163 * platform-specific state in the meantime. 164 * 165 * If the caller knows this macro will only be called by the primary CPU 166 * then this parameter can be defined to 0 to skip this step. 167 * 168 * _init_memory: 169 * Whether the macro needs to initialise the memory. 170 * 171 * _init_c_runtime: 172 * Whether the macro needs to initialise the C runtime environment. 173 * 174 * _exception_vectors: 175 * Address of the exception vectors to program in the VBAR_EL3 register. 176 * ----------------------------------------------------------------------------- 177 */ 178 .macro el3_entrypoint_common \ 179 _init_sctlr, _warm_boot_mailbox, _secondary_cold_boot, \ 180 _init_memory, _init_c_runtime, _exception_vectors 181 182 /* Make sure we are in Secure Mode */ 183#if ENABLE_ASSERTIONS 184 ldcopr r0, SCR 185 tst r0, #SCR_NS_BIT 186 ASM_ASSERT(eq) 187#endif 188 189 .if \_init_sctlr 190 /* ------------------------------------------------------------- 191 * This is the initialisation of SCTLR and so must ensure that 192 * all fields are explicitly set rather than relying on hw. Some 193 * fields reset to an IMPLEMENTATION DEFINED value. 194 * 195 * SCTLR.TE: Set to zero so that exceptions to an Exception 196 * Level executing at PL1 are taken to A32 state. 197 * 198 * SCTLR.EE: Set the CPU endianness before doing anything that 199 * might involve memory reads or writes. Set to zero to select 200 * Little Endian. 201 * 202 * SCTLR.V: Set to zero to select the normal exception vectors 203 * with base address held in VBAR. 204 * 205 * SCTLR.DSSBS: Set to zero to disable speculation store bypass 206 * safe behaviour upon exception entry to EL3. 207 * ------------------------------------------------------------- 208 */ 209 ldr r0, =(SCTLR_RESET_VAL & ~(SCTLR_TE_BIT | SCTLR_EE_BIT | \ 210 SCTLR_V_BIT | SCTLR_DSSBS_BIT)) 211 stcopr r0, SCTLR 212 isb 213 .endif /* _init_sctlr */ 214 215 /* Switch to monitor mode */ 216 cps #MODE32_mon 217 isb 218 219 .if \_warm_boot_mailbox 220 /* ------------------------------------------------------------- 221 * This code will be executed for both warm and cold resets. 222 * Now is the time to distinguish between the two. 223 * Query the platform entrypoint address and if it is not zero 224 * then it means it is a warm boot so jump to this address. 225 * ------------------------------------------------------------- 226 */ 227 bl plat_get_my_entrypoint 228 cmp r0, #0 229 bxne r0 230 .endif /* _warm_boot_mailbox */ 231 232 /* --------------------------------------------------------------------- 233 * Set the exception vectors (VBAR/MVBAR). 234 * --------------------------------------------------------------------- 235 */ 236 ldr r0, =\_exception_vectors 237 stcopr r0, VBAR 238 stcopr r0, MVBAR 239 isb 240 241 /* --------------------------------------------------------------------- 242 * It is a cold boot. 243 * Perform any processor specific actions upon reset e.g. cache, TLB 244 * invalidations etc. 245 * --------------------------------------------------------------------- 246 */ 247 bl reset_handler 248 249 el3_arch_init_common 250 251 .if \_secondary_cold_boot 252 /* ------------------------------------------------------------- 253 * Check if this is a primary or secondary CPU cold boot. 254 * The primary CPU will set up the platform while the 255 * secondaries are placed in a platform-specific state until the 256 * primary CPU performs the necessary actions to bring them out 257 * of that state and allows entry into the OS. 258 * ------------------------------------------------------------- 259 */ 260 bl plat_is_my_cpu_primary 261 cmp r0, #0 262 bne do_primary_cold_boot 263 264 /* This is a cold boot on a secondary CPU */ 265 bl plat_secondary_cold_boot_setup 266 /* plat_secondary_cold_boot_setup() is not supposed to return */ 267 no_ret plat_panic_handler 268 269 do_primary_cold_boot: 270 .endif /* _secondary_cold_boot */ 271 272 /* --------------------------------------------------------------------- 273 * Initialize memory now. Secondary CPU initialization won't get to this 274 * point. 275 * --------------------------------------------------------------------- 276 */ 277 278 .if \_init_memory 279 bl platform_mem_init 280 .endif /* _init_memory */ 281 282 /* --------------------------------------------------------------------- 283 * Init C runtime environment: 284 * - Zero-initialise the NOBITS sections. There are 2 of them: 285 * - the .bss section; 286 * - the coherent memory section (if any). 287 * - Relocate the data section from ROM to RAM, if required. 288 * --------------------------------------------------------------------- 289 */ 290 .if \_init_c_runtime 291#if defined(IMAGE_BL32) || (defined(IMAGE_BL2) && BL2_AT_EL3) 292 /* ----------------------------------------------------------------- 293 * Invalidate the RW memory used by the image. This 294 * includes the data and NOBITS sections. This is done to 295 * safeguard against possible corruption of this memory by 296 * dirty cache lines in a system cache as a result of use by 297 * an earlier boot loader stage. 298 * ----------------------------------------------------------------- 299 */ 300 ldr r0, =__RW_START__ 301 ldr r1, =__RW_END__ 302 sub r1, r1, r0 303 bl inv_dcache_range 304#endif 305 306 ldr r0, =__BSS_START__ 307 ldr r1, =__BSS_SIZE__ 308 bl zeromem 309 310#if USE_COHERENT_MEM 311 ldr r0, =__COHERENT_RAM_START__ 312 ldr r1, =__COHERENT_RAM_UNALIGNED_SIZE__ 313 bl zeromem 314#endif 315 316#ifdef IMAGE_BL1 317 /* ----------------------------------------------------- 318 * Copy data from ROM to RAM. 319 * ----------------------------------------------------- 320 */ 321 ldr r0, =__DATA_RAM_START__ 322 ldr r1, =__DATA_ROM_START__ 323 ldr r2, =__DATA_SIZE__ 324 bl memcpy4 325#endif 326 .endif /* _init_c_runtime */ 327 328 /* --------------------------------------------------------------------- 329 * Allocate a stack whose memory will be marked as Normal-IS-WBWA when 330 * the MMU is enabled. There is no risk of reading stale stack memory 331 * after enabling the MMU as only the primary CPU is running at the 332 * moment. 333 * --------------------------------------------------------------------- 334 */ 335 bl plat_set_my_stack 336 337#if STACK_PROTECTOR_ENABLED 338 .if \_init_c_runtime 339 bl update_stack_protector_canary 340 .endif /* _init_c_runtime */ 341#endif 342 .endm 343 344#endif /* EL3_COMMON_MACROS_S */ 345