1/* 2 * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#ifndef EL3_COMMON_MACROS_S 8#define EL3_COMMON_MACROS_S 9 10#include <arch.h> 11#include <asm_macros.S> 12#include <assert_macros.S> 13 14 /* 15 * Helper macro to initialise EL3 registers we care about. 16 */ 17 .macro el3_arch_init_common 18 /* --------------------------------------------------------------------- 19 * SCTLR has already been initialised - read current value before 20 * modifying. 21 * 22 * SCTLR.I: Enable the instruction cache. 23 * 24 * SCTLR.A: Enable Alignment fault checking. All instructions that load 25 * or store one or more registers have an alignment check that the 26 * address being accessed is aligned to the size of the data element(s) 27 * being accessed. 28 * --------------------------------------------------------------------- 29 */ 30 ldr r1, =(SCTLR_I_BIT | SCTLR_A_BIT) 31 ldcopr r0, SCTLR 32 orr r0, r0, r1 33 stcopr r0, SCTLR 34 isb 35 36 /* --------------------------------------------------------------------- 37 * Initialise SCR, setting all fields rather than relying on the hw. 38 * 39 * SCR.SIF: Enabled so that Secure state instruction fetches from 40 * Non-secure memory are not permitted. 41 * --------------------------------------------------------------------- 42 */ 43 ldr r0, =(SCR_RESET_VAL | SCR_SIF_BIT) 44 stcopr r0, SCR 45 46 /* ----------------------------------------------------- 47 * Enable the Asynchronous data abort now that the 48 * exception vectors have been setup. 49 * ----------------------------------------------------- 50 */ 51 cpsie a 52 isb 53 54 /* --------------------------------------------------------------------- 55 * Initialise NSACR, setting all the fields, except for the 56 * IMPLEMENTATION DEFINED field, rather than relying on the hw. Some 57 * fields are architecturally UNKNOWN on reset. 58 * 59 * NSACR_ENABLE_FP_ACCESS: Represents NSACR.cp11 and NSACR.cp10. The 60 * cp11 field is ignored, but is set to same value as cp10. The cp10 61 * field is set to allow access to Advanced SIMD and floating point 62 * features from both Security states. 63 * --------------------------------------------------------------------- 64 */ 65 ldcopr r0, NSACR 66 and r0, r0, #NSACR_IMP_DEF_MASK 67 orr r0, r0, #(NSACR_RESET_VAL | NSACR_ENABLE_FP_ACCESS) 68 stcopr r0, NSACR 69 isb 70 71 /* --------------------------------------------------------------------- 72 * Initialise CPACR, setting all fields rather than relying on hw. Some 73 * fields are architecturally UNKNOWN on reset. 74 * 75 * CPACR.TRCDIS: Trap control for PL0 and PL1 System register accesses 76 * to trace registers. Set to zero to allow access. 77 * 78 * CPACR_ENABLE_FP_ACCESS: Represents CPACR.cp11 and CPACR.cp10. The 79 * cp11 field is ignored, but is set to same value as cp10. The cp10 80 * field is set to allow full access from PL0 and PL1 to floating-point 81 * and Advanced SIMD features. 82 * --------------------------------------------------------------------- 83 */ 84 ldr r0, =((CPACR_RESET_VAL | CPACR_ENABLE_FP_ACCESS) & ~(TRCDIS_BIT)) 85 stcopr r0, CPACR 86 isb 87 88 /* --------------------------------------------------------------------- 89 * Initialise FPEXC, setting all fields rather than relying on hw. Some 90 * fields are architecturally UNKNOWN on reset and are set to zero 91 * except for field(s) listed below. 92 * 93 * FPEXC.EN: Enable access to Advanced SIMD and floating point features 94 * from all exception levels. 95 * --------------------------------------------------------------------- 96 */ 97 ldr r0, =(FPEXC_RESET_VAL | FPEXC_EN_BIT) 98 vmsr FPEXC, r0 99 isb 100 101#if (ARM_ARCH_MAJOR > 7) 102 /* --------------------------------------------------------------------- 103 * Initialise SDCR, setting all the fields rather than relying on hw. 104 * 105 * SDCR.SPD: Disable AArch32 privileged debug. Debug exceptions from 106 * Secure EL1 are disabled. 107 * 108 * SDCR: Set to one so that cycle counting by PMCCNTR is prohibited in 109 * Secure state. This bit is RES0 in versions of the architecture 110 * earlier than ARMv8.5, setting it to 1 doesn't have any effect on 111 * them. 112 * --------------------------------------------------------------------- 113 */ 114 ldr r0, =(SDCR_RESET_VAL | SDCR_SPD(SDCR_SPD_DISABLE) | SDCR_SCCD_BIT) 115 stcopr r0, SDCR 116#endif 117 118 /* 119 * If Data Independent Timing (DIT) functionality is implemented, 120 * always enable DIT in EL3 121 */ 122 ldcopr r0, ID_PFR0 123 and r0, r0, #(ID_PFR0_DIT_MASK << ID_PFR0_DIT_SHIFT) 124 cmp r0, #ID_PFR0_DIT_SUPPORTED 125 bne 1f 126 mrs r0, cpsr 127 orr r0, r0, #CPSR_DIT_BIT 128 msr cpsr_cxsf, r0 1291: 130 .endm 131 132/* ----------------------------------------------------------------------------- 133 * This is the super set of actions that need to be performed during a cold boot 134 * or a warm boot in EL3. This code is shared by BL1 and BL32 (SP_MIN). 135 * 136 * This macro will always perform reset handling, architectural initialisations 137 * and stack setup. The rest of the actions are optional because they might not 138 * be needed, depending on the context in which this macro is called. This is 139 * why this macro is parameterised ; each parameter allows to enable/disable 140 * some actions. 141 * 142 * _init_sctlr: 143 * Whether the macro needs to initialise the SCTLR register including 144 * configuring the endianness of data accesses. 145 * 146 * _warm_boot_mailbox: 147 * Whether the macro needs to detect the type of boot (cold/warm). The 148 * detection is based on the platform entrypoint address : if it is zero 149 * then it is a cold boot, otherwise it is a warm boot. In the latter case, 150 * this macro jumps on the platform entrypoint address. 151 * 152 * _secondary_cold_boot: 153 * Whether the macro needs to identify the CPU that is calling it: primary 154 * CPU or secondary CPU. The primary CPU will be allowed to carry on with 155 * the platform initialisations, while the secondaries will be put in a 156 * platform-specific state in the meantime. 157 * 158 * If the caller knows this macro will only be called by the primary CPU 159 * then this parameter can be defined to 0 to skip this step. 160 * 161 * _init_memory: 162 * Whether the macro needs to initialise the memory. 163 * 164 * _init_c_runtime: 165 * Whether the macro needs to initialise the C runtime environment. 166 * 167 * _exception_vectors: 168 * Address of the exception vectors to program in the VBAR_EL3 register. 169 * ----------------------------------------------------------------------------- 170 */ 171 .macro el3_entrypoint_common \ 172 _init_sctlr, _warm_boot_mailbox, _secondary_cold_boot, \ 173 _init_memory, _init_c_runtime, _exception_vectors 174 175 /* Make sure we are in Secure Mode */ 176#if ENABLE_ASSERTIONS 177 ldcopr r0, SCR 178 tst r0, #SCR_NS_BIT 179 ASM_ASSERT(eq) 180#endif 181 182 .if \_init_sctlr 183 /* ------------------------------------------------------------- 184 * This is the initialisation of SCTLR and so must ensure that 185 * all fields are explicitly set rather than relying on hw. Some 186 * fields reset to an IMPLEMENTATION DEFINED value. 187 * 188 * SCTLR.TE: Set to zero so that exceptions to an Exception 189 * Level executing at PL1 are taken to A32 state. 190 * 191 * SCTLR.EE: Set the CPU endianness before doing anything that 192 * might involve memory reads or writes. Set to zero to select 193 * Little Endian. 194 * 195 * SCTLR.V: Set to zero to select the normal exception vectors 196 * with base address held in VBAR. 197 * 198 * SCTLR.DSSBS: Set to zero to disable speculation store bypass 199 * safe behaviour upon exception entry to EL3. 200 * ------------------------------------------------------------- 201 */ 202 ldr r0, =(SCTLR_RESET_VAL & ~(SCTLR_TE_BIT | SCTLR_EE_BIT | \ 203 SCTLR_V_BIT | SCTLR_DSSBS_BIT)) 204 stcopr r0, SCTLR 205 isb 206 .endif /* _init_sctlr */ 207 208 /* Switch to monitor mode */ 209 cps #MODE32_mon 210 isb 211 212 .if \_warm_boot_mailbox 213 /* ------------------------------------------------------------- 214 * This code will be executed for both warm and cold resets. 215 * Now is the time to distinguish between the two. 216 * Query the platform entrypoint address and if it is not zero 217 * then it means it is a warm boot so jump to this address. 218 * ------------------------------------------------------------- 219 */ 220 bl plat_get_my_entrypoint 221 cmp r0, #0 222 bxne r0 223 .endif /* _warm_boot_mailbox */ 224 225 /* --------------------------------------------------------------------- 226 * Set the exception vectors (VBAR/MVBAR). 227 * --------------------------------------------------------------------- 228 */ 229 ldr r0, =\_exception_vectors 230 stcopr r0, VBAR 231 stcopr r0, MVBAR 232 isb 233 234 /* --------------------------------------------------------------------- 235 * It is a cold boot. 236 * Perform any processor specific actions upon reset e.g. cache, TLB 237 * invalidations etc. 238 * --------------------------------------------------------------------- 239 */ 240 bl reset_handler 241 242 el3_arch_init_common 243 244 .if \_secondary_cold_boot 245 /* ------------------------------------------------------------- 246 * Check if this is a primary or secondary CPU cold boot. 247 * The primary CPU will set up the platform while the 248 * secondaries are placed in a platform-specific state until the 249 * primary CPU performs the necessary actions to bring them out 250 * of that state and allows entry into the OS. 251 * ------------------------------------------------------------- 252 */ 253 bl plat_is_my_cpu_primary 254 cmp r0, #0 255 bne do_primary_cold_boot 256 257 /* This is a cold boot on a secondary CPU */ 258 bl plat_secondary_cold_boot_setup 259 /* plat_secondary_cold_boot_setup() is not supposed to return */ 260 no_ret plat_panic_handler 261 262 do_primary_cold_boot: 263 .endif /* _secondary_cold_boot */ 264 265 /* --------------------------------------------------------------------- 266 * Initialize memory now. Secondary CPU initialization won't get to this 267 * point. 268 * --------------------------------------------------------------------- 269 */ 270 271 .if \_init_memory 272 bl platform_mem_init 273 .endif /* _init_memory */ 274 275 /* --------------------------------------------------------------------- 276 * Init C runtime environment: 277 * - Zero-initialise the NOBITS sections. There are 2 of them: 278 * - the .bss section; 279 * - the coherent memory section (if any). 280 * - Relocate the data section from ROM to RAM, if required. 281 * --------------------------------------------------------------------- 282 */ 283 .if \_init_c_runtime 284#if defined(IMAGE_BL32) || (defined(IMAGE_BL2) && BL2_AT_EL3) 285 /* ----------------------------------------------------------------- 286 * Invalidate the RW memory used by the image. This 287 * includes the data and NOBITS sections. This is done to 288 * safeguard against possible corruption of this memory by 289 * dirty cache lines in a system cache as a result of use by 290 * an earlier boot loader stage. 291 * ----------------------------------------------------------------- 292 */ 293 ldr r0, =__RW_START__ 294 ldr r1, =__RW_END__ 295 sub r1, r1, r0 296 bl inv_dcache_range 297#endif 298 299 ldr r0, =__BSS_START__ 300 ldr r1, =__BSS_SIZE__ 301 bl zeromem 302 303#if USE_COHERENT_MEM 304 ldr r0, =__COHERENT_RAM_START__ 305 ldr r1, =__COHERENT_RAM_UNALIGNED_SIZE__ 306 bl zeromem 307#endif 308 309#ifdef IMAGE_BL1 310 /* ----------------------------------------------------- 311 * Copy data from ROM to RAM. 312 * ----------------------------------------------------- 313 */ 314 ldr r0, =__DATA_RAM_START__ 315 ldr r1, =__DATA_ROM_START__ 316 ldr r2, =__DATA_SIZE__ 317 bl memcpy4 318#endif 319 .endif /* _init_c_runtime */ 320 321 /* --------------------------------------------------------------------- 322 * Allocate a stack whose memory will be marked as Normal-IS-WBWA when 323 * the MMU is enabled. There is no risk of reading stale stack memory 324 * after enabling the MMU as only the primary CPU is running at the 325 * moment. 326 * --------------------------------------------------------------------- 327 */ 328 bl plat_set_my_stack 329 330#if STACK_PROTECTOR_ENABLED 331 .if \_init_c_runtime 332 bl update_stack_protector_canary 333 .endif /* _init_c_runtime */ 334#endif 335 .endm 336 337#endif /* EL3_COMMON_MACROS_S */ 338