1/* 2 * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#ifndef EL3_COMMON_MACROS_S 8#define EL3_COMMON_MACROS_S 9 10#include <arch.h> 11#include <asm_macros.S> 12#include <assert_macros.S> 13 14 /* 15 * Helper macro to initialise EL3 registers we care about. 16 */ 17 .macro el3_arch_init_common 18 /* --------------------------------------------------------------------- 19 * SCTLR has already been initialised - read current value before 20 * modifying. 21 * 22 * SCTLR.I: Enable the instruction cache. 23 * 24 * SCTLR.A: Enable Alignment fault checking. All instructions that load 25 * or store one or more registers have an alignment check that the 26 * address being accessed is aligned to the size of the data element(s) 27 * being accessed. 28 * --------------------------------------------------------------------- 29 */ 30 ldr r1, =(SCTLR_I_BIT | SCTLR_A_BIT) 31 ldcopr r0, SCTLR 32 orr r0, r0, r1 33 stcopr r0, SCTLR 34 isb 35 36 /* --------------------------------------------------------------------- 37 * Initialise SCR, setting all fields rather than relying on the hw. 38 * 39 * SCR.SIF: Enabled so that Secure state instruction fetches from 40 * Non-secure memory are not permitted. 41 * --------------------------------------------------------------------- 42 */ 43 ldr r0, =(SCR_RESET_VAL | SCR_SIF_BIT) 44 stcopr r0, SCR 45 46 /* ----------------------------------------------------- 47 * Enable the Asynchronous data abort now that the 48 * exception vectors have been setup. 49 * ----------------------------------------------------- 50 */ 51 cpsie a 52 isb 53 54 /* --------------------------------------------------------------------- 55 * Initialise NSACR, setting all the fields, except for the 56 * IMPLEMENTATION DEFINED field, rather than relying on the hw. Some 57 * fields are architecturally UNKNOWN on reset. 58 * 59 * NSACR_ENABLE_FP_ACCESS: Represents NSACR.cp11 and NSACR.cp10. The 60 * cp11 field is ignored, but is set to same value as cp10. The cp10 61 * field is set to allow access to Advanced SIMD and floating point 62 * features from both Security states. 63 * --------------------------------------------------------------------- 64 */ 65 ldcopr r0, NSACR 66 and r0, r0, #NSACR_IMP_DEF_MASK 67 orr r0, r0, #(NSACR_RESET_VAL | NSACR_ENABLE_FP_ACCESS) 68 stcopr r0, NSACR 69 isb 70 71 /* --------------------------------------------------------------------- 72 * Initialise CPACR, setting all fields rather than relying on hw. Some 73 * fields are architecturally UNKNOWN on reset. 74 * 75 * CPACR.TRCDIS: Trap control for PL0 and PL1 System register accesses 76 * to trace registers. Set to zero to allow access. 77 * 78 * CPACR_ENABLE_FP_ACCESS: Represents CPACR.cp11 and CPACR.cp10. The 79 * cp11 field is ignored, but is set to same value as cp10. The cp10 80 * field is set to allow full access from PL0 and PL1 to floating-point 81 * and Advanced SIMD features. 82 * --------------------------------------------------------------------- 83 */ 84 ldr r0, =((CPACR_RESET_VAL | CPACR_ENABLE_FP_ACCESS) & ~(TRCDIS_BIT)) 85 stcopr r0, CPACR 86 isb 87 88 /* --------------------------------------------------------------------- 89 * Initialise FPEXC, setting all fields rather than relying on hw. Some 90 * fields are architecturally UNKNOWN on reset and are set to zero 91 * except for field(s) listed below. 92 * 93 * FPEXC.EN: Enable access to Advanced SIMD and floating point features 94 * from all exception levels. 95 * --------------------------------------------------------------------- 96 */ 97 ldr r0, =(FPEXC_RESET_VAL | FPEXC_EN_BIT) 98 vmsr FPEXC, r0 99 isb 100 101#if (ARM_ARCH_MAJOR > 7) 102 /* --------------------------------------------------------------------- 103 * Initialise SDCR, setting all the fields rather than relying on hw. 104 * 105 * SDCR.SPD: Disable AArch32 privileged debug. Debug exceptions from 106 * Secure EL1 are disabled. 107 * --------------------------------------------------------------------- 108 */ 109 ldr r0, =(SDCR_RESET_VAL | SDCR_SPD(SDCR_SPD_DISABLE)) 110 stcopr r0, SDCR 111#endif 112 113 /* 114 * If Data Independent Timing (DIT) functionality is implemented, 115 * always enable DIT in EL3 116 */ 117 ldcopr r0, ID_PFR0 118 and r0, r0, #(ID_PFR0_DIT_MASK << ID_PFR0_DIT_SHIFT) 119 cmp r0, #ID_PFR0_DIT_SUPPORTED 120 bne 1f 121 mrs r0, cpsr 122 orr r0, r0, #CPSR_DIT_BIT 123 msr cpsr_cxsf, r0 1241: 125 .endm 126 127/* ----------------------------------------------------------------------------- 128 * This is the super set of actions that need to be performed during a cold boot 129 * or a warm boot in EL3. This code is shared by BL1 and BL32 (SP_MIN). 130 * 131 * This macro will always perform reset handling, architectural initialisations 132 * and stack setup. The rest of the actions are optional because they might not 133 * be needed, depending on the context in which this macro is called. This is 134 * why this macro is parameterised ; each parameter allows to enable/disable 135 * some actions. 136 * 137 * _init_sctlr: 138 * Whether the macro needs to initialise the SCTLR register including 139 * configuring the endianness of data accesses. 140 * 141 * _warm_boot_mailbox: 142 * Whether the macro needs to detect the type of boot (cold/warm). The 143 * detection is based on the platform entrypoint address : if it is zero 144 * then it is a cold boot, otherwise it is a warm boot. In the latter case, 145 * this macro jumps on the platform entrypoint address. 146 * 147 * _secondary_cold_boot: 148 * Whether the macro needs to identify the CPU that is calling it: primary 149 * CPU or secondary CPU. The primary CPU will be allowed to carry on with 150 * the platform initialisations, while the secondaries will be put in a 151 * platform-specific state in the meantime. 152 * 153 * If the caller knows this macro will only be called by the primary CPU 154 * then this parameter can be defined to 0 to skip this step. 155 * 156 * _init_memory: 157 * Whether the macro needs to initialise the memory. 158 * 159 * _init_c_runtime: 160 * Whether the macro needs to initialise the C runtime environment. 161 * 162 * _exception_vectors: 163 * Address of the exception vectors to program in the VBAR_EL3 register. 164 * ----------------------------------------------------------------------------- 165 */ 166 .macro el3_entrypoint_common \ 167 _init_sctlr, _warm_boot_mailbox, _secondary_cold_boot, \ 168 _init_memory, _init_c_runtime, _exception_vectors 169 170 /* Make sure we are in Secure Mode */ 171#if ENABLE_ASSERTIONS 172 ldcopr r0, SCR 173 tst r0, #SCR_NS_BIT 174 ASM_ASSERT(eq) 175#endif 176 177 .if \_init_sctlr 178 /* ------------------------------------------------------------- 179 * This is the initialisation of SCTLR and so must ensure that 180 * all fields are explicitly set rather than relying on hw. Some 181 * fields reset to an IMPLEMENTATION DEFINED value. 182 * 183 * SCTLR.TE: Set to zero so that exceptions to an Exception 184 * Level executing at PL1 are taken to A32 state. 185 * 186 * SCTLR.EE: Set the CPU endianness before doing anything that 187 * might involve memory reads or writes. Set to zero to select 188 * Little Endian. 189 * 190 * SCTLR.V: Set to zero to select the normal exception vectors 191 * with base address held in VBAR. 192 * 193 * SCTLR.DSSBS: Set to zero to disable speculation store bypass 194 * safe behaviour upon exception entry to EL3. 195 * ------------------------------------------------------------- 196 */ 197 ldr r0, =(SCTLR_RESET_VAL & ~(SCTLR_TE_BIT | SCTLR_EE_BIT | \ 198 SCTLR_V_BIT | SCTLR_DSSBS_BIT)) 199 stcopr r0, SCTLR 200 isb 201 .endif /* _init_sctlr */ 202 203 /* Switch to monitor mode */ 204 cps #MODE32_mon 205 isb 206 207 .if \_warm_boot_mailbox 208 /* ------------------------------------------------------------- 209 * This code will be executed for both warm and cold resets. 210 * Now is the time to distinguish between the two. 211 * Query the platform entrypoint address and if it is not zero 212 * then it means it is a warm boot so jump to this address. 213 * ------------------------------------------------------------- 214 */ 215 bl plat_get_my_entrypoint 216 cmp r0, #0 217 bxne r0 218 .endif /* _warm_boot_mailbox */ 219 220 /* --------------------------------------------------------------------- 221 * Set the exception vectors (VBAR/MVBAR). 222 * --------------------------------------------------------------------- 223 */ 224 ldr r0, =\_exception_vectors 225 stcopr r0, VBAR 226 stcopr r0, MVBAR 227 isb 228 229 /* --------------------------------------------------------------------- 230 * It is a cold boot. 231 * Perform any processor specific actions upon reset e.g. cache, TLB 232 * invalidations etc. 233 * --------------------------------------------------------------------- 234 */ 235 bl reset_handler 236 237 el3_arch_init_common 238 239 .if \_secondary_cold_boot 240 /* ------------------------------------------------------------- 241 * Check if this is a primary or secondary CPU cold boot. 242 * The primary CPU will set up the platform while the 243 * secondaries are placed in a platform-specific state until the 244 * primary CPU performs the necessary actions to bring them out 245 * of that state and allows entry into the OS. 246 * ------------------------------------------------------------- 247 */ 248 bl plat_is_my_cpu_primary 249 cmp r0, #0 250 bne do_primary_cold_boot 251 252 /* This is a cold boot on a secondary CPU */ 253 bl plat_secondary_cold_boot_setup 254 /* plat_secondary_cold_boot_setup() is not supposed to return */ 255 no_ret plat_panic_handler 256 257 do_primary_cold_boot: 258 .endif /* _secondary_cold_boot */ 259 260 /* --------------------------------------------------------------------- 261 * Initialize memory now. Secondary CPU initialization won't get to this 262 * point. 263 * --------------------------------------------------------------------- 264 */ 265 266 .if \_init_memory 267 bl platform_mem_init 268 .endif /* _init_memory */ 269 270 /* --------------------------------------------------------------------- 271 * Init C runtime environment: 272 * - Zero-initialise the NOBITS sections. There are 2 of them: 273 * - the .bss section; 274 * - the coherent memory section (if any). 275 * - Relocate the data section from ROM to RAM, if required. 276 * --------------------------------------------------------------------- 277 */ 278 .if \_init_c_runtime 279#if defined(IMAGE_BL32) || (defined(IMAGE_BL2) && BL2_AT_EL3) 280 /* ----------------------------------------------------------------- 281 * Invalidate the RW memory used by the image. This 282 * includes the data and NOBITS sections. This is done to 283 * safeguard against possible corruption of this memory by 284 * dirty cache lines in a system cache as a result of use by 285 * an earlier boot loader stage. 286 * ----------------------------------------------------------------- 287 */ 288 ldr r0, =__RW_START__ 289 ldr r1, =__RW_END__ 290 sub r1, r1, r0 291 bl inv_dcache_range 292#endif 293 294 ldr r0, =__BSS_START__ 295 ldr r1, =__BSS_SIZE__ 296 bl zeromem 297 298#if USE_COHERENT_MEM 299 ldr r0, =__COHERENT_RAM_START__ 300 ldr r1, =__COHERENT_RAM_UNALIGNED_SIZE__ 301 bl zeromem 302#endif 303 304#ifdef IMAGE_BL1 305 /* ----------------------------------------------------- 306 * Copy data from ROM to RAM. 307 * ----------------------------------------------------- 308 */ 309 ldr r0, =__DATA_RAM_START__ 310 ldr r1, =__DATA_ROM_START__ 311 ldr r2, =__DATA_SIZE__ 312 bl memcpy4 313#endif 314 .endif /* _init_c_runtime */ 315 316 /* --------------------------------------------------------------------- 317 * Allocate a stack whose memory will be marked as Normal-IS-WBWA when 318 * the MMU is enabled. There is no risk of reading stale stack memory 319 * after enabling the MMU as only the primary CPU is running at the 320 * moment. 321 * --------------------------------------------------------------------- 322 */ 323 bl plat_set_my_stack 324 325#if STACK_PROTECTOR_ENABLED 326 .if \_init_c_runtime 327 bl update_stack_protector_canary 328 .endif /* _init_c_runtime */ 329#endif 330 .endm 331 332#endif /* EL3_COMMON_MACROS_S */ 333