1/* 2 * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#ifndef EL3_COMMON_MACROS_S 8#define EL3_COMMON_MACROS_S 9 10#include <arch.h> 11#include <asm_macros.S> 12#include <assert_macros.S> 13 14 /* 15 * Helper macro to initialise EL3 registers we care about. 16 */ 17 .macro el3_arch_init_common 18 /* --------------------------------------------------------------------- 19 * SCTLR has already been initialised - read current value before 20 * modifying. 21 * 22 * SCTLR.I: Enable the instruction cache. 23 * 24 * SCTLR.A: Enable Alignment fault checking. All instructions that load 25 * or store one or more registers have an alignment check that the 26 * address being accessed is aligned to the size of the data element(s) 27 * being accessed. 28 * --------------------------------------------------------------------- 29 */ 30 ldr r1, =(SCTLR_I_BIT | SCTLR_A_BIT) 31 ldcopr r0, SCTLR 32 orr r0, r0, r1 33 stcopr r0, SCTLR 34 isb 35 36 /* --------------------------------------------------------------------- 37 * Initialise SCR, setting all fields rather than relying on the hw. 38 * 39 * SCR.SIF: Enabled so that Secure state instruction fetches from 40 * Non-secure memory are not permitted. 41 * --------------------------------------------------------------------- 42 */ 43 ldr r0, =(SCR_RESET_VAL | SCR_SIF_BIT) 44 stcopr r0, SCR 45 46 /* ----------------------------------------------------- 47 * Enable the Asynchronous data abort now that the 48 * exception vectors have been setup. 49 * ----------------------------------------------------- 50 */ 51 cpsie a 52 isb 53 54 /* --------------------------------------------------------------------- 55 * Initialise NSACR, setting all the fields, except for the 56 * IMPLEMENTATION DEFINED field, rather than relying on the hw. Some 57 * fields are architecturally UNKNOWN on reset. 58 * 59 * NSACR_ENABLE_FP_ACCESS: Represents NSACR.cp11 and NSACR.cp10. The 60 * cp11 field is ignored, but is set to same value as cp10. The cp10 61 * field is set to allow access to Advanced SIMD and floating point 62 * features from both Security states. 63 * --------------------------------------------------------------------- 64 */ 65 ldcopr r0, NSACR 66 and r0, r0, #NSACR_IMP_DEF_MASK 67 orr r0, r0, #(NSACR_RESET_VAL | NSACR_ENABLE_FP_ACCESS) 68 stcopr r0, NSACR 69 isb 70 71 /* --------------------------------------------------------------------- 72 * Initialise CPACR, setting all fields rather than relying on hw. Some 73 * fields are architecturally UNKNOWN on reset. 74 * 75 * CPACR.TRCDIS: Trap control for PL0 and PL1 System register accesses 76 * to trace registers. Set to zero to allow access. 77 * 78 * CPACR_ENABLE_FP_ACCESS: Represents CPACR.cp11 and CPACR.cp10. The 79 * cp11 field is ignored, but is set to same value as cp10. The cp10 80 * field is set to allow full access from PL0 and PL1 to floating-point 81 * and Advanced SIMD features. 82 * --------------------------------------------------------------------- 83 */ 84 ldr r0, =((CPACR_RESET_VAL | CPACR_ENABLE_FP_ACCESS) & ~(TRCDIS_BIT)) 85 stcopr r0, CPACR 86 isb 87 88 /* --------------------------------------------------------------------- 89 * Initialise FPEXC, setting all fields rather than relying on hw. Some 90 * fields are architecturally UNKNOWN on reset and are set to zero 91 * except for field(s) listed below. 92 * 93 * FPEXC.EN: Enable access to Advanced SIMD and floating point features 94 * from all exception levels. 95 * --------------------------------------------------------------------- 96 */ 97#if (ARM_ARCH_MAJOR > 7) || defined(ARMV7_SUPPORTS_VFP) 98 ldr r0, =(FPEXC_RESET_VAL | FPEXC_EN_BIT) 99 vmsr FPEXC, r0 100 isb 101#endif 102 103#if (ARM_ARCH_MAJOR > 7) 104 /* --------------------------------------------------------------------- 105 * Initialise SDCR, setting all the fields rather than relying on hw. 106 * 107 * SDCR.SPD: Disable AArch32 privileged debug. Debug exceptions from 108 * Secure EL1 are disabled. 109 * --------------------------------------------------------------------- 110 */ 111 ldr r0, =(SDCR_RESET_VAL | SDCR_SPD(SDCR_SPD_DISABLE)) 112 stcopr r0, SDCR 113#endif 114 115 /* 116 * If Data Independent Timing (DIT) functionality is implemented, 117 * always enable DIT in EL3 118 */ 119 ldcopr r0, ID_PFR0 120 and r0, r0, #(ID_PFR0_DIT_MASK << ID_PFR0_DIT_SHIFT) 121 cmp r0, #ID_PFR0_DIT_SUPPORTED 122 bne 1f 123 mrs r0, cpsr 124 orr r0, r0, #CPSR_DIT_BIT 125 msr cpsr_cxsf, r0 1261: 127 .endm 128 129/* ----------------------------------------------------------------------------- 130 * This is the super set of actions that need to be performed during a cold boot 131 * or a warm boot in EL3. This code is shared by BL1 and BL32 (SP_MIN). 132 * 133 * This macro will always perform reset handling, architectural initialisations 134 * and stack setup. The rest of the actions are optional because they might not 135 * be needed, depending on the context in which this macro is called. This is 136 * why this macro is parameterised ; each parameter allows to enable/disable 137 * some actions. 138 * 139 * _init_sctlr: 140 * Whether the macro needs to initialise the SCTLR register including 141 * configuring the endianness of data accesses. 142 * 143 * _warm_boot_mailbox: 144 * Whether the macro needs to detect the type of boot (cold/warm). The 145 * detection is based on the platform entrypoint address : if it is zero 146 * then it is a cold boot, otherwise it is a warm boot. In the latter case, 147 * this macro jumps on the platform entrypoint address. 148 * 149 * _secondary_cold_boot: 150 * Whether the macro needs to identify the CPU that is calling it: primary 151 * CPU or secondary CPU. The primary CPU will be allowed to carry on with 152 * the platform initialisations, while the secondaries will be put in a 153 * platform-specific state in the meantime. 154 * 155 * If the caller knows this macro will only be called by the primary CPU 156 * then this parameter can be defined to 0 to skip this step. 157 * 158 * _init_memory: 159 * Whether the macro needs to initialise the memory. 160 * 161 * _init_c_runtime: 162 * Whether the macro needs to initialise the C runtime environment. 163 * 164 * _exception_vectors: 165 * Address of the exception vectors to program in the VBAR_EL3 register. 166 * ----------------------------------------------------------------------------- 167 */ 168 .macro el3_entrypoint_common \ 169 _init_sctlr, _warm_boot_mailbox, _secondary_cold_boot, \ 170 _init_memory, _init_c_runtime, _exception_vectors 171 172 /* Make sure we are in Secure Mode */ 173#if ENABLE_ASSERTIONS 174 ldcopr r0, SCR 175 tst r0, #SCR_NS_BIT 176 ASM_ASSERT(eq) 177#endif 178 179 .if \_init_sctlr 180 /* ------------------------------------------------------------- 181 * This is the initialisation of SCTLR and so must ensure that 182 * all fields are explicitly set rather than relying on hw. Some 183 * fields reset to an IMPLEMENTATION DEFINED value. 184 * 185 * SCTLR.TE: Set to zero so that exceptions to an Exception 186 * Level executing at PL1 are taken to A32 state. 187 * 188 * SCTLR.EE: Set the CPU endianness before doing anything that 189 * might involve memory reads or writes. Set to zero to select 190 * Little Endian. 191 * 192 * SCTLR.V: Set to zero to select the normal exception vectors 193 * with base address held in VBAR. 194 * 195 * SCTLR.DSSBS: Set to zero to disable speculation store bypass 196 * safe behaviour upon exception entry to EL3. 197 * ------------------------------------------------------------- 198 */ 199 ldr r0, =(SCTLR_RESET_VAL & ~(SCTLR_TE_BIT | SCTLR_EE_BIT | \ 200 SCTLR_V_BIT | SCTLR_DSSBS_BIT)) 201 stcopr r0, SCTLR 202 isb 203 .endif /* _init_sctlr */ 204 205 /* Switch to monitor mode */ 206 cps #MODE32_mon 207 isb 208 209 .if \_warm_boot_mailbox 210 /* ------------------------------------------------------------- 211 * This code will be executed for both warm and cold resets. 212 * Now is the time to distinguish between the two. 213 * Query the platform entrypoint address and if it is not zero 214 * then it means it is a warm boot so jump to this address. 215 * ------------------------------------------------------------- 216 */ 217 bl plat_get_my_entrypoint 218 cmp r0, #0 219 bxne r0 220 .endif /* _warm_boot_mailbox */ 221 222 /* --------------------------------------------------------------------- 223 * Set the exception vectors (VBAR/MVBAR). 224 * --------------------------------------------------------------------- 225 */ 226 ldr r0, =\_exception_vectors 227 stcopr r0, VBAR 228 stcopr r0, MVBAR 229 isb 230 231 /* --------------------------------------------------------------------- 232 * It is a cold boot. 233 * Perform any processor specific actions upon reset e.g. cache, TLB 234 * invalidations etc. 235 * --------------------------------------------------------------------- 236 */ 237 bl reset_handler 238 239 el3_arch_init_common 240 241 .if \_secondary_cold_boot 242 /* ------------------------------------------------------------- 243 * Check if this is a primary or secondary CPU cold boot. 244 * The primary CPU will set up the platform while the 245 * secondaries are placed in a platform-specific state until the 246 * primary CPU performs the necessary actions to bring them out 247 * of that state and allows entry into the OS. 248 * ------------------------------------------------------------- 249 */ 250 bl plat_is_my_cpu_primary 251 cmp r0, #0 252 bne do_primary_cold_boot 253 254 /* This is a cold boot on a secondary CPU */ 255 bl plat_secondary_cold_boot_setup 256 /* plat_secondary_cold_boot_setup() is not supposed to return */ 257 no_ret plat_panic_handler 258 259 do_primary_cold_boot: 260 .endif /* _secondary_cold_boot */ 261 262 /* --------------------------------------------------------------------- 263 * Initialize memory now. Secondary CPU initialization won't get to this 264 * point. 265 * --------------------------------------------------------------------- 266 */ 267 268 .if \_init_memory 269 bl platform_mem_init 270 .endif /* _init_memory */ 271 272 /* --------------------------------------------------------------------- 273 * Init C runtime environment: 274 * - Zero-initialise the NOBITS sections. There are 2 of them: 275 * - the .bss section; 276 * - the coherent memory section (if any). 277 * - Relocate the data section from ROM to RAM, if required. 278 * --------------------------------------------------------------------- 279 */ 280 .if \_init_c_runtime 281#if defined(IMAGE_BL32) || (defined(IMAGE_BL2) && BL2_AT_EL3) 282 /* ----------------------------------------------------------------- 283 * Invalidate the RW memory used by the image. This 284 * includes the data and NOBITS sections. This is done to 285 * safeguard against possible corruption of this memory by 286 * dirty cache lines in a system cache as a result of use by 287 * an earlier boot loader stage. 288 * ----------------------------------------------------------------- 289 */ 290 ldr r0, =__RW_START__ 291 ldr r1, =__RW_END__ 292 sub r1, r1, r0 293 bl inv_dcache_range 294#endif 295 296 ldr r0, =__BSS_START__ 297 ldr r1, =__BSS_SIZE__ 298 bl zeromem 299 300#if USE_COHERENT_MEM 301 ldr r0, =__COHERENT_RAM_START__ 302 ldr r1, =__COHERENT_RAM_UNALIGNED_SIZE__ 303 bl zeromem 304#endif 305 306#ifdef IMAGE_BL1 307 /* ----------------------------------------------------- 308 * Copy data from ROM to RAM. 309 * ----------------------------------------------------- 310 */ 311 ldr r0, =__DATA_RAM_START__ 312 ldr r1, =__DATA_ROM_START__ 313 ldr r2, =__DATA_SIZE__ 314 bl memcpy4 315#endif 316 .endif /* _init_c_runtime */ 317 318 /* --------------------------------------------------------------------- 319 * Allocate a stack whose memory will be marked as Normal-IS-WBWA when 320 * the MMU is enabled. There is no risk of reading stale stack memory 321 * after enabling the MMU as only the primary CPU is running at the 322 * moment. 323 * --------------------------------------------------------------------- 324 */ 325 bl plat_set_my_stack 326 327#if STACK_PROTECTOR_ENABLED 328 .if \_init_c_runtime 329 bl update_stack_protector_canary 330 .endif /* _init_c_runtime */ 331#endif 332 .endm 333 334#endif /* EL3_COMMON_MACROS_S */ 335