1 /* 2 * Copyright (c) 2016-2023, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef ARCH_H 8 #define ARCH_H 9 10 #include <lib/utils_def.h> 11 12 /******************************************************************************* 13 * MIDR bit definitions 14 ******************************************************************************/ 15 #define MIDR_IMPL_MASK U(0xff) 16 #define MIDR_IMPL_SHIFT U(24) 17 #define MIDR_VAR_SHIFT U(20) 18 #define MIDR_VAR_BITS U(4) 19 #define MIDR_VAR_MASK U(0xf) 20 #define MIDR_REV_SHIFT U(0) 21 #define MIDR_REV_BITS U(4) 22 #define MIDR_REV_MASK U(0xf) 23 #define MIDR_PN_MASK U(0xfff) 24 #define MIDR_PN_SHIFT U(4) 25 26 /******************************************************************************* 27 * MPIDR macros 28 ******************************************************************************/ 29 #define MPIDR_MT_MASK (U(1) << 24) 30 #define MPIDR_CPU_MASK MPIDR_AFFLVL_MASK 31 #define MPIDR_CLUSTER_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS) 32 #define MPIDR_AFFINITY_BITS U(8) 33 #define MPIDR_AFFLVL_MASK U(0xff) 34 #define MPIDR_AFFLVL_SHIFT U(3) 35 #define MPIDR_AFF0_SHIFT U(0) 36 #define MPIDR_AFF1_SHIFT U(8) 37 #define MPIDR_AFF2_SHIFT U(16) 38 #define MPIDR_AFF_SHIFT(_n) MPIDR_AFF##_n##_SHIFT 39 #define MPIDR_AFFINITY_MASK U(0x00ffffff) 40 #define MPIDR_AFFLVL0 U(0) 41 #define MPIDR_AFFLVL1 U(1) 42 #define MPIDR_AFFLVL2 U(2) 43 #define MPIDR_AFFLVL(_n) MPIDR_AFFLVL##_n 44 45 #define MPIDR_AFFLVL0_VAL(mpidr) \ 46 (((mpidr) >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK) 47 #define MPIDR_AFFLVL1_VAL(mpidr) \ 48 (((mpidr) >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK) 49 #define MPIDR_AFFLVL2_VAL(mpidr) \ 50 (((mpidr) >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK) 51 #define MPIDR_AFFLVL3_VAL(mpidr) U(0) 52 53 #define MPIDR_AFF_ID(mpid, n) \ 54 (((mpid) >> MPIDR_AFF_SHIFT(n)) & MPIDR_AFFLVL_MASK) 55 56 #define MPID_MASK (MPIDR_MT_MASK |\ 57 (MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT)|\ 58 (MPIDR_AFFLVL_MASK << MPIDR_AFF1_SHIFT)|\ 59 (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT)) 60 61 /* 62 * An invalid MPID. This value can be used by functions that return an MPID to 63 * indicate an error. 64 */ 65 #define INVALID_MPID U(0xFFFFFFFF) 66 67 /* 68 * The MPIDR_MAX_AFFLVL count starts from 0. Take care to 69 * add one while using this macro to define array sizes. 70 */ 71 #define MPIDR_MAX_AFFLVL U(2) 72 73 /* Data Cache set/way op type defines */ 74 #define DC_OP_ISW U(0x0) 75 #define DC_OP_CISW U(0x1) 76 #if ERRATA_A53_827319 77 #define DC_OP_CSW DC_OP_CISW 78 #else 79 #define DC_OP_CSW U(0x2) 80 #endif 81 82 /******************************************************************************* 83 * Generic timer memory mapped registers & offsets 84 ******************************************************************************/ 85 #define CNTCR_OFF U(0x000) 86 /* Counter Count Value Lower register */ 87 #define CNTCVL_OFF U(0x008) 88 /* Counter Count Value Upper register */ 89 #define CNTCVU_OFF U(0x00C) 90 #define CNTFID_OFF U(0x020) 91 92 #define CNTCR_EN (U(1) << 0) 93 #define CNTCR_HDBG (U(1) << 1) 94 #define CNTCR_FCREQ(x) ((x) << 8) 95 96 /******************************************************************************* 97 * System register bit definitions 98 ******************************************************************************/ 99 /* CLIDR definitions */ 100 #define LOUIS_SHIFT U(21) 101 #define LOC_SHIFT U(24) 102 #define CLIDR_FIELD_WIDTH U(3) 103 104 /* CSSELR definitions */ 105 #define LEVEL_SHIFT U(1) 106 107 /* ID_DFR0_EL1 definitions */ 108 #define ID_DFR0_COPTRC_SHIFT U(12) 109 #define ID_DFR0_COPTRC_MASK U(0xf) 110 #define ID_DFR0_COPTRC_SUPPORTED U(1) 111 #define ID_DFR0_COPTRC_LENGTH U(4) 112 #define ID_DFR0_TRACEFILT_SHIFT U(28) 113 #define ID_DFR0_TRACEFILT_MASK U(0xf) 114 #define ID_DFR0_TRACEFILT_SUPPORTED U(1) 115 #define ID_DFR0_TRACEFILT_LENGTH U(4) 116 117 /* ID_DFR1_EL1 definitions */ 118 #define ID_DFR1_MTPMU_SHIFT U(0) 119 #define ID_DFR1_MTPMU_MASK U(0xf) 120 #define ID_DFR1_MTPMU_SUPPORTED U(1) 121 122 /* ID_MMFR3 definitions */ 123 #define ID_MMFR3_PAN_SHIFT U(16) 124 #define ID_MMFR3_PAN_MASK U(0xf) 125 126 /* ID_MMFR4 definitions */ 127 #define ID_MMFR4_CNP_SHIFT U(12) 128 #define ID_MMFR4_CNP_LENGTH U(4) 129 #define ID_MMFR4_CNP_MASK U(0xf) 130 131 #define ID_MMFR4_CCIDX_SHIFT U(24) 132 #define ID_MMFR4_CCIDX_LENGTH U(4) 133 #define ID_MMFR4_CCIDX_MASK U(0xf) 134 135 /* ID_PFR0 definitions */ 136 #define ID_PFR0_AMU_SHIFT U(20) 137 #define ID_PFR0_AMU_LENGTH U(4) 138 #define ID_PFR0_AMU_MASK U(0xf) 139 #define ID_PFR0_AMU_NOT_SUPPORTED U(0x0) 140 #define ID_PFR0_AMU_V1 U(0x1) 141 #define ID_PFR0_AMU_V1P1 U(0x2) 142 143 #define ID_PFR0_DIT_SHIFT U(24) 144 #define ID_PFR0_DIT_LENGTH U(4) 145 #define ID_PFR0_DIT_MASK U(0xf) 146 #define ID_PFR0_DIT_SUPPORTED (U(1) << ID_PFR0_DIT_SHIFT) 147 148 /* ID_PFR1 definitions */ 149 #define ID_PFR1_VIRTEXT_SHIFT U(12) 150 #define ID_PFR1_VIRTEXT_MASK U(0xf) 151 #define GET_VIRT_EXT(id) (((id) >> ID_PFR1_VIRTEXT_SHIFT) \ 152 & ID_PFR1_VIRTEXT_MASK) 153 #define ID_PFR1_GENTIMER_SHIFT U(16) 154 #define ID_PFR1_GENTIMER_MASK U(0xf) 155 #define ID_PFR1_GIC_SHIFT U(28) 156 #define ID_PFR1_GIC_MASK U(0xf) 157 #define ID_PFR1_SEC_SHIFT U(4) 158 #define ID_PFR1_SEC_MASK U(0xf) 159 #define ID_PFR1_ELx_ENABLED U(1) 160 161 /* SCTLR definitions */ 162 #define SCTLR_RES1_DEF ((U(1) << 23) | (U(1) << 22) | (U(1) << 4) | \ 163 (U(1) << 3)) 164 #if ARM_ARCH_MAJOR == 7 165 #define SCTLR_RES1 SCTLR_RES1_DEF 166 #else 167 #define SCTLR_RES1 (SCTLR_RES1_DEF | (U(1) << 11)) 168 #endif 169 #define SCTLR_M_BIT (U(1) << 0) 170 #define SCTLR_A_BIT (U(1) << 1) 171 #define SCTLR_C_BIT (U(1) << 2) 172 #define SCTLR_CP15BEN_BIT (U(1) << 5) 173 #define SCTLR_ITD_BIT (U(1) << 7) 174 #define SCTLR_Z_BIT (U(1) << 11) 175 #define SCTLR_I_BIT (U(1) << 12) 176 #define SCTLR_V_BIT (U(1) << 13) 177 #define SCTLR_RR_BIT (U(1) << 14) 178 #define SCTLR_NTWI_BIT (U(1) << 16) 179 #define SCTLR_NTWE_BIT (U(1) << 18) 180 #define SCTLR_WXN_BIT (U(1) << 19) 181 #define SCTLR_UWXN_BIT (U(1) << 20) 182 #define SCTLR_EE_BIT (U(1) << 25) 183 #define SCTLR_TRE_BIT (U(1) << 28) 184 #define SCTLR_AFE_BIT (U(1) << 29) 185 #define SCTLR_TE_BIT (U(1) << 30) 186 #define SCTLR_DSSBS_BIT (U(1) << 31) 187 #define SCTLR_RESET_VAL (SCTLR_RES1 | SCTLR_NTWE_BIT | \ 188 SCTLR_NTWI_BIT | SCTLR_CP15BEN_BIT) 189 190 /* SDCR definitions */ 191 #define SDCR_SPD(x) ((x) << 14) 192 #define SDCR_SPD_LEGACY U(0x0) 193 #define SDCR_SPD_DISABLE U(0x2) 194 #define SDCR_SPD_ENABLE U(0x3) 195 #define SDCR_SCCD_BIT (U(1) << 23) 196 #define SDCR_TTRF_BIT (U(1) << 19) 197 #define SDCR_SPME_BIT (U(1) << 17) 198 #define SDCR_RESET_VAL U(0x0) 199 #define SDCR_MTPME_BIT (U(1) << 28) 200 201 /* HSCTLR definitions */ 202 #define HSCTLR_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ 203 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \ 204 (U(1) << 11) | (U(1) << 4) | (U(1) << 3)) 205 206 #define HSCTLR_M_BIT (U(1) << 0) 207 #define HSCTLR_A_BIT (U(1) << 1) 208 #define HSCTLR_C_BIT (U(1) << 2) 209 #define HSCTLR_CP15BEN_BIT (U(1) << 5) 210 #define HSCTLR_ITD_BIT (U(1) << 7) 211 #define HSCTLR_SED_BIT (U(1) << 8) 212 #define HSCTLR_I_BIT (U(1) << 12) 213 #define HSCTLR_WXN_BIT (U(1) << 19) 214 #define HSCTLR_EE_BIT (U(1) << 25) 215 #define HSCTLR_TE_BIT (U(1) << 30) 216 217 /* CPACR definitions */ 218 #define CPACR_FPEN(x) ((x) << 20) 219 #define CPACR_FP_TRAP_PL0 UL(0x1) 220 #define CPACR_FP_TRAP_ALL UL(0x2) 221 #define CPACR_FP_TRAP_NONE UL(0x3) 222 223 /* SCR definitions */ 224 #define SCR_TWE_BIT (UL(1) << 13) 225 #define SCR_TWI_BIT (UL(1) << 12) 226 #define SCR_SIF_BIT (UL(1) << 9) 227 #define SCR_HCE_BIT (UL(1) << 8) 228 #define SCR_SCD_BIT (UL(1) << 7) 229 #define SCR_NET_BIT (UL(1) << 6) 230 #define SCR_AW_BIT (UL(1) << 5) 231 #define SCR_FW_BIT (UL(1) << 4) 232 #define SCR_EA_BIT (UL(1) << 3) 233 #define SCR_FIQ_BIT (UL(1) << 2) 234 #define SCR_IRQ_BIT (UL(1) << 1) 235 #define SCR_NS_BIT (UL(1) << 0) 236 #define SCR_VALID_BIT_MASK U(0x33ff) 237 #define SCR_RESET_VAL U(0x0) 238 239 #define GET_NS_BIT(scr) ((scr) & SCR_NS_BIT) 240 241 /* HCR definitions */ 242 #define HCR_TGE_BIT (U(1) << 27) 243 #define HCR_AMO_BIT (U(1) << 5) 244 #define HCR_IMO_BIT (U(1) << 4) 245 #define HCR_FMO_BIT (U(1) << 3) 246 #define HCR_RESET_VAL U(0x0) 247 248 /* CNTHCTL definitions */ 249 #define CNTHCTL_RESET_VAL U(0x0) 250 #define PL1PCEN_BIT (U(1) << 1) 251 #define PL1PCTEN_BIT (U(1) << 0) 252 253 /* CNTKCTL definitions */ 254 #define PL0PTEN_BIT (U(1) << 9) 255 #define PL0VTEN_BIT (U(1) << 8) 256 #define PL0PCTEN_BIT (U(1) << 0) 257 #define PL0VCTEN_BIT (U(1) << 1) 258 #define EVNTEN_BIT (U(1) << 2) 259 #define EVNTDIR_BIT (U(1) << 3) 260 #define EVNTI_SHIFT U(4) 261 #define EVNTI_MASK U(0xf) 262 263 /* HCPTR definitions */ 264 #define HCPTR_RES1 ((U(1) << 13) | (U(1) << 12) | U(0x3ff)) 265 #define TCPAC_BIT (U(1) << 31) 266 #define TAM_SHIFT U(30) 267 #define TAM_BIT (U(1) << TAM_SHIFT) 268 #define TTA_BIT (U(1) << 20) 269 #define TCP11_BIT (U(1) << 11) 270 #define TCP10_BIT (U(1) << 10) 271 #define HCPTR_RESET_VAL HCPTR_RES1 272 273 /* VTTBR definitions */ 274 #define VTTBR_RESET_VAL ULL(0x0) 275 #define VTTBR_VMID_MASK ULL(0xff) 276 #define VTTBR_VMID_SHIFT U(48) 277 #define VTTBR_BADDR_MASK ULL(0xffffffffffff) 278 #define VTTBR_BADDR_SHIFT U(0) 279 280 /* HDCR definitions */ 281 #define HDCR_MTPME_BIT (U(1) << 28) 282 #define HDCR_HLP_BIT (U(1) << 26) 283 #define HDCR_HPME_BIT (U(1) << 7) 284 #define HDCR_RESET_VAL U(0x0) 285 286 /* HSTR definitions */ 287 #define HSTR_RESET_VAL U(0x0) 288 289 /* CNTHP_CTL definitions */ 290 #define CNTHP_CTL_RESET_VAL U(0x0) 291 292 /* NSACR definitions */ 293 #define NSASEDIS_BIT (U(1) << 15) 294 #define NSTRCDIS_BIT (U(1) << 20) 295 #define NSACR_CP11_BIT (U(1) << 11) 296 #define NSACR_CP10_BIT (U(1) << 10) 297 #define NSACR_IMP_DEF_MASK (U(0x7) << 16) 298 #define NSACR_ENABLE_FP_ACCESS (NSACR_CP11_BIT | NSACR_CP10_BIT) 299 #define NSACR_RESET_VAL U(0x0) 300 301 /* CPACR definitions */ 302 #define ASEDIS_BIT (U(1) << 31) 303 #define TRCDIS_BIT (U(1) << 28) 304 #define CPACR_CP11_SHIFT U(22) 305 #define CPACR_CP10_SHIFT U(20) 306 #define CPACR_ENABLE_FP_ACCESS ((U(0x3) << CPACR_CP11_SHIFT) |\ 307 (U(0x3) << CPACR_CP10_SHIFT)) 308 #define CPACR_RESET_VAL U(0x0) 309 310 /* FPEXC definitions */ 311 #define FPEXC_RES1 ((U(1) << 10) | (U(1) << 9) | (U(1) << 8)) 312 #define FPEXC_EN_BIT (U(1) << 30) 313 #define FPEXC_RESET_VAL FPEXC_RES1 314 315 /* SPSR/CPSR definitions */ 316 #define SPSR_FIQ_BIT (U(1) << 0) 317 #define SPSR_IRQ_BIT (U(1) << 1) 318 #define SPSR_ABT_BIT (U(1) << 2) 319 #define SPSR_AIF_SHIFT U(6) 320 #define SPSR_AIF_MASK U(0x7) 321 322 #define SPSR_E_SHIFT U(9) 323 #define SPSR_E_MASK U(0x1) 324 #define SPSR_E_LITTLE U(0) 325 #define SPSR_E_BIG U(1) 326 327 #define SPSR_T_SHIFT U(5) 328 #define SPSR_T_MASK U(0x1) 329 #define SPSR_T_ARM U(0) 330 #define SPSR_T_THUMB U(1) 331 332 #define SPSR_MODE_SHIFT U(0) 333 #define SPSR_MODE_MASK U(0x7) 334 335 #define SPSR_SSBS_BIT BIT_32(23) 336 337 #define DISABLE_ALL_EXCEPTIONS \ 338 (SPSR_FIQ_BIT | SPSR_IRQ_BIT | SPSR_ABT_BIT) 339 340 #define CPSR_DIT_BIT (U(1) << 21) 341 /* 342 * TTBCR definitions 343 */ 344 #define TTBCR_EAE_BIT (U(1) << 31) 345 346 #define TTBCR_SH1_NON_SHAREABLE (U(0x0) << 28) 347 #define TTBCR_SH1_OUTER_SHAREABLE (U(0x2) << 28) 348 #define TTBCR_SH1_INNER_SHAREABLE (U(0x3) << 28) 349 350 #define TTBCR_RGN1_OUTER_NC (U(0x0) << 26) 351 #define TTBCR_RGN1_OUTER_WBA (U(0x1) << 26) 352 #define TTBCR_RGN1_OUTER_WT (U(0x2) << 26) 353 #define TTBCR_RGN1_OUTER_WBNA (U(0x3) << 26) 354 355 #define TTBCR_RGN1_INNER_NC (U(0x0) << 24) 356 #define TTBCR_RGN1_INNER_WBA (U(0x1) << 24) 357 #define TTBCR_RGN1_INNER_WT (U(0x2) << 24) 358 #define TTBCR_RGN1_INNER_WBNA (U(0x3) << 24) 359 360 #define TTBCR_EPD1_BIT (U(1) << 23) 361 #define TTBCR_A1_BIT (U(1) << 22) 362 363 #define TTBCR_T1SZ_SHIFT U(16) 364 #define TTBCR_T1SZ_MASK U(0x7) 365 #define TTBCR_TxSZ_MIN U(0) 366 #define TTBCR_TxSZ_MAX U(7) 367 368 #define TTBCR_SH0_NON_SHAREABLE (U(0x0) << 12) 369 #define TTBCR_SH0_OUTER_SHAREABLE (U(0x2) << 12) 370 #define TTBCR_SH0_INNER_SHAREABLE (U(0x3) << 12) 371 372 #define TTBCR_RGN0_OUTER_NC (U(0x0) << 10) 373 #define TTBCR_RGN0_OUTER_WBA (U(0x1) << 10) 374 #define TTBCR_RGN0_OUTER_WT (U(0x2) << 10) 375 #define TTBCR_RGN0_OUTER_WBNA (U(0x3) << 10) 376 377 #define TTBCR_RGN0_INNER_NC (U(0x0) << 8) 378 #define TTBCR_RGN0_INNER_WBA (U(0x1) << 8) 379 #define TTBCR_RGN0_INNER_WT (U(0x2) << 8) 380 #define TTBCR_RGN0_INNER_WBNA (U(0x3) << 8) 381 382 #define TTBCR_EPD0_BIT (U(1) << 7) 383 #define TTBCR_T0SZ_SHIFT U(0) 384 #define TTBCR_T0SZ_MASK U(0x7) 385 386 /* 387 * HTCR definitions 388 */ 389 #define HTCR_RES1 ((U(1) << 31) | (U(1) << 23)) 390 391 #define HTCR_SH0_NON_SHAREABLE (U(0x0) << 12) 392 #define HTCR_SH0_OUTER_SHAREABLE (U(0x2) << 12) 393 #define HTCR_SH0_INNER_SHAREABLE (U(0x3) << 12) 394 395 #define HTCR_RGN0_OUTER_NC (U(0x0) << 10) 396 #define HTCR_RGN0_OUTER_WBA (U(0x1) << 10) 397 #define HTCR_RGN0_OUTER_WT (U(0x2) << 10) 398 #define HTCR_RGN0_OUTER_WBNA (U(0x3) << 10) 399 400 #define HTCR_RGN0_INNER_NC (U(0x0) << 8) 401 #define HTCR_RGN0_INNER_WBA (U(0x1) << 8) 402 #define HTCR_RGN0_INNER_WT (U(0x2) << 8) 403 #define HTCR_RGN0_INNER_WBNA (U(0x3) << 8) 404 405 #define HTCR_T0SZ_SHIFT U(0) 406 #define HTCR_T0SZ_MASK U(0x7) 407 408 #define MODE_RW_SHIFT U(0x4) 409 #define MODE_RW_MASK U(0x1) 410 #define MODE_RW_32 U(0x1) 411 412 #define MODE32_SHIFT U(0) 413 #define MODE32_MASK U(0x1f) 414 #define MODE32_usr U(0x10) 415 #define MODE32_fiq U(0x11) 416 #define MODE32_irq U(0x12) 417 #define MODE32_svc U(0x13) 418 #define MODE32_mon U(0x16) 419 #define MODE32_abt U(0x17) 420 #define MODE32_hyp U(0x1a) 421 #define MODE32_und U(0x1b) 422 #define MODE32_sys U(0x1f) 423 424 #define GET_M32(mode) (((mode) >> MODE32_SHIFT) & MODE32_MASK) 425 426 #define SPSR_MODE32(mode, isa, endian, aif) \ 427 ( \ 428 ( \ 429 (MODE_RW_32 << MODE_RW_SHIFT) | \ 430 (((mode) & MODE32_MASK) << MODE32_SHIFT) | \ 431 (((isa) & SPSR_T_MASK) << SPSR_T_SHIFT) | \ 432 (((endian) & SPSR_E_MASK) << SPSR_E_SHIFT) | \ 433 (((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT) \ 434 ) & \ 435 (~(SPSR_SSBS_BIT)) \ 436 ) 437 438 /* 439 * TTBR definitions 440 */ 441 #define TTBR_CNP_BIT ULL(0x1) 442 443 /* 444 * CTR definitions 445 */ 446 #define CTR_CWG_SHIFT U(24) 447 #define CTR_CWG_MASK U(0xf) 448 #define CTR_ERG_SHIFT U(20) 449 #define CTR_ERG_MASK U(0xf) 450 #define CTR_DMINLINE_SHIFT U(16) 451 #define CTR_DMINLINE_WIDTH U(4) 452 #define CTR_DMINLINE_MASK ((U(1) << 4) - U(1)) 453 #define CTR_L1IP_SHIFT U(14) 454 #define CTR_L1IP_MASK U(0x3) 455 #define CTR_IMINLINE_SHIFT U(0) 456 #define CTR_IMINLINE_MASK U(0xf) 457 458 #define MAX_CACHE_LINE_SIZE U(0x800) /* 2KB */ 459 460 /* PMCR definitions */ 461 #define PMCR_N_SHIFT U(11) 462 #define PMCR_N_MASK U(0x1f) 463 #define PMCR_N_BITS (PMCR_N_MASK << PMCR_N_SHIFT) 464 #define PMCR_LP_BIT (U(1) << 7) 465 #define PMCR_LC_BIT (U(1) << 6) 466 #define PMCR_DP_BIT (U(1) << 5) 467 #define PMCR_RESET_VAL U(0x0) 468 469 /******************************************************************************* 470 * Definitions of register offsets, fields and macros for CPU system 471 * instructions. 472 ******************************************************************************/ 473 474 #define TLBI_ADDR_SHIFT U(0) 475 #define TLBI_ADDR_MASK U(0xFFFFF000) 476 #define TLBI_ADDR(x) (((x) >> TLBI_ADDR_SHIFT) & TLBI_ADDR_MASK) 477 478 /******************************************************************************* 479 * Definitions of register offsets and fields in the CNTCTLBase Frame of the 480 * system level implementation of the Generic Timer. 481 ******************************************************************************/ 482 #define CNTCTLBASE_CNTFRQ U(0x0) 483 #define CNTNSAR U(0x4) 484 #define CNTNSAR_NS_SHIFT(x) (x) 485 486 #define CNTACR_BASE(x) (U(0x40) + ((x) << 2)) 487 #define CNTACR_RPCT_SHIFT U(0x0) 488 #define CNTACR_RVCT_SHIFT U(0x1) 489 #define CNTACR_RFRQ_SHIFT U(0x2) 490 #define CNTACR_RVOFF_SHIFT U(0x3) 491 #define CNTACR_RWVT_SHIFT U(0x4) 492 #define CNTACR_RWPT_SHIFT U(0x5) 493 494 /******************************************************************************* 495 * Definitions of register offsets and fields in the CNTBaseN Frame of the 496 * system level implementation of the Generic Timer. 497 ******************************************************************************/ 498 /* Physical Count register. */ 499 #define CNTPCT_LO U(0x0) 500 /* Counter Frequency register. */ 501 #define CNTBASEN_CNTFRQ U(0x10) 502 /* Physical Timer CompareValue register. */ 503 #define CNTP_CVAL_LO U(0x20) 504 /* Physical Timer Control register. */ 505 #define CNTP_CTL U(0x2c) 506 507 /* Physical timer control register bit fields shifts and masks */ 508 #define CNTP_CTL_ENABLE_SHIFT 0 509 #define CNTP_CTL_IMASK_SHIFT 1 510 #define CNTP_CTL_ISTATUS_SHIFT 2 511 512 #define CNTP_CTL_ENABLE_MASK U(1) 513 #define CNTP_CTL_IMASK_MASK U(1) 514 #define CNTP_CTL_ISTATUS_MASK U(1) 515 516 /* MAIR macros */ 517 #define MAIR0_ATTR_SET(attr, index) ((attr) << ((index) << U(3))) 518 #define MAIR1_ATTR_SET(attr, index) ((attr) << (((index) - U(3)) << U(3))) 519 520 /* System register defines The format is: coproc, opt1, CRn, CRm, opt2 */ 521 #define SCR p15, 0, c1, c1, 0 522 #define SCTLR p15, 0, c1, c0, 0 523 #define ACTLR p15, 0, c1, c0, 1 524 #define SDCR p15, 0, c1, c3, 1 525 #define MPIDR p15, 0, c0, c0, 5 526 #define MIDR p15, 0, c0, c0, 0 527 #define HVBAR p15, 4, c12, c0, 0 528 #define VBAR p15, 0, c12, c0, 0 529 #define MVBAR p15, 0, c12, c0, 1 530 #define NSACR p15, 0, c1, c1, 2 531 #define CPACR p15, 0, c1, c0, 2 532 #define DCCIMVAC p15, 0, c7, c14, 1 533 #define DCCMVAC p15, 0, c7, c10, 1 534 #define DCIMVAC p15, 0, c7, c6, 1 535 #define DCCISW p15, 0, c7, c14, 2 536 #define DCCSW p15, 0, c7, c10, 2 537 #define DCISW p15, 0, c7, c6, 2 538 #define CTR p15, 0, c0, c0, 1 539 #define CNTFRQ p15, 0, c14, c0, 0 540 #define ID_MMFR3 p15, 0, c0, c1, 7 541 #define ID_MMFR4 p15, 0, c0, c2, 6 542 #define ID_DFR0 p15, 0, c0, c1, 2 543 #define ID_DFR1 p15, 0, c0, c3, 5 544 #define ID_PFR0 p15, 0, c0, c1, 0 545 #define ID_PFR1 p15, 0, c0, c1, 1 546 #define MAIR0 p15, 0, c10, c2, 0 547 #define MAIR1 p15, 0, c10, c2, 1 548 #define TTBCR p15, 0, c2, c0, 2 549 #define TTBR0 p15, 0, c2, c0, 0 550 #define TTBR1 p15, 0, c2, c0, 1 551 #define TLBIALL p15, 0, c8, c7, 0 552 #define TLBIALLH p15, 4, c8, c7, 0 553 #define TLBIALLIS p15, 0, c8, c3, 0 554 #define TLBIMVA p15, 0, c8, c7, 1 555 #define TLBIMVAA p15, 0, c8, c7, 3 556 #define TLBIMVAAIS p15, 0, c8, c3, 3 557 #define TLBIMVAHIS p15, 4, c8, c3, 1 558 #define BPIALLIS p15, 0, c7, c1, 6 559 #define BPIALL p15, 0, c7, c5, 6 560 #define ICIALLU p15, 0, c7, c5, 0 561 #define HSCTLR p15, 4, c1, c0, 0 562 #define HCR p15, 4, c1, c1, 0 563 #define HCPTR p15, 4, c1, c1, 2 564 #define HSTR p15, 4, c1, c1, 3 565 #define CNTHCTL p15, 4, c14, c1, 0 566 #define CNTKCTL p15, 0, c14, c1, 0 567 #define VPIDR p15, 4, c0, c0, 0 568 #define VMPIDR p15, 4, c0, c0, 5 569 #define ISR p15, 0, c12, c1, 0 570 #define CLIDR p15, 1, c0, c0, 1 571 #define CSSELR p15, 2, c0, c0, 0 572 #define CCSIDR p15, 1, c0, c0, 0 573 #define CCSIDR2 p15, 1, c0, c0, 2 574 #define HTCR p15, 4, c2, c0, 2 575 #define HMAIR0 p15, 4, c10, c2, 0 576 #define ATS1CPR p15, 0, c7, c8, 0 577 #define ATS1HR p15, 4, c7, c8, 0 578 #define DBGOSDLR p14, 0, c1, c3, 4 579 580 /* Debug register defines. The format is: coproc, opt1, CRn, CRm, opt2 */ 581 #define HDCR p15, 4, c1, c1, 1 582 #define PMCR p15, 0, c9, c12, 0 583 #define CNTHP_TVAL p15, 4, c14, c2, 0 584 #define CNTHP_CTL p15, 4, c14, c2, 1 585 586 /* AArch32 coproc registers for 32bit MMU descriptor support */ 587 #define PRRR p15, 0, c10, c2, 0 588 #define NMRR p15, 0, c10, c2, 1 589 #define DACR p15, 0, c3, c0, 0 590 591 /* GICv3 CPU Interface system register defines. The format is: coproc, opt1, CRn, CRm, opt2 */ 592 #define ICC_IAR1 p15, 0, c12, c12, 0 593 #define ICC_IAR0 p15, 0, c12, c8, 0 594 #define ICC_EOIR1 p15, 0, c12, c12, 1 595 #define ICC_EOIR0 p15, 0, c12, c8, 1 596 #define ICC_HPPIR1 p15, 0, c12, c12, 2 597 #define ICC_HPPIR0 p15, 0, c12, c8, 2 598 #define ICC_BPR1 p15, 0, c12, c12, 3 599 #define ICC_BPR0 p15, 0, c12, c8, 3 600 #define ICC_DIR p15, 0, c12, c11, 1 601 #define ICC_PMR p15, 0, c4, c6, 0 602 #define ICC_RPR p15, 0, c12, c11, 3 603 #define ICC_CTLR p15, 0, c12, c12, 4 604 #define ICC_MCTLR p15, 6, c12, c12, 4 605 #define ICC_SRE p15, 0, c12, c12, 5 606 #define ICC_HSRE p15, 4, c12, c9, 5 607 #define ICC_MSRE p15, 6, c12, c12, 5 608 #define ICC_IGRPEN0 p15, 0, c12, c12, 6 609 #define ICC_IGRPEN1 p15, 0, c12, c12, 7 610 #define ICC_MGRPEN1 p15, 6, c12, c12, 7 611 612 /* 64 bit system register defines The format is: coproc, opt1, CRm */ 613 #define TTBR0_64 p15, 0, c2 614 #define TTBR1_64 p15, 1, c2 615 #define CNTVOFF_64 p15, 4, c14 616 #define VTTBR_64 p15, 6, c2 617 #define CNTPCT_64 p15, 0, c14 618 #define HTTBR_64 p15, 4, c2 619 #define CNTHP_CVAL_64 p15, 6, c14 620 #define PAR_64 p15, 0, c7 621 622 /* 64 bit GICv3 CPU Interface system register defines. The format is: coproc, opt1, CRm */ 623 #define ICC_SGI1R_EL1_64 p15, 0, c12 624 #define ICC_ASGI1R_EL1_64 p15, 1, c12 625 #define ICC_SGI0R_EL1_64 p15, 2, c12 626 627 /* Fault registers. The format is: coproc, opt1, CRn, CRm, opt2 */ 628 #define DFSR p15, 0, c5, c0, 0 629 #define IFSR p15, 0, c5, c0, 1 630 #define DFAR p15, 0, c6, c0, 0 631 #define IFAR p15, 0, c6, c0, 2 632 633 /******************************************************************************* 634 * Definitions of MAIR encodings for device and normal memory 635 ******************************************************************************/ 636 /* 637 * MAIR encodings for device memory attributes. 638 */ 639 #define MAIR_DEV_nGnRnE U(0x0) 640 #define MAIR_DEV_nGnRE U(0x4) 641 #define MAIR_DEV_nGRE U(0x8) 642 #define MAIR_DEV_GRE U(0xc) 643 644 /* 645 * MAIR encodings for normal memory attributes. 646 * 647 * Cache Policy 648 * WT: Write Through 649 * WB: Write Back 650 * NC: Non-Cacheable 651 * 652 * Transient Hint 653 * NTR: Non-Transient 654 * TR: Transient 655 * 656 * Allocation Policy 657 * RA: Read Allocate 658 * WA: Write Allocate 659 * RWA: Read and Write Allocate 660 * NA: No Allocation 661 */ 662 #define MAIR_NORM_WT_TR_WA U(0x1) 663 #define MAIR_NORM_WT_TR_RA U(0x2) 664 #define MAIR_NORM_WT_TR_RWA U(0x3) 665 #define MAIR_NORM_NC U(0x4) 666 #define MAIR_NORM_WB_TR_WA U(0x5) 667 #define MAIR_NORM_WB_TR_RA U(0x6) 668 #define MAIR_NORM_WB_TR_RWA U(0x7) 669 #define MAIR_NORM_WT_NTR_NA U(0x8) 670 #define MAIR_NORM_WT_NTR_WA U(0x9) 671 #define MAIR_NORM_WT_NTR_RA U(0xa) 672 #define MAIR_NORM_WT_NTR_RWA U(0xb) 673 #define MAIR_NORM_WB_NTR_NA U(0xc) 674 #define MAIR_NORM_WB_NTR_WA U(0xd) 675 #define MAIR_NORM_WB_NTR_RA U(0xe) 676 #define MAIR_NORM_WB_NTR_RWA U(0xf) 677 678 #define MAIR_NORM_OUTER_SHIFT U(4) 679 680 #define MAKE_MAIR_NORMAL_MEMORY(inner, outer) \ 681 ((inner) | ((outer) << MAIR_NORM_OUTER_SHIFT)) 682 683 /* PAR fields */ 684 #define PAR_F_SHIFT U(0) 685 #define PAR_F_MASK ULL(0x1) 686 #define PAR_ADDR_SHIFT U(12) 687 #define PAR_ADDR_MASK (BIT_64(40) - ULL(1)) /* 40-bits-wide page address */ 688 689 /******************************************************************************* 690 * Definitions for system register interface to AMU for FEAT_AMUv1 691 ******************************************************************************/ 692 #define AMCR p15, 0, c13, c2, 0 693 #define AMCFGR p15, 0, c13, c2, 1 694 #define AMCGCR p15, 0, c13, c2, 2 695 #define AMUSERENR p15, 0, c13, c2, 3 696 #define AMCNTENCLR0 p15, 0, c13, c2, 4 697 #define AMCNTENSET0 p15, 0, c13, c2, 5 698 #define AMCNTENCLR1 p15, 0, c13, c3, 0 699 #define AMCNTENSET1 p15, 0, c13, c3, 1 700 701 /* Activity Monitor Group 0 Event Counter Registers */ 702 #define AMEVCNTR00 p15, 0, c0 703 #define AMEVCNTR01 p15, 1, c0 704 #define AMEVCNTR02 p15, 2, c0 705 #define AMEVCNTR03 p15, 3, c0 706 707 /* Activity Monitor Group 0 Event Type Registers */ 708 #define AMEVTYPER00 p15, 0, c13, c6, 0 709 #define AMEVTYPER01 p15, 0, c13, c6, 1 710 #define AMEVTYPER02 p15, 0, c13, c6, 2 711 #define AMEVTYPER03 p15, 0, c13, c6, 3 712 713 /* Activity Monitor Group 1 Event Counter Registers */ 714 #define AMEVCNTR10 p15, 0, c4 715 #define AMEVCNTR11 p15, 1, c4 716 #define AMEVCNTR12 p15, 2, c4 717 #define AMEVCNTR13 p15, 3, c4 718 #define AMEVCNTR14 p15, 4, c4 719 #define AMEVCNTR15 p15, 5, c4 720 #define AMEVCNTR16 p15, 6, c4 721 #define AMEVCNTR17 p15, 7, c4 722 #define AMEVCNTR18 p15, 0, c5 723 #define AMEVCNTR19 p15, 1, c5 724 #define AMEVCNTR1A p15, 2, c5 725 #define AMEVCNTR1B p15, 3, c5 726 #define AMEVCNTR1C p15, 4, c5 727 #define AMEVCNTR1D p15, 5, c5 728 #define AMEVCNTR1E p15, 6, c5 729 #define AMEVCNTR1F p15, 7, c5 730 731 /* Activity Monitor Group 1 Event Type Registers */ 732 #define AMEVTYPER10 p15, 0, c13, c14, 0 733 #define AMEVTYPER11 p15, 0, c13, c14, 1 734 #define AMEVTYPER12 p15, 0, c13, c14, 2 735 #define AMEVTYPER13 p15, 0, c13, c14, 3 736 #define AMEVTYPER14 p15, 0, c13, c14, 4 737 #define AMEVTYPER15 p15, 0, c13, c14, 5 738 #define AMEVTYPER16 p15, 0, c13, c14, 6 739 #define AMEVTYPER17 p15, 0, c13, c14, 7 740 #define AMEVTYPER18 p15, 0, c13, c15, 0 741 #define AMEVTYPER19 p15, 0, c13, c15, 1 742 #define AMEVTYPER1A p15, 0, c13, c15, 2 743 #define AMEVTYPER1B p15, 0, c13, c15, 3 744 #define AMEVTYPER1C p15, 0, c13, c15, 4 745 #define AMEVTYPER1D p15, 0, c13, c15, 5 746 #define AMEVTYPER1E p15, 0, c13, c15, 6 747 #define AMEVTYPER1F p15, 0, c13, c15, 7 748 749 /* AMCNTENSET0 definitions */ 750 #define AMCNTENSET0_Pn_SHIFT U(0) 751 #define AMCNTENSET0_Pn_MASK U(0xffff) 752 753 /* AMCNTENSET1 definitions */ 754 #define AMCNTENSET1_Pn_SHIFT U(0) 755 #define AMCNTENSET1_Pn_MASK U(0xffff) 756 757 /* AMCNTENCLR0 definitions */ 758 #define AMCNTENCLR0_Pn_SHIFT U(0) 759 #define AMCNTENCLR0_Pn_MASK U(0xffff) 760 761 /* AMCNTENCLR1 definitions */ 762 #define AMCNTENCLR1_Pn_SHIFT U(0) 763 #define AMCNTENCLR1_Pn_MASK U(0xffff) 764 765 /* AMCR definitions */ 766 #define AMCR_CG1RZ_SHIFT U(17) 767 #define AMCR_CG1RZ_BIT (ULL(1) << AMCR_CG1RZ_SHIFT) 768 769 /* AMCFGR definitions */ 770 #define AMCFGR_NCG_SHIFT U(28) 771 #define AMCFGR_NCG_MASK U(0xf) 772 #define AMCFGR_N_SHIFT U(0) 773 #define AMCFGR_N_MASK U(0xff) 774 775 /* AMCGCR definitions */ 776 #define AMCGCR_CG0NC_SHIFT U(0) 777 #define AMCGCR_CG0NC_MASK U(0xff) 778 #define AMCGCR_CG1NC_SHIFT U(8) 779 #define AMCGCR_CG1NC_MASK U(0xff) 780 781 /******************************************************************************* 782 * Definitions for DynamicIQ Shared Unit registers 783 ******************************************************************************/ 784 #define CLUSTERPWRDN p15, 0, c15, c3, 6 785 786 /* CLUSTERPWRDN register definitions */ 787 #define DSU_CLUSTER_PWR_OFF 0 788 #define DSU_CLUSTER_PWR_ON 1 789 #define DSU_CLUSTER_PWR_MASK U(1) 790 791 #endif /* ARCH_H */ 792