1 /* 2 * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef ARCH_H 8 #define ARCH_H 9 10 #include <lib/utils_def.h> 11 12 /******************************************************************************* 13 * MIDR bit definitions 14 ******************************************************************************/ 15 #define MIDR_IMPL_MASK U(0xff) 16 #define MIDR_IMPL_SHIFT U(24) 17 #define MIDR_VAR_SHIFT U(20) 18 #define MIDR_VAR_BITS U(4) 19 #define MIDR_REV_SHIFT U(0) 20 #define MIDR_REV_BITS U(4) 21 #define MIDR_PN_MASK U(0xfff) 22 #define MIDR_PN_SHIFT U(4) 23 24 /******************************************************************************* 25 * MPIDR macros 26 ******************************************************************************/ 27 #define MPIDR_MT_MASK (U(1) << 24) 28 #define MPIDR_CPU_MASK MPIDR_AFFLVL_MASK 29 #define MPIDR_CLUSTER_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS) 30 #define MPIDR_AFFINITY_BITS U(8) 31 #define MPIDR_AFFLVL_MASK U(0xff) 32 #define MPIDR_AFFLVL_SHIFT U(3) 33 #define MPIDR_AFF0_SHIFT U(0) 34 #define MPIDR_AFF1_SHIFT U(8) 35 #define MPIDR_AFF2_SHIFT U(16) 36 #define MPIDR_AFF_SHIFT(_n) MPIDR_AFF##_n##_SHIFT 37 #define MPIDR_AFFINITY_MASK U(0x00ffffff) 38 #define MPIDR_AFFLVL0 U(0) 39 #define MPIDR_AFFLVL1 U(1) 40 #define MPIDR_AFFLVL2 U(2) 41 #define MPIDR_AFFLVL(_n) MPIDR_AFFLVL##_n 42 43 #define MPIDR_AFFLVL0_VAL(mpidr) \ 44 (((mpidr) >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK) 45 #define MPIDR_AFFLVL1_VAL(mpidr) \ 46 (((mpidr) >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK) 47 #define MPIDR_AFFLVL2_VAL(mpidr) \ 48 (((mpidr) >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK) 49 #define MPIDR_AFFLVL3_VAL(mpidr) U(0) 50 51 #define MPIDR_AFF_ID(mpid, n) \ 52 (((mpid) >> MPIDR_AFF_SHIFT(n)) & MPIDR_AFFLVL_MASK) 53 54 #define MPID_MASK (MPIDR_MT_MASK |\ 55 (MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT)|\ 56 (MPIDR_AFFLVL_MASK << MPIDR_AFF1_SHIFT)|\ 57 (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT)) 58 59 /* 60 * An invalid MPID. This value can be used by functions that return an MPID to 61 * indicate an error. 62 */ 63 #define INVALID_MPID U(0xFFFFFFFF) 64 65 /* 66 * The MPIDR_MAX_AFFLVL count starts from 0. Take care to 67 * add one while using this macro to define array sizes. 68 */ 69 #define MPIDR_MAX_AFFLVL U(2) 70 71 /* Data Cache set/way op type defines */ 72 #define DC_OP_ISW U(0x0) 73 #define DC_OP_CISW U(0x1) 74 #define DC_OP_CSW U(0x2) 75 76 /******************************************************************************* 77 * Generic timer memory mapped registers & offsets 78 ******************************************************************************/ 79 #define CNTCR_OFF U(0x000) 80 #define CNTFID_OFF U(0x020) 81 82 #define CNTCR_EN (U(1) << 0) 83 #define CNTCR_HDBG (U(1) << 1) 84 #define CNTCR_FCREQ(x) ((x) << 8) 85 86 /******************************************************************************* 87 * System register bit definitions 88 ******************************************************************************/ 89 /* CLIDR definitions */ 90 #define LOUIS_SHIFT U(21) 91 #define LOC_SHIFT U(24) 92 #define CLIDR_FIELD_WIDTH U(3) 93 94 /* CSSELR definitions */ 95 #define LEVEL_SHIFT U(1) 96 97 /* ID_MMFR4 definitions */ 98 #define ID_MMFR4_CNP_SHIFT U(12) 99 #define ID_MMFR4_CNP_LENGTH U(4) 100 #define ID_MMFR4_CNP_MASK U(0xf) 101 102 /* ID_PFR0 definitions */ 103 #define ID_PFR0_AMU_SHIFT U(20) 104 #define ID_PFR0_AMU_LENGTH U(4) 105 #define ID_PFR0_AMU_MASK U(0xf) 106 107 #define ID_PFR0_DIT_SHIFT U(24) 108 #define ID_PFR0_DIT_LENGTH U(4) 109 #define ID_PFR0_DIT_MASK U(0xf) 110 #define ID_PFR0_DIT_SUPPORTED (U(1) << ID_PFR0_DIT_SHIFT) 111 112 /* ID_PFR1 definitions */ 113 #define ID_PFR1_VIRTEXT_SHIFT U(12) 114 #define ID_PFR1_VIRTEXT_MASK U(0xf) 115 #define GET_VIRT_EXT(id) (((id) >> ID_PFR1_VIRTEXT_SHIFT) \ 116 & ID_PFR1_VIRTEXT_MASK) 117 #define ID_PFR1_GENTIMER_SHIFT U(16) 118 #define ID_PFR1_GENTIMER_MASK U(0xf) 119 #define ID_PFR1_GIC_SHIFT U(28) 120 #define ID_PFR1_GIC_MASK U(0xf) 121 122 /* SCTLR definitions */ 123 #define SCTLR_RES1_DEF ((U(1) << 23) | (U(1) << 22) | (U(1) << 4) | \ 124 (U(1) << 3)) 125 #if ARM_ARCH_MAJOR == 7 126 #define SCTLR_RES1 SCTLR_RES1_DEF 127 #else 128 #define SCTLR_RES1 (SCTLR_RES1_DEF | (U(1) << 11)) 129 #endif 130 #define SCTLR_M_BIT (U(1) << 0) 131 #define SCTLR_A_BIT (U(1) << 1) 132 #define SCTLR_C_BIT (U(1) << 2) 133 #define SCTLR_CP15BEN_BIT (U(1) << 5) 134 #define SCTLR_ITD_BIT (U(1) << 7) 135 #define SCTLR_Z_BIT (U(1) << 11) 136 #define SCTLR_I_BIT (U(1) << 12) 137 #define SCTLR_V_BIT (U(1) << 13) 138 #define SCTLR_RR_BIT (U(1) << 14) 139 #define SCTLR_NTWI_BIT (U(1) << 16) 140 #define SCTLR_NTWE_BIT (U(1) << 18) 141 #define SCTLR_WXN_BIT (U(1) << 19) 142 #define SCTLR_UWXN_BIT (U(1) << 20) 143 #define SCTLR_EE_BIT (U(1) << 25) 144 #define SCTLR_TRE_BIT (U(1) << 28) 145 #define SCTLR_AFE_BIT (U(1) << 29) 146 #define SCTLR_TE_BIT (U(1) << 30) 147 #define SCTLR_DSSBS_BIT (U(1) << 31) 148 #define SCTLR_RESET_VAL (SCTLR_RES1 | SCTLR_NTWE_BIT | \ 149 SCTLR_NTWI_BIT | SCTLR_CP15BEN_BIT) 150 151 /* SDCR definitions */ 152 #define SDCR_SPD(x) ((x) << 14) 153 #define SDCR_SPD_LEGACY U(0x0) 154 #define SDCR_SPD_DISABLE U(0x2) 155 #define SDCR_SPD_ENABLE U(0x3) 156 #define SDCR_RESET_VAL U(0x0) 157 158 /* HSCTLR definitions */ 159 #define HSCTLR_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ 160 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \ 161 (U(1) << 11) | (U(1) << 4) | (U(1) << 3)) 162 163 #define HSCTLR_M_BIT (U(1) << 0) 164 #define HSCTLR_A_BIT (U(1) << 1) 165 #define HSCTLR_C_BIT (U(1) << 2) 166 #define HSCTLR_CP15BEN_BIT (U(1) << 5) 167 #define HSCTLR_ITD_BIT (U(1) << 7) 168 #define HSCTLR_SED_BIT (U(1) << 8) 169 #define HSCTLR_I_BIT (U(1) << 12) 170 #define HSCTLR_WXN_BIT (U(1) << 19) 171 #define HSCTLR_EE_BIT (U(1) << 25) 172 #define HSCTLR_TE_BIT (U(1) << 30) 173 174 /* CPACR definitions */ 175 #define CPACR_FPEN(x) ((x) << 20) 176 #define CPACR_FP_TRAP_PL0 U(0x1) 177 #define CPACR_FP_TRAP_ALL U(0x2) 178 #define CPACR_FP_TRAP_NONE U(0x3) 179 180 /* SCR definitions */ 181 #define SCR_TWE_BIT (U(1) << 13) 182 #define SCR_TWI_BIT (U(1) << 12) 183 #define SCR_SIF_BIT (U(1) << 9) 184 #define SCR_HCE_BIT (U(1) << 8) 185 #define SCR_SCD_BIT (U(1) << 7) 186 #define SCR_NET_BIT (U(1) << 6) 187 #define SCR_AW_BIT (U(1) << 5) 188 #define SCR_FW_BIT (U(1) << 4) 189 #define SCR_EA_BIT (U(1) << 3) 190 #define SCR_FIQ_BIT (U(1) << 2) 191 #define SCR_IRQ_BIT (U(1) << 1) 192 #define SCR_NS_BIT (U(1) << 0) 193 #define SCR_VALID_BIT_MASK U(0x33ff) 194 #define SCR_RESET_VAL U(0x0) 195 196 #define GET_NS_BIT(scr) ((scr) & SCR_NS_BIT) 197 198 /* HCR definitions */ 199 #define HCR_TGE_BIT (U(1) << 27) 200 #define HCR_AMO_BIT (U(1) << 5) 201 #define HCR_IMO_BIT (U(1) << 4) 202 #define HCR_FMO_BIT (U(1) << 3) 203 #define HCR_RESET_VAL U(0x0) 204 205 /* CNTHCTL definitions */ 206 #define CNTHCTL_RESET_VAL U(0x0) 207 #define PL1PCEN_BIT (U(1) << 1) 208 #define PL1PCTEN_BIT (U(1) << 0) 209 210 /* CNTKCTL definitions */ 211 #define PL0PTEN_BIT (U(1) << 9) 212 #define PL0VTEN_BIT (U(1) << 8) 213 #define PL0PCTEN_BIT (U(1) << 0) 214 #define PL0VCTEN_BIT (U(1) << 1) 215 #define EVNTEN_BIT (U(1) << 2) 216 #define EVNTDIR_BIT (U(1) << 3) 217 #define EVNTI_SHIFT U(4) 218 #define EVNTI_MASK U(0xf) 219 220 /* HCPTR definitions */ 221 #define HCPTR_RES1 ((U(1) << 13) | (U(1) << 12) | U(0x3ff)) 222 #define TCPAC_BIT (U(1) << 31) 223 #define TAM_BIT (U(1) << 30) 224 #define TTA_BIT (U(1) << 20) 225 #define TCP11_BIT (U(1) << 11) 226 #define TCP10_BIT (U(1) << 10) 227 #define HCPTR_RESET_VAL HCPTR_RES1 228 229 /* VTTBR defintions */ 230 #define VTTBR_RESET_VAL ULL(0x0) 231 #define VTTBR_VMID_MASK ULL(0xff) 232 #define VTTBR_VMID_SHIFT U(48) 233 #define VTTBR_BADDR_MASK ULL(0xffffffffffff) 234 #define VTTBR_BADDR_SHIFT U(0) 235 236 /* HDCR definitions */ 237 #define HDCR_RESET_VAL U(0x0) 238 239 /* HSTR definitions */ 240 #define HSTR_RESET_VAL U(0x0) 241 242 /* CNTHP_CTL definitions */ 243 #define CNTHP_CTL_RESET_VAL U(0x0) 244 245 /* NSACR definitions */ 246 #define NSASEDIS_BIT (U(1) << 15) 247 #define NSTRCDIS_BIT (U(1) << 20) 248 #define NSACR_CP11_BIT (U(1) << 11) 249 #define NSACR_CP10_BIT (U(1) << 10) 250 #define NSACR_IMP_DEF_MASK (U(0x7) << 16) 251 #define NSACR_ENABLE_FP_ACCESS (NSACR_CP11_BIT | NSACR_CP10_BIT) 252 #define NSACR_RESET_VAL U(0x0) 253 254 /* CPACR definitions */ 255 #define ASEDIS_BIT (U(1) << 31) 256 #define TRCDIS_BIT (U(1) << 28) 257 #define CPACR_CP11_SHIFT U(22) 258 #define CPACR_CP10_SHIFT U(20) 259 #define CPACR_ENABLE_FP_ACCESS ((U(0x3) << CPACR_CP11_SHIFT) |\ 260 (U(0x3) << CPACR_CP10_SHIFT)) 261 #define CPACR_RESET_VAL U(0x0) 262 263 /* FPEXC definitions */ 264 #define FPEXC_RES1 ((U(1) << 10) | (U(1) << 9) | (U(1) << 8)) 265 #define FPEXC_EN_BIT (U(1) << 30) 266 #define FPEXC_RESET_VAL FPEXC_RES1 267 268 /* SPSR/CPSR definitions */ 269 #define SPSR_FIQ_BIT (U(1) << 0) 270 #define SPSR_IRQ_BIT (U(1) << 1) 271 #define SPSR_ABT_BIT (U(1) << 2) 272 #define SPSR_AIF_SHIFT U(6) 273 #define SPSR_AIF_MASK U(0x7) 274 275 #define SPSR_E_SHIFT U(9) 276 #define SPSR_E_MASK U(0x1) 277 #define SPSR_E_LITTLE U(0) 278 #define SPSR_E_BIG U(1) 279 280 #define SPSR_T_SHIFT U(5) 281 #define SPSR_T_MASK U(0x1) 282 #define SPSR_T_ARM U(0) 283 #define SPSR_T_THUMB U(1) 284 285 #define SPSR_MODE_SHIFT U(0) 286 #define SPSR_MODE_MASK U(0x7) 287 288 #define DISABLE_ALL_EXCEPTIONS \ 289 (SPSR_FIQ_BIT | SPSR_IRQ_BIT | SPSR_ABT_BIT) 290 291 #define CPSR_DIT_BIT (U(1) << 21) 292 /* 293 * TTBCR definitions 294 */ 295 #define TTBCR_EAE_BIT (U(1) << 31) 296 297 #define TTBCR_SH1_NON_SHAREABLE (U(0x0) << 28) 298 #define TTBCR_SH1_OUTER_SHAREABLE (U(0x2) << 28) 299 #define TTBCR_SH1_INNER_SHAREABLE (U(0x3) << 28) 300 301 #define TTBCR_RGN1_OUTER_NC (U(0x0) << 26) 302 #define TTBCR_RGN1_OUTER_WBA (U(0x1) << 26) 303 #define TTBCR_RGN1_OUTER_WT (U(0x2) << 26) 304 #define TTBCR_RGN1_OUTER_WBNA (U(0x3) << 26) 305 306 #define TTBCR_RGN1_INNER_NC (U(0x0) << 24) 307 #define TTBCR_RGN1_INNER_WBA (U(0x1) << 24) 308 #define TTBCR_RGN1_INNER_WT (U(0x2) << 24) 309 #define TTBCR_RGN1_INNER_WBNA (U(0x3) << 24) 310 311 #define TTBCR_EPD1_BIT (U(1) << 23) 312 #define TTBCR_A1_BIT (U(1) << 22) 313 314 #define TTBCR_T1SZ_SHIFT U(16) 315 #define TTBCR_T1SZ_MASK U(0x7) 316 #define TTBCR_TxSZ_MIN U(0) 317 #define TTBCR_TxSZ_MAX U(7) 318 319 #define TTBCR_SH0_NON_SHAREABLE (U(0x0) << 12) 320 #define TTBCR_SH0_OUTER_SHAREABLE (U(0x2) << 12) 321 #define TTBCR_SH0_INNER_SHAREABLE (U(0x3) << 12) 322 323 #define TTBCR_RGN0_OUTER_NC (U(0x0) << 10) 324 #define TTBCR_RGN0_OUTER_WBA (U(0x1) << 10) 325 #define TTBCR_RGN0_OUTER_WT (U(0x2) << 10) 326 #define TTBCR_RGN0_OUTER_WBNA (U(0x3) << 10) 327 328 #define TTBCR_RGN0_INNER_NC (U(0x0) << 8) 329 #define TTBCR_RGN0_INNER_WBA (U(0x1) << 8) 330 #define TTBCR_RGN0_INNER_WT (U(0x2) << 8) 331 #define TTBCR_RGN0_INNER_WBNA (U(0x3) << 8) 332 333 #define TTBCR_EPD0_BIT (U(1) << 7) 334 #define TTBCR_T0SZ_SHIFT U(0) 335 #define TTBCR_T0SZ_MASK U(0x7) 336 337 /* 338 * HTCR definitions 339 */ 340 #define HTCR_RES1 ((U(1) << 31) | (U(1) << 23)) 341 342 #define HTCR_SH0_NON_SHAREABLE (U(0x0) << 12) 343 #define HTCR_SH0_OUTER_SHAREABLE (U(0x2) << 12) 344 #define HTCR_SH0_INNER_SHAREABLE (U(0x3) << 12) 345 346 #define HTCR_RGN0_OUTER_NC (U(0x0) << 10) 347 #define HTCR_RGN0_OUTER_WBA (U(0x1) << 10) 348 #define HTCR_RGN0_OUTER_WT (U(0x2) << 10) 349 #define HTCR_RGN0_OUTER_WBNA (U(0x3) << 10) 350 351 #define HTCR_RGN0_INNER_NC (U(0x0) << 8) 352 #define HTCR_RGN0_INNER_WBA (U(0x1) << 8) 353 #define HTCR_RGN0_INNER_WT (U(0x2) << 8) 354 #define HTCR_RGN0_INNER_WBNA (U(0x3) << 8) 355 356 #define HTCR_T0SZ_SHIFT U(0) 357 #define HTCR_T0SZ_MASK U(0x7) 358 359 #define MODE_RW_SHIFT U(0x4) 360 #define MODE_RW_MASK U(0x1) 361 #define MODE_RW_32 U(0x1) 362 363 #define MODE32_SHIFT U(0) 364 #define MODE32_MASK U(0x1f) 365 #define MODE32_usr U(0x10) 366 #define MODE32_fiq U(0x11) 367 #define MODE32_irq U(0x12) 368 #define MODE32_svc U(0x13) 369 #define MODE32_mon U(0x16) 370 #define MODE32_abt U(0x17) 371 #define MODE32_hyp U(0x1a) 372 #define MODE32_und U(0x1b) 373 #define MODE32_sys U(0x1f) 374 375 #define GET_M32(mode) (((mode) >> MODE32_SHIFT) & MODE32_MASK) 376 377 #define SPSR_MODE32(mode, isa, endian, aif) \ 378 (MODE_RW_32 << MODE_RW_SHIFT | \ 379 ((mode) & MODE32_MASK) << MODE32_SHIFT | \ 380 ((isa) & SPSR_T_MASK) << SPSR_T_SHIFT | \ 381 ((endian) & SPSR_E_MASK) << SPSR_E_SHIFT | \ 382 ((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT) 383 384 /* 385 * TTBR definitions 386 */ 387 #define TTBR_CNP_BIT ULL(0x1) 388 389 /* 390 * CTR definitions 391 */ 392 #define CTR_CWG_SHIFT U(24) 393 #define CTR_CWG_MASK U(0xf) 394 #define CTR_ERG_SHIFT U(20) 395 #define CTR_ERG_MASK U(0xf) 396 #define CTR_DMINLINE_SHIFT U(16) 397 #define CTR_DMINLINE_WIDTH U(4) 398 #define CTR_DMINLINE_MASK ((U(1) << 4) - U(1)) 399 #define CTR_L1IP_SHIFT U(14) 400 #define CTR_L1IP_MASK U(0x3) 401 #define CTR_IMINLINE_SHIFT U(0) 402 #define CTR_IMINLINE_MASK U(0xf) 403 404 #define MAX_CACHE_LINE_SIZE U(0x800) /* 2KB */ 405 406 /* PMCR definitions */ 407 #define PMCR_N_SHIFT U(11) 408 #define PMCR_N_MASK U(0x1f) 409 #define PMCR_N_BITS (PMCR_N_MASK << PMCR_N_SHIFT) 410 #define PMCR_LC_BIT (U(1) << 6) 411 #define PMCR_DP_BIT (U(1) << 5) 412 413 /******************************************************************************* 414 * Definitions of register offsets, fields and macros for CPU system 415 * instructions. 416 ******************************************************************************/ 417 418 #define TLBI_ADDR_SHIFT U(0) 419 #define TLBI_ADDR_MASK U(0xFFFFF000) 420 #define TLBI_ADDR(x) (((x) >> TLBI_ADDR_SHIFT) & TLBI_ADDR_MASK) 421 422 /******************************************************************************* 423 * Definitions of register offsets and fields in the CNTCTLBase Frame of the 424 * system level implementation of the Generic Timer. 425 ******************************************************************************/ 426 #define CNTCTLBASE_CNTFRQ U(0x0) 427 #define CNTNSAR U(0x4) 428 #define CNTNSAR_NS_SHIFT(x) (x) 429 430 #define CNTACR_BASE(x) (U(0x40) + ((x) << 2)) 431 #define CNTACR_RPCT_SHIFT U(0x0) 432 #define CNTACR_RVCT_SHIFT U(0x1) 433 #define CNTACR_RFRQ_SHIFT U(0x2) 434 #define CNTACR_RVOFF_SHIFT U(0x3) 435 #define CNTACR_RWVT_SHIFT U(0x4) 436 #define CNTACR_RWPT_SHIFT U(0x5) 437 438 /******************************************************************************* 439 * Definitions of register offsets and fields in the CNTBaseN Frame of the 440 * system level implementation of the Generic Timer. 441 ******************************************************************************/ 442 /* Physical Count register. */ 443 #define CNTPCT_LO U(0x0) 444 /* Counter Frequency register. */ 445 #define CNTBASEN_CNTFRQ U(0x10) 446 /* Physical Timer CompareValue register. */ 447 #define CNTP_CVAL_LO U(0x20) 448 /* Physical Timer Control register. */ 449 #define CNTP_CTL U(0x2c) 450 451 /* Physical timer control register bit fields shifts and masks */ 452 #define CNTP_CTL_ENABLE_SHIFT 0 453 #define CNTP_CTL_IMASK_SHIFT 1 454 #define CNTP_CTL_ISTATUS_SHIFT 2 455 456 #define CNTP_CTL_ENABLE_MASK U(1) 457 #define CNTP_CTL_IMASK_MASK U(1) 458 #define CNTP_CTL_ISTATUS_MASK U(1) 459 460 /* MAIR macros */ 461 #define MAIR0_ATTR_SET(attr, index) ((attr) << ((index) << U(3))) 462 #define MAIR1_ATTR_SET(attr, index) ((attr) << (((index) - U(3)) << U(3))) 463 464 /* System register defines The format is: coproc, opt1, CRn, CRm, opt2 */ 465 #define SCR p15, 0, c1, c1, 0 466 #define SCTLR p15, 0, c1, c0, 0 467 #define ACTLR p15, 0, c1, c0, 1 468 #define SDCR p15, 0, c1, c3, 1 469 #define MPIDR p15, 0, c0, c0, 5 470 #define MIDR p15, 0, c0, c0, 0 471 #define HVBAR p15, 4, c12, c0, 0 472 #define VBAR p15, 0, c12, c0, 0 473 #define MVBAR p15, 0, c12, c0, 1 474 #define NSACR p15, 0, c1, c1, 2 475 #define CPACR p15, 0, c1, c0, 2 476 #define DCCIMVAC p15, 0, c7, c14, 1 477 #define DCCMVAC p15, 0, c7, c10, 1 478 #define DCIMVAC p15, 0, c7, c6, 1 479 #define DCCISW p15, 0, c7, c14, 2 480 #define DCCSW p15, 0, c7, c10, 2 481 #define DCISW p15, 0, c7, c6, 2 482 #define CTR p15, 0, c0, c0, 1 483 #define CNTFRQ p15, 0, c14, c0, 0 484 #define ID_MMFR4 p15, 0, c0, c2, 6 485 #define ID_PFR0 p15, 0, c0, c1, 0 486 #define ID_PFR1 p15, 0, c0, c1, 1 487 #define MAIR0 p15, 0, c10, c2, 0 488 #define MAIR1 p15, 0, c10, c2, 1 489 #define TTBCR p15, 0, c2, c0, 2 490 #define TTBR0 p15, 0, c2, c0, 0 491 #define TTBR1 p15, 0, c2, c0, 1 492 #define TLBIALL p15, 0, c8, c7, 0 493 #define TLBIALLH p15, 4, c8, c7, 0 494 #define TLBIALLIS p15, 0, c8, c3, 0 495 #define TLBIMVA p15, 0, c8, c7, 1 496 #define TLBIMVAA p15, 0, c8, c7, 3 497 #define TLBIMVAAIS p15, 0, c8, c3, 3 498 #define TLBIMVAHIS p15, 4, c8, c3, 1 499 #define BPIALLIS p15, 0, c7, c1, 6 500 #define BPIALL p15, 0, c7, c5, 6 501 #define ICIALLU p15, 0, c7, c5, 0 502 #define HSCTLR p15, 4, c1, c0, 0 503 #define HCR p15, 4, c1, c1, 0 504 #define HCPTR p15, 4, c1, c1, 2 505 #define HSTR p15, 4, c1, c1, 3 506 #define CNTHCTL p15, 4, c14, c1, 0 507 #define CNTKCTL p15, 0, c14, c1, 0 508 #define VPIDR p15, 4, c0, c0, 0 509 #define VMPIDR p15, 4, c0, c0, 5 510 #define ISR p15, 0, c12, c1, 0 511 #define CLIDR p15, 1, c0, c0, 1 512 #define CSSELR p15, 2, c0, c0, 0 513 #define CCSIDR p15, 1, c0, c0, 0 514 #define HTCR p15, 4, c2, c0, 2 515 #define HMAIR0 p15, 4, c10, c2, 0 516 #define ATS1CPR p15, 0, c7, c8, 0 517 #define ATS1HR p15, 4, c7, c8, 0 518 #define DBGOSDLR p14, 0, c1, c3, 4 519 520 /* Debug register defines. The format is: coproc, opt1, CRn, CRm, opt2 */ 521 #define HDCR p15, 4, c1, c1, 1 522 #define PMCR p15, 0, c9, c12, 0 523 #define CNTHP_TVAL p15, 4, c14, c2, 0 524 #define CNTHP_CTL p15, 4, c14, c2, 1 525 526 /* AArch32 coproc registers for 32bit MMU descriptor support */ 527 #define PRRR p15, 0, c10, c2, 0 528 #define NMRR p15, 0, c10, c2, 1 529 #define DACR p15, 0, c3, c0, 0 530 531 /* GICv3 CPU Interface system register defines. The format is: coproc, opt1, CRn, CRm, opt2 */ 532 #define ICC_IAR1 p15, 0, c12, c12, 0 533 #define ICC_IAR0 p15, 0, c12, c8, 0 534 #define ICC_EOIR1 p15, 0, c12, c12, 1 535 #define ICC_EOIR0 p15, 0, c12, c8, 1 536 #define ICC_HPPIR1 p15, 0, c12, c12, 2 537 #define ICC_HPPIR0 p15, 0, c12, c8, 2 538 #define ICC_BPR1 p15, 0, c12, c12, 3 539 #define ICC_BPR0 p15, 0, c12, c8, 3 540 #define ICC_DIR p15, 0, c12, c11, 1 541 #define ICC_PMR p15, 0, c4, c6, 0 542 #define ICC_RPR p15, 0, c12, c11, 3 543 #define ICC_CTLR p15, 0, c12, c12, 4 544 #define ICC_MCTLR p15, 6, c12, c12, 4 545 #define ICC_SRE p15, 0, c12, c12, 5 546 #define ICC_HSRE p15, 4, c12, c9, 5 547 #define ICC_MSRE p15, 6, c12, c12, 5 548 #define ICC_IGRPEN0 p15, 0, c12, c12, 6 549 #define ICC_IGRPEN1 p15, 0, c12, c12, 7 550 #define ICC_MGRPEN1 p15, 6, c12, c12, 7 551 552 /* 64 bit system register defines The format is: coproc, opt1, CRm */ 553 #define TTBR0_64 p15, 0, c2 554 #define TTBR1_64 p15, 1, c2 555 #define CNTVOFF_64 p15, 4, c14 556 #define VTTBR_64 p15, 6, c2 557 #define CNTPCT_64 p15, 0, c14 558 #define HTTBR_64 p15, 4, c2 559 #define CNTHP_CVAL_64 p15, 6, c14 560 #define PAR_64 p15, 0, c7 561 562 /* 64 bit GICv3 CPU Interface system register defines. The format is: coproc, opt1, CRm */ 563 #define ICC_SGI1R_EL1_64 p15, 0, c12 564 #define ICC_ASGI1R_EL1_64 p15, 1, c12 565 #define ICC_SGI0R_EL1_64 p15, 2, c12 566 567 /******************************************************************************* 568 * Definitions of MAIR encodings for device and normal memory 569 ******************************************************************************/ 570 /* 571 * MAIR encodings for device memory attributes. 572 */ 573 #define MAIR_DEV_nGnRnE U(0x0) 574 #define MAIR_DEV_nGnRE U(0x4) 575 #define MAIR_DEV_nGRE U(0x8) 576 #define MAIR_DEV_GRE U(0xc) 577 578 /* 579 * MAIR encodings for normal memory attributes. 580 * 581 * Cache Policy 582 * WT: Write Through 583 * WB: Write Back 584 * NC: Non-Cacheable 585 * 586 * Transient Hint 587 * NTR: Non-Transient 588 * TR: Transient 589 * 590 * Allocation Policy 591 * RA: Read Allocate 592 * WA: Write Allocate 593 * RWA: Read and Write Allocate 594 * NA: No Allocation 595 */ 596 #define MAIR_NORM_WT_TR_WA U(0x1) 597 #define MAIR_NORM_WT_TR_RA U(0x2) 598 #define MAIR_NORM_WT_TR_RWA U(0x3) 599 #define MAIR_NORM_NC U(0x4) 600 #define MAIR_NORM_WB_TR_WA U(0x5) 601 #define MAIR_NORM_WB_TR_RA U(0x6) 602 #define MAIR_NORM_WB_TR_RWA U(0x7) 603 #define MAIR_NORM_WT_NTR_NA U(0x8) 604 #define MAIR_NORM_WT_NTR_WA U(0x9) 605 #define MAIR_NORM_WT_NTR_RA U(0xa) 606 #define MAIR_NORM_WT_NTR_RWA U(0xb) 607 #define MAIR_NORM_WB_NTR_NA U(0xc) 608 #define MAIR_NORM_WB_NTR_WA U(0xd) 609 #define MAIR_NORM_WB_NTR_RA U(0xe) 610 #define MAIR_NORM_WB_NTR_RWA U(0xf) 611 612 #define MAIR_NORM_OUTER_SHIFT U(4) 613 614 #define MAKE_MAIR_NORMAL_MEMORY(inner, outer) \ 615 ((inner) | ((outer) << MAIR_NORM_OUTER_SHIFT)) 616 617 /* PAR fields */ 618 #define PAR_F_SHIFT U(0) 619 #define PAR_F_MASK ULL(0x1) 620 #define PAR_ADDR_SHIFT U(12) 621 #define PAR_ADDR_MASK (BIT_64(40) - ULL(1)) /* 40-bits-wide page address */ 622 623 /******************************************************************************* 624 * Definitions for system register interface to AMU for ARMv8.4 onwards 625 ******************************************************************************/ 626 #define AMCR p15, 0, c13, c2, 0 627 #define AMCFGR p15, 0, c13, c2, 1 628 #define AMCGCR p15, 0, c13, c2, 2 629 #define AMUSERENR p15, 0, c13, c2, 3 630 #define AMCNTENCLR0 p15, 0, c13, c2, 4 631 #define AMCNTENSET0 p15, 0, c13, c2, 5 632 #define AMCNTENCLR1 p15, 0, c13, c3, 0 633 #define AMCNTENSET1 p15, 0, c13, c3, 1 634 635 /* Activity Monitor Group 0 Event Counter Registers */ 636 #define AMEVCNTR00 p15, 0, c0 637 #define AMEVCNTR01 p15, 1, c0 638 #define AMEVCNTR02 p15, 2, c0 639 #define AMEVCNTR03 p15, 3, c0 640 641 /* Activity Monitor Group 0 Event Type Registers */ 642 #define AMEVTYPER00 p15, 0, c13, c6, 0 643 #define AMEVTYPER01 p15, 0, c13, c6, 1 644 #define AMEVTYPER02 p15, 0, c13, c6, 2 645 #define AMEVTYPER03 p15, 0, c13, c6, 3 646 647 /* Activity Monitor Group 1 Event Counter Registers */ 648 #define AMEVCNTR10 p15, 0, c4 649 #define AMEVCNTR11 p15, 1, c4 650 #define AMEVCNTR12 p15, 2, c4 651 #define AMEVCNTR13 p15, 3, c4 652 #define AMEVCNTR14 p15, 4, c4 653 #define AMEVCNTR15 p15, 5, c4 654 #define AMEVCNTR16 p15, 6, c4 655 #define AMEVCNTR17 p15, 7, c4 656 #define AMEVCNTR18 p15, 0, c5 657 #define AMEVCNTR19 p15, 1, c5 658 #define AMEVCNTR1A p15, 2, c5 659 #define AMEVCNTR1B p15, 3, c5 660 #define AMEVCNTR1C p15, 4, c5 661 #define AMEVCNTR1D p15, 5, c5 662 #define AMEVCNTR1E p15, 6, c5 663 #define AMEVCNTR1F p15, 7, c5 664 665 /* Activity Monitor Group 1 Event Type Registers */ 666 #define AMEVTYPER10 p15, 0, c13, c14, 0 667 #define AMEVTYPER11 p15, 0, c13, c14, 1 668 #define AMEVTYPER12 p15, 0, c13, c14, 2 669 #define AMEVTYPER13 p15, 0, c13, c14, 3 670 #define AMEVTYPER14 p15, 0, c13, c14, 4 671 #define AMEVTYPER15 p15, 0, c13, c14, 5 672 #define AMEVTYPER16 p15, 0, c13, c14, 6 673 #define AMEVTYPER17 p15, 0, c13, c14, 7 674 #define AMEVTYPER18 p15, 0, c13, c15, 0 675 #define AMEVTYPER19 p15, 0, c13, c15, 1 676 #define AMEVTYPER1A p15, 0, c13, c15, 2 677 #define AMEVTYPER1B p15, 0, c13, c15, 3 678 #define AMEVTYPER1C p15, 0, c13, c15, 4 679 #define AMEVTYPER1D p15, 0, c13, c15, 5 680 #define AMEVTYPER1E p15, 0, c13, c15, 6 681 #define AMEVTYPER1F p15, 0, c13, c15, 7 682 683 #endif /* ARCH_H */ 684