xref: /rk3399_ARM-atf/fdts/tc-fpga.dtsi (revision e6ef3ef0f637b52f60aa383bdea9a59bfc03c8e5)
14e772e6bSLeo Yan/*
24e772e6bSLeo Yan * Copyright (c) 2023-2024, Arm Limited. All rights reserved.
34e772e6bSLeo Yan *
44e772e6bSLeo Yan * SPDX-License-Identifier: BSD-3-Clause
54e772e6bSLeo Yan */
64e772e6bSLeo Yan
74e772e6bSLeo Yan#define GIC_CTRL_ADDR		30000000
84e772e6bSLeo Yan#define GIC_GICR_OFFSET		0x1000000
94e772e6bSLeo Yan#define UART_OFFSET		0x10000
104e772e6bSLeo Yan/* 1440x3200@120 framebuffer */
114e772e6bSLeo Yan#define VENCODER_TIMING_CLK 836000000
124e772e6bSLeo Yan#define VENCODER_TIMING								\
134e772e6bSLeo Yan	clock-frequency = <VENCODER_TIMING_CLK>;				\
144e772e6bSLeo Yan	hactive = <1440>;							\
154e772e6bSLeo Yan	vactive = <3200>;							\
164e772e6bSLeo Yan	hfront-porch = <136>;							\
174e772e6bSLeo Yan	hback-porch = <296>;							\
184e772e6bSLeo Yan	hsync-len = <160>;							\
194e772e6bSLeo Yan	vfront-porch = <3>;							\
204e772e6bSLeo Yan	vback-porch = <217>;							\
214e772e6bSLeo Yan	vsync-len = <10>
22*e6ef3ef0SLeo Yan
23*e6ef3ef0SLeo Yan/ {
24*e6ef3ef0SLeo Yan	chosen {
25*e6ef3ef0SLeo Yan		stdout-path = "serial0:38400n8";
26*e6ef3ef0SLeo Yan	};
27*e6ef3ef0SLeo Yan
28*e6ef3ef0SLeo Yan	ethernet: ethernet@18000000 {
29*e6ef3ef0SLeo Yan		compatible = "smsc,lan9115";
30*e6ef3ef0SLeo Yan		phy-mode = "mii";
31*e6ef3ef0SLeo Yan	};
32*e6ef3ef0SLeo Yan
33*e6ef3ef0SLeo Yan	mmci: mmci@1c050000 {
34*e6ef3ef0SLeo Yan		non-removable;
35*e6ef3ef0SLeo Yan	};
36*e6ef3ef0SLeo Yan};
37