1// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) 2/* 3 * Copyright (C) 2025, Ultratronik GmbH 4 * Copyright (C) STMicroelectronics 2025 - All Rights Reserved 5 * Author: Boerge Struempfel <boerge.struempfel@gmail.com> for Ultratronik GmbH. 6 */ 7 8&clk_hse { 9 clock-frequency = <40000000>; 10}; 11 12&clk_hsi { 13 clock-frequency = <64000000>; 14}; 15 16&clk_lse { 17 clock-frequency = <32768>; 18}; 19 20&clk_lsi { 21 clock-frequency = <32000>; 22}; 23 24&clk_msi { 25 clock-frequency = <16000000>; 26}; 27 28&rcc { 29 st,busclk = < 30 DIV_CFG(DIV_LSMCU, 1) 31 DIV_CFG(DIV_APB1, 0) 32 DIV_CFG(DIV_APB2, 0) 33 DIV_CFG(DIV_APB3, 0) 34 DIV_CFG(DIV_APB4, 0) 35 DIV_CFG(DIV_APBDBG, 0) 36 >; 37 38 st,flexgen = < 39 FLEXGEN_CFG(0, XBAR_SRC_PLL4, 0, 2) 40 FLEXGEN_CFG(1, XBAR_SRC_PLL4, 0, 5) 41 FLEXGEN_CFG(2, XBAR_SRC_PLL4, 0, 1) 42 FLEXGEN_CFG(4, XBAR_SRC_PLL4, 0, 3) 43 FLEXGEN_CFG(5, XBAR_SRC_PLL4, 0, 2) 44 FLEXGEN_CFG(19, XBAR_SRC_HSI_KER, 0, 0) 45 FLEXGEN_CFG(48, XBAR_SRC_PLL5, 0, 3) 46 FLEXGEN_CFG(51, XBAR_SRC_PLL4, 0, 5) 47 FLEXGEN_CFG(52, XBAR_SRC_PLL4, 0, 5) 48 FLEXGEN_CFG(58, XBAR_SRC_HSE_KER, 0, 1) 49 FLEXGEN_CFG(63, XBAR_SRC_PLL4, 0, 2) 50 >; 51 52 st,kerclk = < 53 MUX_CFG(MUX_USB2PHY1, MUX_USB2PHY1_FLEX57) 54 MUX_CFG(MUX_USB2PHY2, MUX_USB2PHY2_FLEX58) 55 >; 56 57 pll1: st,pll-1 { 58 st,pll = <&pll1_cfg_1200Mhz>; 59 60 pll1_cfg_1200Mhz: pll1-cfg-1200Mhz { 61 cfg = <30 1 1 1>; 62 src = <MUX_CFG(MUX_MUXSEL5, MUXSEL_HSE)>; 63 }; 64 }; 65 66 pll2: st,pll-2 { 67 st,pll = <&pll2_cfg_600Mhz>; 68 69 pll2_cfg_600Mhz: pll2-cfg-600Mhz { 70 cfg = <30 1 1 2>; 71 src = <MUX_CFG(MUX_MUXSEL6, MUXSEL_HSE)>; 72 }; 73 }; 74 75 pll4: st,pll-4 { 76 st,pll = <&pll4_cfg_1200Mhz>; 77 78 pll4_cfg_1200Mhz: pll4-cfg-1200Mhz { 79 cfg = <30 1 1 1>; 80 src = <MUX_CFG(MUX_MUXSEL0, MUXSEL_HSE)>; 81 }; 82 }; 83 84 pll5: st,pll-5 { 85 st,pll = <&pll5_cfg_532Mhz>; 86 87 pll5_cfg_532Mhz: pll5-cfg-532Mhz { 88 cfg = <133 5 1 2>; 89 src = <MUX_CFG(MUX_MUXSEL1, MUXSEL_HSE)>; 90 }; 91 }; 92}; 93