1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved 4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics. 5 */ 6/dts-v1/; 7 8#include "stm32mp157c.dtsi" 9#include "stm32mp157caa-pinctrl.dtsi" 10 11/ { 12 model = "STMicroelectronics STM32MP157C eval daughter"; 13 compatible = "st,stm32mp157c-ed1", "st,stm32mp157"; 14 15 chosen { 16 stdout-path = "serial0:115200n8"; 17 }; 18 19 aliases { 20 serial0 = &uart4; 21 }; 22}; 23 24&clk_hse { 25 st,digbypass; 26}; 27 28&i2c4 { 29 pinctrl-names = "default"; 30 pinctrl-0 = <&i2c4_pins_a>; 31 i2c-scl-rising-time-ns = <185>; 32 i2c-scl-falling-time-ns = <20>; 33 status = "okay"; 34 35 pmic: stpmic@33 { 36 compatible = "st,stpmic1"; 37 reg = <0x33>; 38 interrupts-extended = <&exti_pwr 55 IRQ_TYPE_EDGE_FALLING>; 39 interrupt-controller; 40 #interrupt-cells = <2>; 41 status = "okay"; 42 43 st,main-control-register = <0x04>; 44 st,vin-control-register = <0xc0>; 45 st,usb-control-register = <0x30>; 46 47 regulators { 48 compatible = "st,stpmic1-regulators"; 49 50 ldo1-supply = <&v3v3>; 51 ldo2-supply = <&v3v3>; 52 ldo3-supply = <&vdd_ddr>; 53 ldo5-supply = <&v3v3>; 54 ldo6-supply = <&v3v3>; 55 56 vddcore: buck1 { 57 regulator-name = "vddcore"; 58 regulator-min-microvolt = <800000>; 59 regulator-max-microvolt = <1350000>; 60 regulator-always-on; 61 regulator-initial-mode = <0>; 62 regulator-over-current-protection; 63 }; 64 65 vdd_ddr: buck2 { 66 regulator-name = "vdd_ddr"; 67 regulator-min-microvolt = <1350000>; 68 regulator-max-microvolt = <1350000>; 69 regulator-always-on; 70 regulator-initial-mode = <0>; 71 regulator-over-current-protection; 72 }; 73 74 vdd: buck3 { 75 regulator-name = "vdd"; 76 regulator-min-microvolt = <3300000>; 77 regulator-max-microvolt = <3300000>; 78 regulator-always-on; 79 st,mask-reset; 80 regulator-initial-mode = <0>; 81 regulator-over-current-protection; 82 }; 83 84 v3v3: buck4 { 85 regulator-name = "v3v3"; 86 regulator-min-microvolt = <3300000>; 87 regulator-max-microvolt = <3300000>; 88 regulator-always-on; 89 regulator-over-current-protection; 90 regulator-initial-mode = <0>; 91 }; 92 93 vdda: ldo1 { 94 regulator-name = "vdda"; 95 regulator-min-microvolt = <2900000>; 96 regulator-max-microvolt = <2900000>; 97 }; 98 99 v2v8: ldo2 { 100 regulator-name = "v2v8"; 101 regulator-min-microvolt = <2800000>; 102 regulator-max-microvolt = <2800000>; 103 }; 104 105 vtt_ddr: ldo3 { 106 regulator-name = "vtt_ddr"; 107 regulator-min-microvolt = <500000>; 108 regulator-max-microvolt = <750000>; 109 regulator-always-on; 110 regulator-over-current-protection; 111 }; 112 113 vdd_usb: ldo4 { 114 regulator-name = "vdd_usb"; 115 regulator-min-microvolt = <3300000>; 116 regulator-max-microvolt = <3300000>; 117 }; 118 119 vdd_sd: ldo5 { 120 regulator-name = "vdd_sd"; 121 regulator-min-microvolt = <2900000>; 122 regulator-max-microvolt = <2900000>; 123 regulator-boot-on; 124 }; 125 126 v1v8: ldo6 { 127 regulator-name = "v1v8"; 128 regulator-min-microvolt = <1800000>; 129 regulator-max-microvolt = <1800000>; 130 }; 131 132 vref_ddr: vref_ddr { 133 regulator-name = "vref_ddr"; 134 regulator-always-on; 135 regulator-over-current-protection; 136 }; 137 }; 138 }; 139}; 140 141&iwdg2 { 142 timeout-sec = <32>; 143 status = "okay"; 144}; 145 146&rng1 { 147 status = "okay"; 148}; 149 150&rtc { 151 status = "okay"; 152}; 153 154&sdmmc1 { 155 pinctrl-names = "default"; 156 pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>; 157 broken-cd; 158 st,sig-dir; 159 st,neg-edge; 160 st,use-ckin; 161 bus-width = <4>; 162 vmmc-supply = <&vdd_sd>; 163 sd-uhs-sdr12; 164 sd-uhs-sdr25; 165 sd-uhs-sdr50; 166 sd-uhs-ddr50; 167 sd-uhs-sdr104; 168 status = "okay"; 169}; 170 171&sdmmc2 { 172 pinctrl-names = "default"; 173 pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>; 174 non-removable; 175 no-sd; 176 no-sdio; 177 st,neg-edge; 178 bus-width = <8>; 179 vmmc-supply = <&v3v3>; 180 vqmmc-supply = <&v3v3>; 181 mmc-ddr-3_3v; 182 status = "okay"; 183}; 184 185&uart4 { 186 pinctrl-names = "default"; 187 pinctrl-0 = <&uart4_pins_a>; 188 status = "okay"; 189}; 190 191/* ATF Specific */ 192#include <dt-bindings/clock/stm32mp1-clksrc.h> 193#include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi" 194 195/ { 196 aliases { 197 gpio0 = &gpioa; 198 gpio1 = &gpiob; 199 gpio2 = &gpioc; 200 gpio3 = &gpiod; 201 gpio4 = &gpioe; 202 gpio5 = &gpiof; 203 gpio6 = &gpiog; 204 gpio7 = &gpioh; 205 gpio8 = &gpioi; 206 gpio9 = &gpioj; 207 gpio10 = &gpiok; 208 gpio25 = &gpioz; 209 i2c3 = &i2c4; 210 }; 211 212 soc { 213 stgen: stgen@5C008000 { 214 compatible = "st,stm32-stgen"; 215 reg = <0x5C008000 0x1000>; 216 status = "okay"; 217 }; 218 }; 219}; 220 221/* CLOCK init */ 222&rcc { 223 secure-status = "disabled"; 224 st,clksrc = < 225 CLK_MPU_PLL1P 226 CLK_AXI_PLL2P 227 CLK_PLL12_HSE 228 CLK_PLL3_HSE 229 CLK_PLL4_HSE 230 CLK_RTC_LSE 231 CLK_MCO1_DISABLED 232 CLK_MCO2_DISABLED 233 >; 234 235 st,clkdiv = < 236 1 /*MPU*/ 237 0 /*AXI*/ 238 1 /*APB1*/ 239 1 /*APB2*/ 240 1 /*APB3*/ 241 1 /*APB4*/ 242 2 /*APB5*/ 243 23 /*RTC*/ 244 0 /*MCO1*/ 245 0 /*MCO2*/ 246 >; 247 248 st,pkcs = < 249 CLK_CKPER_HSE 250 CLK_FMC_ACLK 251 CLK_QSPI_ACLK 252 CLK_ETH_DISABLED 253 CLK_SDMMC12_PLL4P 254 CLK_DSI_DSIPLL 255 CLK_STGEN_HSE 256 CLK_USBPHY_HSE 257 CLK_SPI2S1_PLL3Q 258 CLK_SPI2S23_PLL3Q 259 CLK_SPI45_HSI 260 CLK_SPI6_HSI 261 CLK_I2C46_HSI 262 CLK_SDMMC3_PLL4P 263 CLK_USBO_USBPHY 264 CLK_ADC_CKPER 265 CLK_CEC_LSE 266 CLK_I2C12_HSI 267 CLK_I2C35_HSI 268 CLK_UART1_HSI 269 CLK_UART24_HSI 270 CLK_UART35_HSI 271 CLK_UART6_HSI 272 CLK_UART78_HSI 273 CLK_SPDIF_PLL4P 274 CLK_FDCAN_PLL4Q 275 CLK_SAI1_PLL3Q 276 CLK_SAI2_PLL3Q 277 CLK_SAI3_PLL3Q 278 CLK_SAI4_PLL3Q 279 CLK_RNG1_LSI 280 CLK_RNG2_LSI 281 CLK_LPTIM1_PCLK1 282 CLK_LPTIM23_PCLK3 283 CLK_LPTIM45_LSE 284 >; 285 286 /* VCO = 1300.0 MHz => P = 650 (CPU) */ 287 pll1: st,pll@0 { 288 cfg = < 2 80 0 0 0 PQR(1,0,0) >; 289 frac = < 0x800 >; 290 }; 291 292 /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */ 293 pll2: st,pll@1 { 294 cfg = < 2 65 1 0 0 PQR(1,1,1) >; 295 frac = < 0x1400 >; 296 }; 297 298 /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */ 299 pll3: st,pll@2 { 300 cfg = < 1 33 1 16 36 PQR(1,1,1) >; 301 frac = < 0x1a04 >; 302 }; 303 304 /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */ 305 pll4: st,pll@3 { 306 cfg = < 3 98 5 7 7 PQR(1,1,1) >; 307 }; 308}; 309 310/delete-node/ &clk_csi; 311