1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright (c) 2017-2024, STMicroelectronics - All Rights Reserved 4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics. 5 */ 6/dts-v1/; 7 8#include "stm32mp157.dtsi" 9#include "stm32mp15xc.dtsi" 10#include "stm32mp15-pinctrl.dtsi" 11#include "stm32mp15xxaa-pinctrl.dtsi" 12#include <dt-bindings/clock/stm32mp1-clksrc.h> 13#include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi" 14 15/ { 16 model = "STMicroelectronics STM32MP157C eval daughter"; 17 compatible = "st,stm32mp157c-ed1", "st,stm32mp157"; 18 19 aliases { 20 serial0 = &uart4; 21 }; 22 23 chosen { 24 stdout-path = "serial0:115200n8"; 25 }; 26 27 memory@c0000000 { 28 device_type = "memory"; 29 reg = <0xC0000000 0x40000000>; 30 }; 31}; 32 33&bsec { 34 board_id: board-id@ec { 35 reg = <0xec 0x4>; 36 st,non-secure-otp; 37 }; 38}; 39 40&clk_hse { 41 st,digbypass; 42}; 43 44&cpu0 { 45 cpu-supply = <&vddcore>; 46}; 47 48&cpu1 { 49 cpu-supply = <&vddcore>; 50}; 51 52&cryp1 { 53 status = "okay"; 54}; 55 56&hash1 { 57 status = "okay"; 58}; 59 60&i2c4 { 61 pinctrl-names = "default"; 62 pinctrl-0 = <&i2c4_pins_a>; 63 i2c-scl-rising-time-ns = <185>; 64 i2c-scl-falling-time-ns = <20>; 65 clock-frequency = <400000>; 66 status = "okay"; 67 68 pmic: stpmic@33 { 69 compatible = "st,stpmic1"; 70 reg = <0x33>; 71 interrupts-extended = <&exti_pwr 55 IRQ_TYPE_EDGE_FALLING>; 72 interrupt-controller; 73 #interrupt-cells = <2>; 74 status = "okay"; 75 76 regulators { 77 compatible = "st,stpmic1-regulators"; 78 ldo1-supply = <&v3v3>; 79 ldo2-supply = <&v3v3>; 80 ldo3-supply = <&vdd_ddr>; 81 ldo5-supply = <&v3v3>; 82 ldo6-supply = <&v3v3>; 83 pwr_sw1-supply = <&bst_out>; 84 pwr_sw2-supply = <&bst_out>; 85 86 vddcore: buck1 { 87 regulator-name = "vddcore"; 88 regulator-min-microvolt = <1200000>; 89 regulator-max-microvolt = <1350000>; 90 regulator-always-on; 91 regulator-initial-mode = <0>; 92 regulator-over-current-protection; 93 }; 94 95 vdd_ddr: buck2 { 96 regulator-name = "vdd_ddr"; 97 regulator-min-microvolt = <1350000>; 98 regulator-max-microvolt = <1350000>; 99 regulator-always-on; 100 regulator-initial-mode = <0>; 101 regulator-over-current-protection; 102 }; 103 104 vdd: buck3 { 105 regulator-name = "vdd"; 106 regulator-min-microvolt = <3300000>; 107 regulator-max-microvolt = <3300000>; 108 regulator-always-on; 109 st,mask-reset; 110 regulator-initial-mode = <0>; 111 regulator-over-current-protection; 112 }; 113 114 v3v3: buck4 { 115 regulator-name = "v3v3"; 116 regulator-min-microvolt = <3300000>; 117 regulator-max-microvolt = <3300000>; 118 regulator-always-on; 119 regulator-over-current-protection; 120 regulator-initial-mode = <0>; 121 }; 122 123 vdda: ldo1 { 124 regulator-name = "vdda"; 125 regulator-min-microvolt = <2900000>; 126 regulator-max-microvolt = <2900000>; 127 }; 128 129 v2v8: ldo2 { 130 regulator-name = "v2v8"; 131 regulator-min-microvolt = <2800000>; 132 regulator-max-microvolt = <2800000>; 133 }; 134 135 vtt_ddr: ldo3 { 136 regulator-name = "vtt_ddr"; 137 regulator-always-on; 138 regulator-over-current-protection; 139 st,regulator-sink-source; 140 }; 141 142 vdd_usb: ldo4 { 143 regulator-name = "vdd_usb"; 144 regulator-min-microvolt = <3300000>; 145 regulator-max-microvolt = <3300000>; 146 }; 147 148 vdd_sd: ldo5 { 149 regulator-name = "vdd_sd"; 150 regulator-min-microvolt = <2900000>; 151 regulator-max-microvolt = <2900000>; 152 regulator-boot-on; 153 }; 154 155 v1v8: ldo6 { 156 regulator-name = "v1v8"; 157 regulator-min-microvolt = <1800000>; 158 regulator-max-microvolt = <1800000>; 159 }; 160 161 vref_ddr: vref_ddr { 162 regulator-name = "vref_ddr"; 163 regulator-always-on; 164 }; 165 166 bst_out: boost { 167 regulator-name = "bst_out"; 168 }; 169 170 vbus_otg: pwr_sw1 { 171 regulator-name = "vbus_otg"; 172 }; 173 174 vbus_sw: pwr_sw2 { 175 regulator-name = "vbus_sw"; 176 regulator-active-discharge = <1>; 177 }; 178 }; 179 }; 180}; 181 182&iwdg2 { 183 timeout-sec = <32>; 184 status = "okay"; 185}; 186 187&pwr_regulators { 188 vdd-supply = <&vdd>; 189 vdd_3v3_usbfs-supply = <&vdd_usb>; 190}; 191 192&rcc { 193 st,clksrc = < 194 CLK_MPU_PLL1P 195 CLK_AXI_PLL2P 196 CLK_MCU_PLL3P 197 CLK_RTC_LSE 198 CLK_MCO1_DISABLED 199 CLK_MCO2_DISABLED 200 CLK_CKPER_HSE 201 CLK_FMC_ACLK 202 CLK_QSPI_ACLK 203 CLK_ETH_PLL4P 204 CLK_SDMMC12_PLL4P 205 CLK_DSI_DSIPLL 206 CLK_STGEN_HSE 207 CLK_USBPHY_HSE 208 CLK_SPI2S1_PLL3Q 209 CLK_SPI2S23_PLL3Q 210 CLK_SPI45_HSI 211 CLK_SPI6_HSI 212 CLK_I2C46_HSI 213 CLK_SDMMC3_PLL4P 214 CLK_USBO_USBPHY 215 CLK_ADC_CKPER 216 CLK_CEC_LSE 217 CLK_I2C12_HSI 218 CLK_I2C35_HSI 219 CLK_UART1_HSI 220 CLK_UART24_HSI 221 CLK_UART35_HSI 222 CLK_UART6_HSI 223 CLK_UART78_HSI 224 CLK_SPDIF_PLL4P 225 CLK_FDCAN_PLL4R 226 CLK_SAI1_PLL3Q 227 CLK_SAI2_PLL3Q 228 CLK_SAI3_PLL3Q 229 CLK_SAI4_PLL3Q 230 CLK_RNG1_CSI 231 CLK_RNG2_LSI 232 CLK_LPTIM1_PCLK1 233 CLK_LPTIM23_PCLK3 234 CLK_LPTIM45_LSE 235 >; 236 237 st,clkdiv = < 238 DIV(DIV_MPU, 1) 239 DIV(DIV_AXI, 0) 240 DIV(DIV_MCU, 0) 241 DIV(DIV_APB1, 1) 242 DIV(DIV_APB2, 1) 243 DIV(DIV_APB3, 1) 244 DIV(DIV_APB4, 1) 245 DIV(DIV_APB5, 2) 246 DIV(DIV_RTC, 23) 247 DIV(DIV_MCO1, 0) 248 DIV(DIV_MCO2, 0) 249 >; 250 251 st,pll_vco { 252 pll1_vco_1300Mhz: pll1-vco-1300Mhz { 253 src = < CLK_PLL12_HSE >; 254 divmn = < 2 80 >; 255 frac = < 0x800 >; 256 }; 257 258 pll2_vco_1066Mhz: pll2-vco-1066Mhz { 259 src = <CLK_PLL12_HSE>; 260 divmn = <2 65>; 261 frac = <0x1400>; 262 }; 263 264 pll3_vco_417Mhz: pll3-vco-417Mhz { 265 src = <CLK_PLL3_HSE>; 266 divmn = <1 33>; 267 frac = <0x1a04>; 268 }; 269 270 pll4_vco_594Mhz: pll4-vco-594Mhz { 271 src = <CLK_PLL4_HSE>; 272 divmn = <3 98>; 273 }; 274 }; 275 276 /* VCO = 1300.0 MHz => P = 650 (CPU) */ 277 pll1: st,pll@0 { 278 compatible = "st,stm32mp1-pll"; 279 reg = <0>; 280 281 st,pll = < &pll1_cfg1 >; 282 283 pll1_cfg1: pll1_cfg1 { 284 st,pll_vco = < &pll1_vco_1300Mhz >; 285 st,pll_div_pqr = < 0 0 0 >; 286 }; 287 }; 288 289 /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */ 290 pll2: st,pll@1 { 291 compatible = "st,stm32mp1-pll"; 292 reg = <1>; 293 294 st,pll = <&pll2_cfg1>; 295 296 pll2_cfg1: pll2_cfg1 { 297 st,pll_vco = <&pll2_vco_1066Mhz>; 298 st,pll_div_pqr = <1 0 0>; 299 }; 300 }; 301 302 /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */ 303 pll3: st,pll@2 { 304 compatible = "st,stm32mp1-pll"; 305 reg = <2>; 306 307 st,pll = <&pll3_cfg1>; 308 309 pll3_cfg1: pll3_cfg1 { 310 st,pll_vco = <&pll3_vco_417Mhz>; 311 st,pll_div_pqr = <1 16 36>; 312 }; 313 }; 314 315 /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */ 316 pll4: st,pll@3 { 317 compatible = "st,stm32mp1-pll"; 318 reg = <3>; 319 320 st,pll = <&pll4_cfg1>; 321 322 pll4_cfg1: pll4_cfg1 { 323 st,pll_vco = <&pll4_vco_594Mhz>; 324 st,pll_div_pqr = <5 7 7>; 325 }; 326 }; 327}; 328 329&rng1 { 330 status = "okay"; 331}; 332 333&rtc { 334 status = "okay"; 335}; 336 337&sdmmc1 { 338 pinctrl-names = "default"; 339 pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>; 340 disable-wp; 341 st,sig-dir; 342 st,neg-edge; 343 st,use-ckin; 344 bus-width = <4>; 345 vmmc-supply = <&vdd_sd>; 346 sd-uhs-sdr12; 347 sd-uhs-sdr25; 348 sd-uhs-sdr50; 349 sd-uhs-ddr50; 350 status = "okay"; 351}; 352 353&sdmmc2 { 354 pinctrl-names = "default"; 355 pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>; 356 non-removable; 357 no-sd; 358 no-sdio; 359 st,neg-edge; 360 bus-width = <8>; 361 vmmc-supply = <&v3v3>; 362 vqmmc-supply = <&vdd>; 363 mmc-ddr-3_3v; 364 status = "okay"; 365}; 366 367&uart4 { 368 pinctrl-names = "default"; 369 pinctrl-0 = <&uart4_pins_a>; 370 status = "okay"; 371}; 372