1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright (c) 2017-2021, STMicroelectronics - All Rights Reserved 4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics. 5 */ 6/dts-v1/; 7 8#include "stm32mp157.dtsi" 9#include "stm32mp15xc.dtsi" 10#include "stm32mp15-pinctrl.dtsi" 11#include "stm32mp15xxaa-pinctrl.dtsi" 12#include <dt-bindings/clock/stm32mp1-clksrc.h> 13#include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi" 14 15/ { 16 model = "STMicroelectronics STM32MP157C eval daughter"; 17 compatible = "st,stm32mp157c-ed1", "st,stm32mp157"; 18 19 chosen { 20 stdout-path = "serial0:115200n8"; 21 }; 22 23 memory@c0000000 { 24 device_type = "memory"; 25 reg = <0xC0000000 0x40000000>; 26 }; 27 28 aliases { 29 serial0 = &uart4; 30 }; 31}; 32 33&bsec { 34 board_id: board_id@ec { 35 reg = <0xec 0x4>; 36 status = "okay"; 37 secure-status = "okay"; 38 }; 39}; 40 41&clk_hse { 42 st,digbypass; 43}; 44 45&cpu0 { 46 cpu-supply = <&vddcore>; 47}; 48 49&cpu1 { 50 cpu-supply = <&vddcore>; 51}; 52 53&cryp1 { 54 status = "okay"; 55}; 56 57&hash1 { 58 status = "okay"; 59}; 60 61&i2c4 { 62 pinctrl-names = "default"; 63 pinctrl-0 = <&i2c4_pins_a>; 64 i2c-scl-rising-time-ns = <185>; 65 i2c-scl-falling-time-ns = <20>; 66 clock-frequency = <400000>; 67 status = "okay"; 68 69 pmic: stpmic@33 { 70 compatible = "st,stpmic1"; 71 reg = <0x33>; 72 interrupts-extended = <&exti_pwr 55 IRQ_TYPE_EDGE_FALLING>; 73 interrupt-controller; 74 #interrupt-cells = <2>; 75 status = "okay"; 76 77 regulators { 78 compatible = "st,stpmic1-regulators"; 79 ldo1-supply = <&v3v3>; 80 ldo2-supply = <&v3v3>; 81 ldo3-supply = <&vdd_ddr>; 82 ldo5-supply = <&v3v3>; 83 ldo6-supply = <&v3v3>; 84 pwr_sw1-supply = <&bst_out>; 85 pwr_sw2-supply = <&bst_out>; 86 87 vddcore: buck1 { 88 regulator-name = "vddcore"; 89 regulator-min-microvolt = <1200000>; 90 regulator-max-microvolt = <1350000>; 91 regulator-always-on; 92 regulator-initial-mode = <0>; 93 regulator-over-current-protection; 94 }; 95 96 vdd_ddr: buck2 { 97 regulator-name = "vdd_ddr"; 98 regulator-min-microvolt = <1350000>; 99 regulator-max-microvolt = <1350000>; 100 regulator-always-on; 101 regulator-initial-mode = <0>; 102 regulator-over-current-protection; 103 }; 104 105 vdd: buck3 { 106 regulator-name = "vdd"; 107 regulator-min-microvolt = <3300000>; 108 regulator-max-microvolt = <3300000>; 109 regulator-always-on; 110 st,mask-reset; 111 regulator-initial-mode = <0>; 112 regulator-over-current-protection; 113 }; 114 115 v3v3: buck4 { 116 regulator-name = "v3v3"; 117 regulator-min-microvolt = <3300000>; 118 regulator-max-microvolt = <3300000>; 119 regulator-always-on; 120 regulator-over-current-protection; 121 regulator-initial-mode = <0>; 122 }; 123 124 vdda: ldo1 { 125 regulator-name = "vdda"; 126 regulator-min-microvolt = <2900000>; 127 regulator-max-microvolt = <2900000>; 128 }; 129 130 v2v8: ldo2 { 131 regulator-name = "v2v8"; 132 regulator-min-microvolt = <2800000>; 133 regulator-max-microvolt = <2800000>; 134 }; 135 136 vtt_ddr: ldo3 { 137 regulator-name = "vtt_ddr"; 138 regulator-always-on; 139 regulator-over-current-protection; 140 st,regulator-sink-source; 141 }; 142 143 vdd_usb: ldo4 { 144 regulator-name = "vdd_usb"; 145 regulator-min-microvolt = <3300000>; 146 regulator-max-microvolt = <3300000>; 147 }; 148 149 vdd_sd: ldo5 { 150 regulator-name = "vdd_sd"; 151 regulator-min-microvolt = <2900000>; 152 regulator-max-microvolt = <2900000>; 153 regulator-boot-on; 154 }; 155 156 v1v8: ldo6 { 157 regulator-name = "v1v8"; 158 regulator-min-microvolt = <1800000>; 159 regulator-max-microvolt = <1800000>; 160 }; 161 162 vref_ddr: vref_ddr { 163 regulator-name = "vref_ddr"; 164 regulator-always-on; 165 }; 166 167 bst_out: boost { 168 regulator-name = "bst_out"; 169 }; 170 171 vbus_otg: pwr_sw1 { 172 regulator-name = "vbus_otg"; 173 }; 174 175 vbus_sw: pwr_sw2 { 176 regulator-name = "vbus_sw"; 177 regulator-active-discharge = <1>; 178 }; 179 }; 180 181 onkey { 182 compatible = "st,stpmic1-onkey"; 183 power-off-time-sec = <10>; 184 status = "okay"; 185 }; 186 187 watchdog { 188 compatible = "st,stpmic1-wdt"; 189 status = "disabled"; 190 }; 191 }; 192}; 193 194&iwdg2 { 195 timeout-sec = <32>; 196 status = "okay"; 197}; 198 199&pwr_regulators { 200 vdd-supply = <&vdd>; 201 vdd_3v3_usbfs-supply = <&vdd_usb>; 202}; 203 204&rcc { 205 secure-status = "disabled"; 206 st,clksrc = < 207 CLK_MPU_PLL1P 208 CLK_AXI_PLL2P 209 CLK_MCU_PLL3P 210 CLK_PLL12_HSE 211 CLK_PLL3_HSE 212 CLK_PLL4_HSE 213 CLK_RTC_LSE 214 CLK_MCO1_DISABLED 215 CLK_MCO2_DISABLED 216 >; 217 218 st,clkdiv = < 219 1 /*MPU*/ 220 0 /*AXI*/ 221 0 /*MCU*/ 222 1 /*APB1*/ 223 1 /*APB2*/ 224 1 /*APB3*/ 225 1 /*APB4*/ 226 2 /*APB5*/ 227 23 /*RTC*/ 228 0 /*MCO1*/ 229 0 /*MCO2*/ 230 >; 231 232 st,pkcs = < 233 CLK_CKPER_HSE 234 CLK_FMC_ACLK 235 CLK_QSPI_ACLK 236 CLK_ETH_PLL4P 237 CLK_SDMMC12_PLL4P 238 CLK_DSI_DSIPLL 239 CLK_STGEN_HSE 240 CLK_USBPHY_HSE 241 CLK_SPI2S1_PLL3Q 242 CLK_SPI2S23_PLL3Q 243 CLK_SPI45_HSI 244 CLK_SPI6_HSI 245 CLK_I2C46_HSI 246 CLK_SDMMC3_PLL4P 247 CLK_USBO_USBPHY 248 CLK_ADC_CKPER 249 CLK_CEC_LSE 250 CLK_I2C12_HSI 251 CLK_I2C35_HSI 252 CLK_UART1_HSI 253 CLK_UART24_HSI 254 CLK_UART35_HSI 255 CLK_UART6_HSI 256 CLK_UART78_HSI 257 CLK_SPDIF_PLL4P 258 CLK_FDCAN_PLL4R 259 CLK_SAI1_PLL3Q 260 CLK_SAI2_PLL3Q 261 CLK_SAI3_PLL3Q 262 CLK_SAI4_PLL3Q 263 CLK_RNG1_LSI 264 CLK_RNG2_LSI 265 CLK_LPTIM1_PCLK1 266 CLK_LPTIM23_PCLK3 267 CLK_LPTIM45_LSE 268 >; 269 270 /* VCO = 1300.0 MHz => P = 650 (CPU) */ 271 pll1: st,pll@0 { 272 compatible = "st,stm32mp1-pll"; 273 reg = <0>; 274 cfg = <2 80 0 0 0 PQR(1,0,0)>; 275 frac = <0x800>; 276 }; 277 278 /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */ 279 pll2: st,pll@1 { 280 compatible = "st,stm32mp1-pll"; 281 reg = <1>; 282 cfg = <2 65 1 0 0 PQR(1,1,1)>; 283 frac = <0x1400>; 284 }; 285 286 /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */ 287 pll3: st,pll@2 { 288 compatible = "st,stm32mp1-pll"; 289 reg = <2>; 290 cfg = <1 33 1 16 36 PQR(1,1,1)>; 291 frac = <0x1a04>; 292 }; 293 294 /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */ 295 pll4: st,pll@3 { 296 compatible = "st,stm32mp1-pll"; 297 reg = <3>; 298 cfg = <3 98 5 7 7 PQR(1,1,1)>; 299 }; 300}; 301 302&rng1 { 303 status = "okay"; 304}; 305 306&rtc { 307 status = "okay"; 308}; 309 310&sdmmc1 { 311 pinctrl-names = "default"; 312 pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>; 313 disable-wp; 314 st,sig-dir; 315 st,neg-edge; 316 st,use-ckin; 317 bus-width = <4>; 318 vmmc-supply = <&vdd_sd>; 319 sd-uhs-sdr12; 320 sd-uhs-sdr25; 321 sd-uhs-sdr50; 322 sd-uhs-ddr50; 323 status = "okay"; 324}; 325 326&sdmmc2 { 327 pinctrl-names = "default"; 328 pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>; 329 non-removable; 330 no-sd; 331 no-sdio; 332 st,neg-edge; 333 bus-width = <8>; 334 vmmc-supply = <&v3v3>; 335 vqmmc-supply = <&vdd>; 336 mmc-ddr-3_3v; 337 status = "okay"; 338}; 339 340&uart4 { 341 pinctrl-names = "default"; 342 pinctrl-0 = <&uart4_pins_a>; 343 status = "okay"; 344}; 345