1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright (C) 2023, Protonic Holland - All Rights Reserved 4 * Author: David Jander <david@protonic.nl> 5 */ 6/dts-v1/; 7 8#include "stm32mp151.dtsi" 9#include "stm32mp15-pinctrl.dtsi" 10#include "stm32mp15xxad-pinctrl.dtsi" 11#include <dt-bindings/clock/stm32mp1-clksrc.h> 12#include "stm32mp15-ddr3-1x2Gb-1066-binG.dtsi" 13 14/ { 15 model = "Protonic PRTT1A"; 16 compatible = "prt,prtt1a", "st,stm32mp151"; 17 18 chosen { 19 stdout-path = "serial0:115200n8"; 20 }; 21 22 aliases { 23 mmc0 = &sdmmc1; 24 mmc1 = &sdmmc2; 25 serial0 = &uart4; 26 }; 27 28 memory@c0000000 { 29 device_type = "memory"; 30 reg = <0xC0000000 0x10000000>; 31 }; 32}; 33 34&iwdg2 { 35 timeout-sec = <32>; 36 status = "okay"; 37 secure-status = "okay"; 38}; 39 40&qspi { 41 pinctrl-names = "default", "sleep"; 42 pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>; 43 reg = <0x58003000 0x1000>, <0x70000000 0x4000000>; 44 #address-cells = <1>; 45 #size-cells = <0>; 46 status = "okay"; 47 48 flash@0 { 49 compatible = "spi-nand"; 50 reg = <0>; 51 spi-rx-bus-width = <4>; 52 spi-max-frequency = <104000000>; 53 #address-cells = <1>; 54 #size-cells = <1>; 55 }; 56}; 57 58&qspi_bk1_pins_a { 59 pins1 { 60 bias-pull-up; 61 drive-push-pull; 62 slew-rate = <1>; 63 }; 64}; 65 66&rcc { 67 st,clksrc = < 68 CLK_MPU_PLL1P 69 CLK_AXI_PLL2P 70 CLK_MCU_PLL3P 71 CLK_PLL12_HSE 72 CLK_PLL3_HSE 73 CLK_PLL4_HSE 74 CLK_RTC_LSI 75 CLK_MCO1_DISABLED 76 CLK_MCO2_DISABLED 77 >; 78 79 st,clkdiv = < 80 1 /*MPU*/ 81 0 /*AXI*/ 82 0 /*MCU*/ 83 1 /*APB1*/ 84 1 /*APB2*/ 85 1 /*APB3*/ 86 1 /*APB4*/ 87 2 /*APB5*/ 88 23 /*RTC*/ 89 0 /*MCO1*/ 90 0 /*MCO2*/ 91 >; 92 93 st,pkcs = < 94 CLK_CKPER_HSE 95 CLK_FMC_ACLK 96 CLK_QSPI_ACLK 97 CLK_ETH_DISABLED 98 CLK_SDMMC12_PLL4P 99 CLK_DSI_DSIPLL 100 CLK_STGEN_HSE 101 CLK_USBPHY_HSE 102 CLK_SPI2S1_PLL3Q 103 CLK_SPI2S23_PLL3Q 104 CLK_SPI45_HSI 105 CLK_SPI6_HSI 106 CLK_I2C46_HSI 107 CLK_SDMMC3_PLL4P 108 CLK_USBO_USBPHY 109 CLK_ADC_CKPER 110 CLK_CEC_LSI 111 CLK_I2C12_HSI 112 CLK_I2C35_HSI 113 CLK_UART1_HSI 114 CLK_UART24_HSI 115 CLK_UART35_HSI 116 CLK_UART6_HSI 117 CLK_UART78_HSI 118 CLK_SPDIF_PLL4P 119 CLK_FDCAN_PLL4R 120 CLK_SAI1_PLL3Q 121 CLK_SAI2_PLL3Q 122 CLK_SAI3_PLL3Q 123 CLK_SAI4_PLL3Q 124 CLK_RNG1_LSI 125 CLK_RNG2_LSI 126 CLK_LPTIM1_PCLK1 127 CLK_LPTIM23_PCLK3 128 CLK_LPTIM45_LSI 129 >; 130 131 /* VCO = 1300.0 MHz => P = 650 (CPU) */ 132 pll1: st,pll@0 { 133 compatible = "st,stm32mp1-pll"; 134 reg = <0>; 135 cfg = <2 80 0 0 0 PQR(1,0,0)>; 136 frac = <0x800>; 137 }; 138 139 /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */ 140 pll2: st,pll@1 { 141 compatible = "st,stm32mp1-pll"; 142 reg = <1>; 143 cfg = <2 65 1 0 0 PQR(1,1,1)>; 144 frac = <0x1400>; 145 }; 146 147 /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */ 148 pll3: st,pll@2 { 149 compatible = "st,stm32mp1-pll"; 150 reg = <2>; 151 cfg = <1 33 1 16 36 PQR(1,1,1)>; 152 frac = <0x1a04>; 153 }; 154 155 /* VCO = 480.0 MHz => P = 120, Q = 40, R = 96 */ 156 pll4: st,pll@3 { 157 compatible = "st,stm32mp1-pll"; 158 reg = <3>; 159 cfg = <1 39 3 11 4 PQR(1,1,1)>; 160 }; 161}; 162 163&rng1 { 164 status = "okay"; 165}; 166 167&rtc { 168 status = "okay"; 169}; 170 171&sdmmc1 { 172 pinctrl-names = "default"; 173 pinctrl-0 = <&sdmmc1_b4_pins_a>; 174 bus-width = <4>; 175 status = "okay"; 176}; 177 178&sdmmc1_b4_pins_a { 179 pins1 { 180 bias-pull-up; 181 }; 182 pins2 { 183 bias-pull-up; 184 }; 185}; 186 187/* NOTE: Although the PRTT1A does not have an eMMC, we declare it 188 * anyway, in order to be able to use the same binary for the 189 * PRTT1C also. All involved pins are N.C. on PRTT1A/S for that 190 * reason, so it should do no harm. All inputs configured with 191 * pull-ups to avoid floating inputs. */ 192&sdmmc2 { 193 pinctrl-names = "default"; 194 pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>; 195 bus-width = <8>; 196 status = "okay"; 197}; 198 199&sdmmc2_b4_pins_a { 200 pins1 { 201 pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */ 202 <STM32_PINMUX('B', 7, AF10)>, /* SDMMC2_D1 */ 203 <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */ 204 <STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */ 205 <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */ 206 }; 207}; 208 209&sdmmc2_d47_pins_a { 210 pins { 211 pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */ 212 <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */ 213 <STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */ 214 <STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */ 215 }; 216}; 217 218&uart4 { 219 pinctrl-names = "default"; 220 pinctrl-0 = <&uart4_pins_a>; 221 status = "okay"; 222}; 223 224&uart4_pins_a { 225 pins1 { 226 pinmux = <STM32_PINMUX('B', 9, AF8)>; /* UART4_TX */ 227 bias-disable; 228 drive-push-pull; 229 slew-rate = <0>; 230 }; 231 pins2 { 232 pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */ 233 bias-pull-up; 234 }; 235}; 236