1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright (C) 2023, Protonic Holland - All Rights Reserved 4 * Copyright (C) 2024-2025, STMicroelectronics - All Rights Reserved 5 * Author: David Jander <david@protonic.nl> 6 */ 7/dts-v1/; 8 9#include "stm32mp151.dtsi" 10#include "stm32mp15-pinctrl.dtsi" 11#include "stm32mp15xxad-pinctrl.dtsi" 12#include <dt-bindings/clock/stm32mp1-clksrc.h> 13#include "stm32mp15-ddr3-1x2Gb-1066-binG.dtsi" 14 15/ { 16 model = "Protonic PRTT1A"; 17 compatible = "prt,prtt1a", "st,stm32mp151"; 18 19 chosen { 20 stdout-path = "serial0:115200n8"; 21 }; 22 23 aliases { 24 mmc0 = &sdmmc1; 25 mmc1 = &sdmmc2; 26 serial0 = &uart4; 27 }; 28 29 memory@c0000000 { 30 device_type = "memory"; 31 reg = <0xC0000000 0x10000000>; 32 }; 33}; 34 35&iwdg2 { 36 timeout-sec = <32>; 37 status = "okay"; 38 secure-status = "okay"; 39}; 40 41&qspi { 42 pinctrl-names = "default", "sleep"; 43 pinctrl-0 = <&qspi_clk_pins_a 44 &qspi_bk1_pins_a 45 &qspi_cs1_pins_a>; 46 reg = <0x58003000 0x1000>, <0x70000000 0x4000000>; 47 #address-cells = <1>; 48 #size-cells = <0>; 49 status = "okay"; 50 51 flash@0 { 52 compatible = "spi-nand"; 53 reg = <0>; 54 spi-rx-bus-width = <4>; 55 spi-max-frequency = <104000000>; 56 #address-cells = <1>; 57 #size-cells = <1>; 58 }; 59}; 60 61&qspi_bk1_pins_a { 62 pins { 63 bias-pull-up; 64 drive-push-pull; 65 slew-rate = <1>; 66 }; 67}; 68 69&rcc { 70 st,clksrc = < 71 CLK_MPU_PLL1P 72 CLK_AXI_PLL2P 73 CLK_MCU_PLL3P 74 CLK_RTC_LSI 75 CLK_MCO1_DISABLED 76 CLK_MCO2_DISABLED 77 CLK_CKPER_HSE 78 CLK_FMC_ACLK 79 CLK_QSPI_ACLK 80 CLK_ETH_DISABLED 81 CLK_SDMMC12_PLL4P 82 CLK_DSI_DSIPLL 83 CLK_STGEN_HSE 84 CLK_USBPHY_HSE 85 CLK_SPI2S1_PLL3Q 86 CLK_SPI2S23_PLL3Q 87 CLK_SPI45_HSI 88 CLK_SPI6_HSI 89 CLK_I2C46_HSI 90 CLK_SDMMC3_PLL4P 91 CLK_USBO_USBPHY 92 CLK_ADC_CKPER 93 CLK_CEC_LSI 94 CLK_I2C12_HSI 95 CLK_I2C35_HSI 96 CLK_UART1_HSI 97 CLK_UART24_HSI 98 CLK_UART35_HSI 99 CLK_UART6_HSI 100 CLK_UART78_HSI 101 CLK_SPDIF_PLL4P 102 CLK_FDCAN_PLL4R 103 CLK_SAI1_PLL3Q 104 CLK_SAI2_PLL3Q 105 CLK_SAI3_PLL3Q 106 CLK_SAI4_PLL3Q 107 CLK_RNG1_CSI 108 CLK_RNG2_LSI 109 CLK_LPTIM1_PCLK1 110 CLK_LPTIM23_PCLK3 111 CLK_LPTIM45_LSI 112 >; 113 114 st,clkdiv = < 115 DIV(DIV_MPU, 1) 116 DIV(DIV_AXI, 0) 117 DIV(DIV_MCU, 0) 118 DIV(DIV_APB1, 1) 119 DIV(DIV_APB2, 1) 120 DIV(DIV_APB3, 1) 121 DIV(DIV_APB4, 1) 122 DIV(DIV_APB5, 2) 123 DIV(DIV_RTC, 23) 124 DIV(DIV_MCO1, 0) 125 DIV(DIV_MCO2, 0) 126 >; 127 128 st,pll_vco { 129 pll2_vco_1066Mhz: pll2-vco-1066Mhz { 130 src = <CLK_PLL12_HSE>; 131 divmn = <2 65>; 132 frac = <0x1400>; 133 }; 134 135 pll3_vco_417Mhz: pll3-vco-417Mhz { 136 src = <CLK_PLL3_HSE>; 137 divmn = <1 33>; 138 frac = <0x1a04>; 139 }; 140 141 pll4_vco_480Mhz: pll4-vco-480Mhz { 142 src = <CLK_PLL4_HSE>; 143 divmn = <1 39>; 144 }; 145 }; 146 147 /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */ 148 pll2: st,pll@1 { 149 compatible = "st,stm32mp1-pll"; 150 reg = <1>; 151 152 st,pll = <&pll2_cfg1>; 153 154 pll2_cfg1: pll2_cfg1 { 155 st,pll_vco = <&pll2_vco_1066Mhz>; 156 st,pll_div_pqr = <1 0 0>; 157 }; 158 }; 159 160 /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */ 161 pll3: st,pll@2 { 162 compatible = "st,stm32mp1-pll"; 163 reg = <2>; 164 165 st,pll = <&pll3_cfg1>; 166 167 pll3_cfg1: pll3_cfg1 { 168 st,pll_vco = <&pll3_vco_417Mhz>; 169 st,pll_div_pqr = <1 16 36>; 170 }; 171 }; 172 173 /* VCO = 480.0 MHz => P = 120, Q = 40, R = 96 */ 174 pll4: st,pll@3 { 175 compatible = "st,stm32mp1-pll"; 176 reg = <3>; 177 178 st,pll = <&pll4_cfg1>; 179 180 pll4_cfg1: pll4_cfg1 { 181 st,pll_vco = <&pll4_vco_480Mhz>; 182 st,pll_div_pqr = <3 11 4>; 183 }; 184 }; 185}; 186 187&rng1 { 188 status = "okay"; 189}; 190 191&rtc { 192 status = "okay"; 193}; 194 195&sdmmc1 { 196 pinctrl-names = "default"; 197 pinctrl-0 = <&sdmmc1_b4_pins_a>; 198 bus-width = <4>; 199 status = "okay"; 200}; 201 202&sdmmc1_b4_pins_a { 203 pins1 { 204 bias-pull-up; 205 }; 206 pins2 { 207 bias-pull-up; 208 }; 209}; 210 211/* NOTE: Although the PRTT1A does not have an eMMC, we declare it 212 * anyway, in order to be able to use the same binary for the 213 * PRTT1C also. All involved pins are N.C. on PRTT1A/S for that 214 * reason, so it should do no harm. All inputs configured with 215 * pull-ups to avoid floating inputs. */ 216&sdmmc2 { 217 pinctrl-names = "default"; 218 pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>; 219 bus-width = <8>; 220 status = "okay"; 221}; 222 223&sdmmc2_b4_pins_a { 224 pins1 { 225 pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */ 226 <STM32_PINMUX('B', 7, AF10)>, /* SDMMC2_D1 */ 227 <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */ 228 <STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */ 229 <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */ 230 }; 231}; 232 233&sdmmc2_d47_pins_a { 234 pins { 235 pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */ 236 <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */ 237 <STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */ 238 <STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */ 239 }; 240}; 241 242&uart4 { 243 pinctrl-names = "default"; 244 pinctrl-0 = <&uart4_pins_a>; 245 status = "okay"; 246}; 247 248&uart4_pins_a { 249 pins1 { 250 pinmux = <STM32_PINMUX('B', 9, AF8)>; /* UART4_TX */ 251 bias-disable; 252 drive-push-pull; 253 slew-rate = <0>; 254 }; 255 pins2 { 256 pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */ 257 bias-pull-up; 258 }; 259}; 260