1*6c1e71e1SYann Gautier// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause 2*6c1e71e1SYann Gautier/* 3*6c1e71e1SYann Gautier * Copyright (C) 2018, STMicroelectronics - All Rights Reserved 4*6c1e71e1SYann Gautier */ 5*6c1e71e1SYann Gautier/* STM32MP157C DK1/DK2 BOARD configuration 6*6c1e71e1SYann Gautier * 1x DDR3L 4Gb, 16-bit, 533MHz. 7*6c1e71e1SYann Gautier * Reference used NT5CC256M16DP-DI from NANYA 8*6c1e71e1SYann Gautier * 9*6c1e71e1SYann Gautier * DDR type / Platform DDR3/3L 10*6c1e71e1SYann Gautier * freq 533MHz 11*6c1e71e1SYann Gautier * width 16 12*6c1e71e1SYann Gautier * datasheet 0 = MT41J256M16-187 / DDR3-1066 bin G 13*6c1e71e1SYann Gautier * DDR density 4 14*6c1e71e1SYann Gautier * timing mode optimized 15*6c1e71e1SYann Gautier * Scheduling/QoS options : type = 2 16*6c1e71e1SYann Gautier * address mapping : RBC 17*6c1e71e1SYann Gautier * Tc > + 85C : N 18*6c1e71e1SYann Gautier */ 19*6c1e71e1SYann Gautier 20*6c1e71e1SYann Gautier#define DDR_MEM_NAME "DDR3-1066/888 bin G 1x4Gb 533MHz v1.41" 21*6c1e71e1SYann Gautier#define DDR_MEM_SPEED 533000 22*6c1e71e1SYann Gautier#define DDR_MEM_SIZE 0x20000000 23*6c1e71e1SYann Gautier 24*6c1e71e1SYann Gautier#define DDR_MSTR 0x00041401 25*6c1e71e1SYann Gautier#define DDR_MRCTRL0 0x00000010 26*6c1e71e1SYann Gautier#define DDR_MRCTRL1 0x00000000 27*6c1e71e1SYann Gautier#define DDR_DERATEEN 0x00000000 28*6c1e71e1SYann Gautier#define DDR_DERATEINT 0x00800000 29*6c1e71e1SYann Gautier#define DDR_PWRCTL 0x00000000 30*6c1e71e1SYann Gautier#define DDR_PWRTMG 0x00400010 31*6c1e71e1SYann Gautier#define DDR_HWLPCTL 0x00000000 32*6c1e71e1SYann Gautier#define DDR_RFSHCTL0 0x00210000 33*6c1e71e1SYann Gautier#define DDR_RFSHCTL3 0x00000000 34*6c1e71e1SYann Gautier#define DDR_RFSHTMG 0x0081008B 35*6c1e71e1SYann Gautier#define DDR_CRCPARCTL0 0x00000000 36*6c1e71e1SYann Gautier#define DDR_DRAMTMG0 0x121B2414 37*6c1e71e1SYann Gautier#define DDR_DRAMTMG1 0x000A041C 38*6c1e71e1SYann Gautier#define DDR_DRAMTMG2 0x0608090F 39*6c1e71e1SYann Gautier#define DDR_DRAMTMG3 0x0050400C 40*6c1e71e1SYann Gautier#define DDR_DRAMTMG4 0x08040608 41*6c1e71e1SYann Gautier#define DDR_DRAMTMG5 0x06060403 42*6c1e71e1SYann Gautier#define DDR_DRAMTMG6 0x02020002 43*6c1e71e1SYann Gautier#define DDR_DRAMTMG7 0x00000202 44*6c1e71e1SYann Gautier#define DDR_DRAMTMG8 0x00001005 45*6c1e71e1SYann Gautier#define DDR_DRAMTMG14 0x000000A0 46*6c1e71e1SYann Gautier#define DDR_ZQCTL0 0xC2000040 47*6c1e71e1SYann Gautier#define DDR_DFITMG0 0x02060105 48*6c1e71e1SYann Gautier#define DDR_DFITMG1 0x00000202 49*6c1e71e1SYann Gautier#define DDR_DFILPCFG0 0x07000000 50*6c1e71e1SYann Gautier#define DDR_DFIUPD0 0xC0400003 51*6c1e71e1SYann Gautier#define DDR_DFIUPD1 0x00000000 52*6c1e71e1SYann Gautier#define DDR_DFIUPD2 0x00000000 53*6c1e71e1SYann Gautier#define DDR_DFIPHYMSTR 0x00000000 54*6c1e71e1SYann Gautier#define DDR_ADDRMAP1 0x00070707 55*6c1e71e1SYann Gautier#define DDR_ADDRMAP2 0x00000000 56*6c1e71e1SYann Gautier#define DDR_ADDRMAP3 0x1F000000 57*6c1e71e1SYann Gautier#define DDR_ADDRMAP4 0x00001F1F 58*6c1e71e1SYann Gautier#define DDR_ADDRMAP5 0x06060606 59*6c1e71e1SYann Gautier#define DDR_ADDRMAP6 0x0F060606 60*6c1e71e1SYann Gautier#define DDR_ADDRMAP9 0x00000000 61*6c1e71e1SYann Gautier#define DDR_ADDRMAP10 0x00000000 62*6c1e71e1SYann Gautier#define DDR_ADDRMAP11 0x00000000 63*6c1e71e1SYann Gautier#define DDR_ODTCFG 0x06000600 64*6c1e71e1SYann Gautier#define DDR_ODTMAP 0x00000001 65*6c1e71e1SYann Gautier#define DDR_SCHED 0x00000C01 66*6c1e71e1SYann Gautier#define DDR_SCHED1 0x00000000 67*6c1e71e1SYann Gautier#define DDR_PERFHPR1 0x01000001 68*6c1e71e1SYann Gautier#define DDR_PERFLPR1 0x08000200 69*6c1e71e1SYann Gautier#define DDR_PERFWR1 0x08000400 70*6c1e71e1SYann Gautier#define DDR_DBG0 0x00000000 71*6c1e71e1SYann Gautier#define DDR_DBG1 0x00000000 72*6c1e71e1SYann Gautier#define DDR_DBGCMD 0x00000000 73*6c1e71e1SYann Gautier#define DDR_POISONCFG 0x00000000 74*6c1e71e1SYann Gautier#define DDR_PCCFG 0x00000010 75*6c1e71e1SYann Gautier#define DDR_PCFGR_0 0x00010000 76*6c1e71e1SYann Gautier#define DDR_PCFGW_0 0x00000000 77*6c1e71e1SYann Gautier#define DDR_PCFGQOS0_0 0x02100C03 78*6c1e71e1SYann Gautier#define DDR_PCFGQOS1_0 0x00800100 79*6c1e71e1SYann Gautier#define DDR_PCFGWQOS0_0 0x01100C03 80*6c1e71e1SYann Gautier#define DDR_PCFGWQOS1_0 0x01000200 81*6c1e71e1SYann Gautier#define DDR_PCFGR_1 0x00010000 82*6c1e71e1SYann Gautier#define DDR_PCFGW_1 0x00000000 83*6c1e71e1SYann Gautier#define DDR_PCFGQOS0_1 0x02100C03 84*6c1e71e1SYann Gautier#define DDR_PCFGQOS1_1 0x00800040 85*6c1e71e1SYann Gautier#define DDR_PCFGWQOS0_1 0x01100C03 86*6c1e71e1SYann Gautier#define DDR_PCFGWQOS1_1 0x01000200 87*6c1e71e1SYann Gautier#define DDR_PGCR 0x01442E02 88*6c1e71e1SYann Gautier#define DDR_PTR0 0x0022AA5B 89*6c1e71e1SYann Gautier#define DDR_PTR1 0x04841104 90*6c1e71e1SYann Gautier#define DDR_PTR2 0x042DA068 91*6c1e71e1SYann Gautier#define DDR_ACIOCR 0x10400812 92*6c1e71e1SYann Gautier#define DDR_DXCCR 0x00000C40 93*6c1e71e1SYann Gautier#define DDR_DSGCR 0xF200001F 94*6c1e71e1SYann Gautier#define DDR_DCR 0x0000000B 95*6c1e71e1SYann Gautier#define DDR_DTPR0 0x38D488D0 96*6c1e71e1SYann Gautier#define DDR_DTPR1 0x098B00D8 97*6c1e71e1SYann Gautier#define DDR_DTPR2 0x10023600 98*6c1e71e1SYann Gautier#define DDR_MR0 0x00000840 99*6c1e71e1SYann Gautier#define DDR_MR1 0x00000000 100*6c1e71e1SYann Gautier#define DDR_MR2 0x00000208 101*6c1e71e1SYann Gautier#define DDR_MR3 0x00000000 102*6c1e71e1SYann Gautier#define DDR_ODTCR 0x00010000 103*6c1e71e1SYann Gautier#define DDR_ZQ0CR1 0x00000038 104*6c1e71e1SYann Gautier#define DDR_DX0GCR 0x0000CE81 105*6c1e71e1SYann Gautier#define DDR_DX0DLLCR 0x40000000 106*6c1e71e1SYann Gautier#define DDR_DX0DQTR 0xFFFFFFFF 107*6c1e71e1SYann Gautier#define DDR_DX0DQSTR 0x3DB02000 108*6c1e71e1SYann Gautier#define DDR_DX1GCR 0x0000CE81 109*6c1e71e1SYann Gautier#define DDR_DX1DLLCR 0x40000000 110*6c1e71e1SYann Gautier#define DDR_DX1DQTR 0xFFFFFFFF 111*6c1e71e1SYann Gautier#define DDR_DX1DQSTR 0x3DB02000 112*6c1e71e1SYann Gautier#define DDR_DX2GCR 0x0000CE81 113*6c1e71e1SYann Gautier#define DDR_DX2DLLCR 0x40000000 114*6c1e71e1SYann Gautier#define DDR_DX2DQTR 0xFFFFFFFF 115*6c1e71e1SYann Gautier#define DDR_DX2DQSTR 0x3DB02000 116*6c1e71e1SYann Gautier#define DDR_DX3GCR 0x0000CE81 117*6c1e71e1SYann Gautier#define DDR_DX3DLLCR 0x40000000 118*6c1e71e1SYann Gautier#define DDR_DX3DQTR 0xFFFFFFFF 119*6c1e71e1SYann Gautier#define DDR_DX3DQSTR 0x3DB02000 120*6c1e71e1SYann Gautier 121*6c1e71e1SYann Gautier#include "stm32mp15-ddr.dtsi" 122