1/* 2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 motherboard { 32 arm,v2m-memory-map = "rs1"; 33 compatible = "arm,vexpress,v2m-p1", "simple-bus"; 34 #address-cells = <2>; /* SMB chipselect number and offset */ 35 #size-cells = <1>; 36 #interrupt-cells = <1>; 37 ranges; 38 39 flash@0,00000000 { 40 compatible = "arm,vexpress-flash", "cfi-flash"; 41 reg = <0 0x00000000 0x04000000>, 42 <4 0x00000000 0x04000000>; 43 bank-width = <4>; 44 }; 45 46 vram@2,00000000 { 47 compatible = "arm,vexpress-vram"; 48 reg = <2 0x00000000 0x00800000>; 49 }; 50 51 ethernet@2,02000000 { 52 compatible = "smsc,lan91c111"; 53 reg = <2 0x02000000 0x10000>; 54 interrupts = <15>; 55 }; 56 57 v2m_clk24mhz: clk24mhz { 58 compatible = "fixed-clock"; 59 #clock-cells = <0>; 60 clock-frequency = <24000000>; 61 clock-output-names = "v2m:clk24mhz"; 62 }; 63 64 v2m_refclk1mhz: refclk1mhz { 65 compatible = "fixed-clock"; 66 #clock-cells = <0>; 67 clock-frequency = <1000000>; 68 clock-output-names = "v2m:refclk1mhz"; 69 }; 70 71 v2m_refclk32khz: refclk32khz { 72 compatible = "fixed-clock"; 73 #clock-cells = <0>; 74 clock-frequency = <32768>; 75 clock-output-names = "v2m:refclk32khz"; 76 }; 77 78 iofpga@3,00000000 { 79 compatible = "arm,amba-bus", "simple-bus"; 80 #address-cells = <1>; 81 #size-cells = <1>; 82 ranges = <0 3 0 0x200000>; 83 84 v2m_sysreg: sysreg@010000 { 85 compatible = "arm,vexpress-sysreg"; 86 reg = <0x010000 0x1000>; 87 gpio-controller; 88 #gpio-cells = <2>; 89 }; 90 91 v2m_sysctl: sysctl@020000 { 92 compatible = "arm,sp810", "arm,primecell"; 93 reg = <0x020000 0x1000>; 94 clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&v2m_clk24mhz>; 95 clock-names = "refclk", "timclk", "apb_pclk"; 96 #clock-cells = <1>; 97 clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3"; 98 }; 99 100 aaci@040000 { 101 compatible = "arm,pl041", "arm,primecell"; 102 reg = <0x040000 0x1000>; 103 interrupts = <11>; 104 clocks = <&v2m_clk24mhz>; 105 clock-names = "apb_pclk"; 106 }; 107 108 mmci@050000 { 109 compatible = "arm,pl180", "arm,primecell"; 110 reg = <0x050000 0x1000>; 111 interrupts = <9 10>; 112 cd-gpios = <&v2m_sysreg 0 0>; 113 wp-gpios = <&v2m_sysreg 1 0>; 114 max-frequency = <12000000>; 115 vmmc-supply = <&v2m_fixed_3v3>; 116 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; 117 clock-names = "mclk", "apb_pclk"; 118 }; 119 120 kmi@060000 { 121 compatible = "arm,pl050", "arm,primecell"; 122 reg = <0x060000 0x1000>; 123 interrupts = <12>; 124 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; 125 clock-names = "KMIREFCLK", "apb_pclk"; 126 }; 127 128 kmi@070000 { 129 compatible = "arm,pl050", "arm,primecell"; 130 reg = <0x070000 0x1000>; 131 interrupts = <13>; 132 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; 133 clock-names = "KMIREFCLK", "apb_pclk"; 134 }; 135 136 v2m_serial0: uart@090000 { 137 compatible = "arm,pl011", "arm,primecell"; 138 reg = <0x090000 0x1000>; 139 interrupts = <5>; 140 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; 141 clock-names = "uartclk", "apb_pclk"; 142 }; 143 144 v2m_serial1: uart@0a0000 { 145 compatible = "arm,pl011", "arm,primecell"; 146 reg = <0x0a0000 0x1000>; 147 interrupts = <6>; 148 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; 149 clock-names = "uartclk", "apb_pclk"; 150 }; 151 152 v2m_serial2: uart@0b0000 { 153 compatible = "arm,pl011", "arm,primecell"; 154 reg = <0x0b0000 0x1000>; 155 interrupts = <7>; 156 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; 157 clock-names = "uartclk", "apb_pclk"; 158 }; 159 160 v2m_serial3: uart@0c0000 { 161 compatible = "arm,pl011", "arm,primecell"; 162 reg = <0x0c0000 0x1000>; 163 interrupts = <8>; 164 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; 165 clock-names = "uartclk", "apb_pclk"; 166 }; 167 168 wdt@0f0000 { 169 compatible = "arm,sp805", "arm,primecell"; 170 reg = <0x0f0000 0x1000>; 171 interrupts = <0>; 172 clocks = <&v2m_refclk32khz>, <&v2m_clk24mhz>; 173 clock-names = "wdogclk", "apb_pclk"; 174 }; 175 176 v2m_timer01: timer@110000 { 177 compatible = "arm,sp804", "arm,primecell"; 178 reg = <0x110000 0x1000>; 179 interrupts = <2>; 180 clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_clk24mhz>; 181 clock-names = "timclken1", "timclken2", "apb_pclk"; 182 }; 183 184 v2m_timer23: timer@120000 { 185 compatible = "arm,sp804", "arm,primecell"; 186 reg = <0x120000 0x1000>; 187 interrupts = <3>; 188 clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&v2m_clk24mhz>; 189 clock-names = "timclken1", "timclken2", "apb_pclk"; 190 }; 191 192 rtc@170000 { 193 compatible = "arm,pl031", "arm,primecell"; 194 reg = <0x170000 0x1000>; 195 interrupts = <4>; 196 clocks = <&v2m_clk24mhz>; 197 clock-names = "apb_pclk"; 198 }; 199 200 clcd@1f0000 { 201 compatible = "arm,pl111", "arm,primecell"; 202 reg = <0x1f0000 0x1000>; 203 interrupts = <14>; 204 clocks = <&v2m_oscclk1>, <&v2m_clk24mhz>; 205 clock-names = "clcdclk", "apb_pclk"; 206 mode = "XVGA"; 207 use_dma = <0>; 208 framebuffer = <0x18000000 0x00180000>; 209 }; 210 211 virtio_block@0130000 { 212 compatible = "virtio,mmio"; 213 reg = <0x130000 0x1000>; 214 interrupts = <0x2a>; 215 }; 216 }; 217 218 v2m_fixed_3v3: fixedregulator@0 { 219 compatible = "regulator-fixed"; 220 regulator-name = "3V3"; 221 regulator-min-microvolt = <3300000>; 222 regulator-max-microvolt = <3300000>; 223 regulator-always-on; 224 }; 225 226 mcc { 227 compatible = "arm,vexpress,config-bus", "simple-bus"; 228 arm,vexpress,config-bridge = <&v2m_sysreg>; 229 230 v2m_oscclk1: osc@1 { 231 /* CLCD clock */ 232 compatible = "arm,vexpress-osc"; 233 arm,vexpress-sysreg,func = <1 1>; 234 freq-range = <23750000 63500000>; 235 #clock-cells = <0>; 236 clock-output-names = "v2m:oscclk1"; 237 }; 238 239 /* 240 * Not supported in FVP models 241 * 242 * reset@0 { 243 * compatible = "arm,vexpress-reset"; 244 * arm,vexpress-sysreg,func = <5 0>; 245 * }; 246 */ 247 248 muxfpga@0 { 249 compatible = "arm,vexpress-muxfpga"; 250 arm,vexpress-sysreg,func = <7 0>; 251 }; 252 253 /* 254 * Not used - Superseded by PSCI sys_poweroff 255 * 256 * shutdown@0 { 257 * compatible = "arm,vexpress-shutdown"; 258 * arm,vexpress-sysreg,func = <8 0>; 259 * }; 260 */ 261 262 /* 263 * Not used - Superseded by PSCI sys_reset 264 * 265 * reboot@0 { 266 * compatible = "arm,vexpress-reboot"; 267 * arm,vexpress-sysreg,func = <9 0>; 268 * }; 269 */ 270 271 dvimode@0 { 272 compatible = "arm,vexpress-dvimode"; 273 arm,vexpress-sysreg,func = <11 0>; 274 }; 275 }; 276 }; 277