1/* 2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of the ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31/dts-v1/; 32 33/memreserve/ 0x80000000 0x00010000; 34 35/ { 36}; 37 38/ { 39 model = "FVP Foundation"; 40 compatible = "arm,fvp-base", "arm,vexpress"; 41 interrupt-parent = <&gic>; 42 #address-cells = <2>; 43 #size-cells = <2>; 44 45 chosen { }; 46 47 aliases { 48 serial0 = &v2m_serial0; 49 serial1 = &v2m_serial1; 50 serial2 = &v2m_serial2; 51 serial3 = &v2m_serial3; 52 }; 53 54 psci { 55 compatible = "arm,psci"; 56 method = "smc"; 57 cpu_suspend = <0xc4000001>; 58 cpu_off = <0x84000002>; 59 cpu_on = <0xc4000003>; 60 }; 61 62 cpus { 63 #address-cells = <2>; 64 #size-cells = <0>; 65 66 cpu@0 { 67 device_type = "cpu"; 68 compatible = "arm,armv8"; 69 reg = <0x0 0x0>; 70 enable-method = "psci"; 71 }; 72 cpu@1 { 73 device_type = "cpu"; 74 compatible = "arm,armv8"; 75 reg = <0x0 0x1>; 76 enable-method = "psci"; 77 }; 78 cpu@2 { 79 device_type = "cpu"; 80 compatible = "arm,armv8"; 81 reg = <0x0 0x2>; 82 enable-method = "psci"; 83 }; 84 cpu@3 { 85 device_type = "cpu"; 86 compatible = "arm,armv8"; 87 reg = <0x0 0x3>; 88 enable-method = "psci"; 89 }; 90 }; 91 92 memory@80000000 { 93 device_type = "memory"; 94 reg = <0x00000000 0x80000000 0 0x80000000>, 95 <0x00000008 0x80000000 0 0x80000000>; 96 }; 97 98 gic: interrupt-controller@2f000000 { 99 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; 100 #interrupt-cells = <3>; 101 #address-cells = <0>; 102 interrupt-controller; 103 reg = <0x0 0x2f000000 0 0x10000>, 104 <0x0 0x2c000000 0 0x2000>, 105 <0x0 0x2c010000 0 0x2000>, 106 <0x0 0x2c02F000 0 0x2000>; 107 interrupts = <1 9 0xf04>; 108 }; 109 110 timer { 111 compatible = "arm,armv8-timer"; 112 interrupts = <1 13 0xff01>, 113 <1 14 0xff01>, 114 <1 11 0xff01>, 115 <1 10 0xff01>; 116 clock-frequency = <100000000>; 117 }; 118 119 timer@2a810000 { 120 compatible = "arm,armv7-timer-mem"; 121 reg = <0x0 0x2a810000 0x0 0x10000>; 122 clock-frequency = <100000000>; 123 #address-cells = <2>; 124 #size-cells = <2>; 125 ranges; 126 frame@2a830000 { 127 frame-number = <1>; 128 interrupts = <0 26 4>; 129 reg = <0x0 0x2a830000 0x0 0x10000>; 130 }; 131 }; 132 133 pmu { 134 compatible = "arm,armv8-pmuv3"; 135 interrupts = <0 60 4>, 136 <0 61 4>, 137 <0 62 4>, 138 <0 63 4>; 139 }; 140 141 smb { 142 compatible = "simple-bus"; 143 144 #address-cells = <2>; 145 #size-cells = <1>; 146 ranges = <0 0 0 0x08000000 0x04000000>, 147 <1 0 0 0x14000000 0x04000000>, 148 <2 0 0 0x18000000 0x04000000>, 149 <3 0 0 0x1c000000 0x04000000>, 150 <4 0 0 0x0c000000 0x04000000>, 151 <5 0 0 0x10000000 0x04000000>; 152 153 #interrupt-cells = <1>; 154 interrupt-map-mask = <0 0 63>; 155 interrupt-map = <0 0 0 &gic 0 0 4>, 156 <0 0 1 &gic 0 1 4>, 157 <0 0 2 &gic 0 2 4>, 158 <0 0 3 &gic 0 3 4>, 159 <0 0 4 &gic 0 4 4>, 160 <0 0 5 &gic 0 5 4>, 161 <0 0 6 &gic 0 6 4>, 162 <0 0 7 &gic 0 7 4>, 163 <0 0 8 &gic 0 8 4>, 164 <0 0 9 &gic 0 9 4>, 165 <0 0 10 &gic 0 10 4>, 166 <0 0 11 &gic 0 11 4>, 167 <0 0 12 &gic 0 12 4>, 168 <0 0 13 &gic 0 13 4>, 169 <0 0 14 &gic 0 14 4>, 170 <0 0 15 &gic 0 15 4>, 171 <0 0 16 &gic 0 16 4>, 172 <0 0 17 &gic 0 17 4>, 173 <0 0 18 &gic 0 18 4>, 174 <0 0 19 &gic 0 19 4>, 175 <0 0 20 &gic 0 20 4>, 176 <0 0 21 &gic 0 21 4>, 177 <0 0 22 &gic 0 22 4>, 178 <0 0 23 &gic 0 23 4>, 179 <0 0 24 &gic 0 24 4>, 180 <0 0 25 &gic 0 25 4>, 181 <0 0 26 &gic 0 26 4>, 182 <0 0 27 &gic 0 27 4>, 183 <0 0 28 &gic 0 28 4>, 184 <0 0 29 &gic 0 29 4>, 185 <0 0 30 &gic 0 30 4>, 186 <0 0 31 &gic 0 31 4>, 187 <0 0 32 &gic 0 32 4>, 188 <0 0 33 &gic 0 33 4>, 189 <0 0 34 &gic 0 34 4>, 190 <0 0 35 &gic 0 35 4>, 191 <0 0 36 &gic 0 36 4>, 192 <0 0 37 &gic 0 37 4>, 193 <0 0 38 &gic 0 38 4>, 194 <0 0 39 &gic 0 39 4>, 195 <0 0 40 &gic 0 40 4>, 196 <0 0 41 &gic 0 41 4>, 197 <0 0 42 &gic 0 42 4>; 198 199 /include/ "fvp-foundation-motherboard.dtsi" 200 }; 201}; 202