1/* 2 * Copyright (c) 2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <dt-bindings/interrupt-controller/arm-gicv5.h> 8 9/* TODO: rtsm_ve-motherboard.dtsi definitons */ 10 11/ { 12 gic: interrupt-controller { 13 compatible = "arm,gic-v5"; 14 15 #interrupt-cells = <3>; 16 interrupt-controller; 17 18 #address-cells = <2>; 19 #size-cells = <2>; 20 ranges; 21 22 interrupts = <GIC_PPI 25 IRQ_TYPE_LEVEL_HIGH>; 23 24 irs0: irs@2f1a0000 { 25 compatible = "arm,gic-v5-irs"; 26 reg = <0x0 0x2f1a0000 0x0 0x10000>; /* NS IRS_CONFIG_FRAME */ 27 reg-names = "ns-config"; 28 29 #address-cells = <2>; 30 #size-cells = <2>; 31 ranges; 32 33 cpus = <&CPU0 34 &CPU1 35 &CPU2 36 &CPU3 37 &CPU4 38 &CPU5 39 &CPU6 40 &CPU7>; 41 arm,iaffids = /bits/ 16 <0 1 2 3 4 5 6 7>; 42 43 its@2f120000 { 44 compatible = "arm,gic-v5-its"; 45 reg = <0x0 0x2f120000 0x0 0x10000>; /* NS ITS_CONFIG_FRAME */ 46 reg-names = "ns-config"; 47 48 #address-cells = <2>; 49 #size-cells = <2>; 50 51 ranges; 52 53 its0: msi-controller@2f130000 { 54 reg = <0x0 0x2f130000 0x0 0x10000>; /* ITS_TRANSLATE_FRAME */ 55 reg-names = "ns-translate"; 56 57 #msi-cells = <1>; 58 msi-controller; 59 }; 60 }; 61 }; 62 }; 63 64 iwb0: interrupt-controller@2f000000 { 65 compatible = "arm,gic-v5-iwb"; 66 reg = <0x0 0x2f000000 0x0 0x10000>; 67 68 #address-cells = <0>; 69 70 interrupt-controller; 71 #interrupt-cells = <2>; 72 73 msi-parent = <&its0 64>; 74 }; 75 76 timer { 77 interrupts = <GIC_PPI 30 IRQ_TYPE_LEVEL_HIGH>, 78 <GIC_PPI 27 IRQ_TYPE_LEVEL_HIGH>, 79 <GIC_PPI 26 IRQ_TYPE_LEVEL_HIGH>; 80 interrupt-names = "phys", "virt", "hyp-phys"; 81 }; 82 83 timer@2a810000 { 84 frame@2a830000 { 85 /* Formerly GIC_LPI 58, now wire 26 as SPI. */ 86 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 87 }; 88 }; 89 90 pmu { 91 interrupts = <GIC_PPI 23 IRQ_TYPE_LEVEL_HIGH>; 92 }; 93 94 /* 95 * Previously these were mapped to SPIs 32-74. We now explicitly describe 96 * the wires on the IWB to which the interrupts are connected. All of the 97 * below are signalled as SPIs. 98 */ 99 bus@8000000 { 100 interrupt-map = <0 0 0 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 101 <0 0 1 &gic 0 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 102 <0 0 2 &gic 0 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 103 <0 0 3 &gic 0 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 104 <0 0 4 &gic 0 0 GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 105 <0 0 5 &gic 0 0 GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 106 <0 0 6 &gic 0 0 GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 107 <0 0 7 &gic 0 0 GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 108 <0 0 8 &gic 0 0 GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 109 <0 0 9 &gic 0 0 GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 110 <0 0 10 &gic 0 0 GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 111 <0 0 11 &gic 0 0 GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 112 <0 0 12 &gic 0 0 GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 113 <0 0 13 &gic 0 0 GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 114 <0 0 14 &gic 0 0 GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 115 <0 0 15 &gic 0 0 GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 116 <0 0 16 &gic 0 0 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 117 <0 0 17 &gic 0 0 GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 118 <0 0 18 &gic 0 0 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 119 <0 0 19 &gic 0 0 GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 120 <0 0 20 &gic 0 0 GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 121 <0 0 21 &gic 0 0 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 122 <0 0 22 &gic 0 0 GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 123 <0 0 23 &gic 0 0 GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 124 <0 0 24 &gic 0 0 GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 125 <0 0 25 &gic 0 0 GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 126 <0 0 26 &gic 0 0 GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 127 <0 0 27 &gic 0 0 GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 128 <0 0 28 &gic 0 0 GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 129 <0 0 29 &gic 0 0 GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 130 <0 0 30 &gic 0 0 GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 131 <0 0 31 &gic 0 0 GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 132 <0 0 32 &gic 0 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 133 <0 0 33 &gic 0 0 GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 134 <0 0 34 &gic 0 0 GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 135 <0 0 35 &gic 0 0 GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 136 <0 0 36 &gic 0 0 GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, 137 <0 0 37 &gic 0 0 GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 138 <0 0 38 &gic 0 0 GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, 139 <0 0 39 &gic 0 0 GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 140 <0 0 40 &gic 0 0 GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 141 <0 0 41 &gic 0 0 GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 142 <0 0 42 &iwb0 42 IRQ_TYPE_LEVEL_HIGH>, 143 <0 0 46 &iwb0 46 IRQ_TYPE_LEVEL_HIGH>; 144 }; 145 146#if (ENABLE_RME == 1) 147 pci: pci@40000000 { 148 interrupt-map = <0 0 0 1 &gic 0 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 149 <0 0 0 2 &gic 0 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 150 <0 0 0 3 &gic 0 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 151 <0 0 0 4 &gic 0 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 152 msi-map = <0x0 &its0 0x0 0x10000>; 153 }; 154 smmu: iommu@2b400000 { 155 interrupts = <GIC_SPI 106 IRQ_TYPE_EDGE_RISING>, 156 <GIC_SPI 111 IRQ_TYPE_EDGE_RISING>, 157 <GIC_SPI 107 IRQ_TYPE_EDGE_RISING>, 158 <GIC_SPI 109 IRQ_TYPE_EDGE_RISING>; 159 msi-parent = <&its0 0x10000>; 160 }; 161#endif /* ENABLE_RME */ 162}; 163