xref: /rk3399_ARM-atf/fdts/fvp-base-gicv3-psci-dynamiq.dts (revision 0400ccb6444838ec2ad9b74a0c37d9339cd7a478) 
1*0400ccb6SJeenu Viswambharan/*
2*0400ccb6SJeenu Viswambharan * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
3*0400ccb6SJeenu Viswambharan *
4*0400ccb6SJeenu Viswambharan * SPDX-License-Identifier: BSD-3-Clause
5*0400ccb6SJeenu Viswambharan */
6*0400ccb6SJeenu Viswambharan
7*0400ccb6SJeenu Viswambharan/dts-v1/;
8*0400ccb6SJeenu Viswambharan
9*0400ccb6SJeenu Viswambharan/include/ "fvp-base-gicv3-psci-common.dtsi"
10*0400ccb6SJeenu Viswambharan
11*0400ccb6SJeenu Viswambharan&CPU0 {
12*0400ccb6SJeenu Viswambharan	reg = <0x0 0x0>;
13*0400ccb6SJeenu Viswambharan};
14*0400ccb6SJeenu Viswambharan
15*0400ccb6SJeenu Viswambharan&CPU1 {
16*0400ccb6SJeenu Viswambharan	reg = <0x0 0x100>;
17*0400ccb6SJeenu Viswambharan};
18*0400ccb6SJeenu Viswambharan
19*0400ccb6SJeenu Viswambharan&CPU2 {
20*0400ccb6SJeenu Viswambharan	reg = <0x0 0x200>;
21*0400ccb6SJeenu Viswambharan};
22*0400ccb6SJeenu Viswambharan
23*0400ccb6SJeenu Viswambharan&CPU3 {
24*0400ccb6SJeenu Viswambharan	reg = <0x0 0x300>;
25*0400ccb6SJeenu Viswambharan};
26*0400ccb6SJeenu Viswambharan
27*0400ccb6SJeenu Viswambharan&CPU4 {
28*0400ccb6SJeenu Viswambharan	reg = <0x0 0x400>;
29*0400ccb6SJeenu Viswambharan};
30*0400ccb6SJeenu Viswambharan
31*0400ccb6SJeenu Viswambharan&CPU5 {
32*0400ccb6SJeenu Viswambharan	reg = <0x0 0x500>;
33*0400ccb6SJeenu Viswambharan};
34*0400ccb6SJeenu Viswambharan
35*0400ccb6SJeenu Viswambharan&CPU6 {
36*0400ccb6SJeenu Viswambharan	reg = <0x0 0x600>;
37*0400ccb6SJeenu Viswambharan};
38*0400ccb6SJeenu Viswambharan
39*0400ccb6SJeenu Viswambharan&CPU7 {
40*0400ccb6SJeenu Viswambharan	reg = <0x0 0x700>;
41*0400ccb6SJeenu Viswambharan};
42