1/* 2 * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7/* Configuration: max 4 clusters with up to 4 CPUs */ 8 9/dts-v1/; 10 11#define AFF 12 13#include "fvp-defs.dtsi" 14 15/memreserve/ 0x80000000 0x00010000; 16 17/ { 18}; 19 20/ { 21 model = "FVP Base"; 22 compatible = "arm,vfp-base", "arm,vexpress"; 23 interrupt-parent = <&gic>; 24 #address-cells = <2>; 25 #size-cells = <2>; 26 27 chosen { }; 28 29 aliases { 30 serial0 = &v2m_serial0; 31 serial1 = &v2m_serial1; 32 serial2 = &v2m_serial2; 33 serial3 = &v2m_serial3; 34 }; 35 36 psci { 37 compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci"; 38 method = "smc"; 39 cpu_suspend = <0xc4000001>; 40 cpu_off = <0x84000002>; 41 cpu_on = <0xc4000003>; 42 sys_poweroff = <0x84000008>; 43 sys_reset = <0x84000009>; 44 max-pwr-lvl = <2>; 45 }; 46 47 cpus { 48 #address-cells = <2>; 49 #size-cells = <0>; 50 51 CPU_MAP 52 53 idle-states { 54 entry-method = "arm,psci"; 55 56 CPU_SLEEP_0: cpu-sleep-0 { 57 compatible = "arm,idle-state"; 58 local-timer-stop; 59 arm,psci-suspend-param = <0x0010000>; 60 entry-latency-us = <40>; 61 exit-latency-us = <100>; 62 min-residency-us = <150>; 63 }; 64 65 CLUSTER_SLEEP_0: cluster-sleep-0 { 66 compatible = "arm,idle-state"; 67 local-timer-stop; 68 arm,psci-suspend-param = <0x1010000>; 69 entry-latency-us = <500>; 70 exit-latency-us = <1000>; 71 min-residency-us = <2500>; 72 }; 73 }; 74 75 CPUS 76 77 L2_0: l2-cache0 { 78 compatible = "cache"; 79 }; 80 }; 81 82 memory@80000000 { 83 device_type = "memory"; 84 reg = <0x00000000 0x80000000 0 0x7F000000>, 85 <0x00000008 0x80000000 0 0x80000000>; 86 }; 87 88 gic: interrupt-controller@2f000000 { 89 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; 90 #interrupt-cells = <3>; 91 #address-cells = <0>; 92 interrupt-controller; 93 reg = <0x0 0x2f000000 0 0x10000>, 94 <0x0 0x2c000000 0 0x2000>, 95 <0x0 0x2c010000 0 0x2000>, 96 <0x0 0x2c02F000 0 0x2000>; 97 interrupts = <1 9 0xf04>; 98 }; 99 100 timer { 101 compatible = "arm,armv8-timer"; 102 interrupts = <1 13 0xff01>, 103 <1 14 0xff01>, 104 <1 11 0xff01>, 105 <1 10 0xff01>; 106 clock-frequency = <100000000>; 107 }; 108 109 timer@2a810000 { 110 compatible = "arm,armv7-timer-mem"; 111 reg = <0x0 0x2a810000 0x0 0x10000>; 112 clock-frequency = <100000000>; 113 #address-cells = <2>; 114 #size-cells = <2>; 115 ranges; 116 frame@2a830000 { 117 frame-number = <1>; 118 interrupts = <0 26 4>; 119 reg = <0x0 0x2a830000 0x0 0x10000>; 120 }; 121 }; 122 123 pmu { 124 compatible = "arm,armv8-pmuv3"; 125 interrupts = <0 60 4>, 126 <0 61 4>, 127 <0 62 4>, 128 <0 63 4>; 129 }; 130 131 smb { 132 compatible = "simple-bus"; 133 134 #address-cells = <2>; 135 #size-cells = <1>; 136 ranges = <0 0 0 0x08000000 0x04000000>, 137 <1 0 0 0x14000000 0x04000000>, 138 <2 0 0 0x18000000 0x04000000>, 139 <3 0 0 0x1c000000 0x04000000>, 140 <4 0 0 0x0c000000 0x04000000>, 141 <5 0 0 0x10000000 0x04000000>; 142 143 #include "rtsm_ve-motherboard.dtsi" 144 }; 145 146 panels { 147 panel@0 { 148 compatible = "panel"; 149 mode = "XVGA"; 150 refresh = <60>; 151 xres = <1024>; 152 yres = <768>; 153 pixclock = <15748>; 154 left_margin = <152>; 155 right_margin = <48>; 156 upper_margin = <23>; 157 lower_margin = <3>; 158 hsync_len = <104>; 159 vsync_len = <4>; 160 sync = <0>; 161 vmode = "FB_VMODE_NONINTERLACED"; 162 tim2 = "TIM2_BCD", "TIM2_IPC"; 163 cntl = "CNTL_LCDTFT", "CNTL_BGR", "CNTL_LCDVCOMP(1)"; 164 caps = "CLCD_CAP_5551", "CLCD_CAP_565", "CLCD_CAP_888"; 165 bpp = <16>; 166 }; 167 }; 168}; 169