1/* 2 * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7/dts-v1/; 8 9/memreserve/ 0x80000000 0x00010000; 10 11/ { 12}; 13 14/ { 15 model = "FVP Base"; 16 compatible = "arm,vfp-base", "arm,vexpress"; 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 chosen { }; 22 23 aliases { 24 serial0 = &v2m_serial0; 25 serial1 = &v2m_serial1; 26 serial2 = &v2m_serial2; 27 serial3 = &v2m_serial3; 28 }; 29 30 psci { 31 compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci"; 32 method = "smc"; 33 cpu_suspend = <0xc4000001>; 34 cpu_off = <0x84000002>; 35 cpu_on = <0xc4000003>; 36 sys_poweroff = <0x84000008>; 37 sys_reset = <0x84000009>; 38 max-pwr-lvl = <2>; 39 }; 40 41 cpus { 42 #address-cells = <2>; 43 #size-cells = <0>; 44 45 cpu-map { 46 cluster0 { 47 core0 { 48 cpu = <&CPU0>; 49 }; 50 core1 { 51 cpu = <&CPU1>; 52 }; 53 core2 { 54 cpu = <&CPU2>; 55 }; 56 core3 { 57 cpu = <&CPU3>; 58 }; 59 }; 60 61 cluster1 { 62 core0 { 63 cpu = <&CPU4>; 64 }; 65 core1 { 66 cpu = <&CPU5>; 67 }; 68 core2 { 69 cpu = <&CPU6>; 70 }; 71 core3 { 72 cpu = <&CPU7>; 73 }; 74 }; 75 }; 76 77 idle-states { 78 entry-method = "arm,psci"; 79 80 CPU_SLEEP_0: cpu-sleep-0 { 81 compatible = "arm,idle-state"; 82 local-timer-stop; 83 arm,psci-suspend-param = <0x0010000>; 84 entry-latency-us = <40>; 85 exit-latency-us = <100>; 86 min-residency-us = <150>; 87 }; 88 89 CLUSTER_SLEEP_0: cluster-sleep-0 { 90 compatible = "arm,idle-state"; 91 local-timer-stop; 92 arm,psci-suspend-param = <0x1010000>; 93 entry-latency-us = <500>; 94 exit-latency-us = <1000>; 95 min-residency-us = <2500>; 96 }; 97 }; 98 99 CPU0:cpu@0 { 100 device_type = "cpu"; 101 compatible = "arm,armv8"; 102 reg = <0x0 0x0>; 103 enable-method = "psci"; 104 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 105 next-level-cache = <&L2_0>; 106 }; 107 108 CPU1:cpu@1 { 109 device_type = "cpu"; 110 compatible = "arm,armv8"; 111 reg = <0x0 0x1>; 112 enable-method = "psci"; 113 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 114 next-level-cache = <&L2_0>; 115 }; 116 117 CPU2:cpu@2 { 118 device_type = "cpu"; 119 compatible = "arm,armv8"; 120 reg = <0x0 0x2>; 121 enable-method = "psci"; 122 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 123 next-level-cache = <&L2_0>; 124 }; 125 126 CPU3:cpu@3 { 127 device_type = "cpu"; 128 compatible = "arm,armv8"; 129 reg = <0x0 0x3>; 130 enable-method = "psci"; 131 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 132 next-level-cache = <&L2_0>; 133 }; 134 135 CPU4:cpu@100 { 136 device_type = "cpu"; 137 compatible = "arm,armv8"; 138 reg = <0x0 0x100>; 139 enable-method = "psci"; 140 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 141 next-level-cache = <&L2_0>; 142 }; 143 144 CPU5:cpu@101 { 145 device_type = "cpu"; 146 compatible = "arm,armv8"; 147 reg = <0x0 0x101>; 148 enable-method = "psci"; 149 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 150 next-level-cache = <&L2_0>; 151 }; 152 153 CPU6:cpu@102 { 154 device_type = "cpu"; 155 compatible = "arm,armv8"; 156 reg = <0x0 0x102>; 157 enable-method = "psci"; 158 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 159 next-level-cache = <&L2_0>; 160 }; 161 162 CPU7:cpu@103 { 163 device_type = "cpu"; 164 compatible = "arm,armv8"; 165 reg = <0x0 0x103>; 166 enable-method = "psci"; 167 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 168 next-level-cache = <&L2_0>; 169 }; 170 171 L2_0: l2-cache0 { 172 compatible = "cache"; 173 }; 174 }; 175 176 memory@80000000 { 177 device_type = "memory"; 178 reg = <0x00000000 0x80000000 0 0x7F000000>, 179 <0x00000008 0x80000000 0 0x80000000>; 180 }; 181 182 gic: interrupt-controller@2f000000 { 183 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; 184 #interrupt-cells = <3>; 185 #address-cells = <0>; 186 interrupt-controller; 187 reg = <0x0 0x2f000000 0 0x10000>, 188 <0x0 0x2c000000 0 0x2000>, 189 <0x0 0x2c010000 0 0x2000>, 190 <0x0 0x2c02F000 0 0x2000>; 191 interrupts = <1 9 0xf04>; 192 }; 193 194 timer { 195 compatible = "arm,armv8-timer"; 196 interrupts = <1 13 0xff01>, 197 <1 14 0xff01>, 198 <1 11 0xff01>, 199 <1 10 0xff01>; 200 clock-frequency = <100000000>; 201 }; 202 203 timer@2a810000 { 204 compatible = "arm,armv7-timer-mem"; 205 reg = <0x0 0x2a810000 0x0 0x10000>; 206 clock-frequency = <100000000>; 207 #address-cells = <2>; 208 #size-cells = <2>; 209 ranges; 210 frame@2a830000 { 211 frame-number = <1>; 212 interrupts = <0 26 4>; 213 reg = <0x0 0x2a830000 0x0 0x10000>; 214 }; 215 }; 216 217 pmu { 218 compatible = "arm,armv8-pmuv3"; 219 interrupts = <0 60 4>, 220 <0 61 4>, 221 <0 62 4>, 222 <0 63 4>; 223 }; 224 225 smb { 226 compatible = "simple-bus"; 227 228 #address-cells = <2>; 229 #size-cells = <1>; 230 ranges = <0 0 0 0x08000000 0x04000000>, 231 <1 0 0 0x14000000 0x04000000>, 232 <2 0 0 0x18000000 0x04000000>, 233 <3 0 0 0x1c000000 0x04000000>, 234 <4 0 0 0x0c000000 0x04000000>, 235 <5 0 0 0x10000000 0x04000000>; 236 237 #include "rtsm_ve-motherboard.dtsi" 238 }; 239 240 panels { 241 panel@0 { 242 compatible = "panel"; 243 mode = "XVGA"; 244 refresh = <60>; 245 xres = <1024>; 246 yres = <768>; 247 pixclock = <15748>; 248 left_margin = <152>; 249 right_margin = <48>; 250 upper_margin = <23>; 251 lower_margin = <3>; 252 hsync_len = <104>; 253 vsync_len = <4>; 254 sync = <0>; 255 vmode = "FB_VMODE_NONINTERLACED"; 256 tim2 = "TIM2_BCD", "TIM2_IPC"; 257 cntl = "CNTL_LCDTFT", "CNTL_BGR", "CNTL_LCDVCOMP(1)"; 258 caps = "CLCD_CAP_5551", "CLCD_CAP_565", "CLCD_CAP_888"; 259 bpp = <16>; 260 }; 261 }; 262}; 263